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CN1938924B - PWM controller with modulator for power saving and noise reduction - Google Patents

PWM controller with modulator for power saving and noise reduction Download PDF

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Publication number
CN1938924B
CN1938924B CN2004800427247A CN200480042724A CN1938924B CN 1938924 B CN1938924 B CN 1938924B CN 2004800427247 A CN2004800427247 A CN 2004800427247A CN 200480042724 A CN200480042724 A CN 200480042724A CN 1938924 B CN1938924 B CN 1938924B
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China
Prior art keywords
voltage
transistor
current
output
input terminal
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Expired - Fee Related
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CN2004800427247A
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Chinese (zh)
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CN1938924A (en
Inventor
杨大勇
陈秋麟
林振宇
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Fairchild Taiwan Corp
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System General Corp Taiwan
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/40—Means for preventing magnetic saturation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present invention provides a modulator of a PWM controller for saving power and reducing noise under light load and no load conditions. The maximum on-time is kept constant and the bias current of the oscillator in the PWM controller is modulated to achieve off-time modulation. The bias current is a function of the supply voltage and the feedback voltage from the voltage feedback loop. The threshold voltage defines the level of the light load. The limit voltage defines the low level of the supply voltage. The bias current synthesizer generates a bias current. Reducing the bias current increases the off time of the switching cycle. Once the feedback voltage decreases below the threshold voltage, the bias current decreases linearly and the off-time of the switching cycle gradually increases. When the supply voltage is lower than the limit voltage, the bias current increases and determines the maximum off-time of the switching cycle. Keeping the maximum on-time constant and increasing the switching period only by increasing the off-time can prevent saturation of the magnetic components (e.g., inductors and transformers). In addition, the control circuit disables the oscillator when the PWM frequency may fall into the acoustic band, so noise can be greatly reduced at light load and no load.

Description

Has the PWM controller that is used to save power and reduces the modulator of noise
Technical field
The present invention relates to a kind of switching power supply, and more particularly relate to switching power supply pulse width modulation (pulse width modulation, PWM).
Background technology
The PWM controller is that the integrated circuit that switches duty cycle is controlled and regulated to a kind of switching power supply that is used for.When standing the environment adjusting, require the power system design of computer and other electric product to satisfy power management and energy conservation standard.Power management be to operating period consumed power system manage, and during non-operation mode, only consume power seldom.For the power management applications in the power supply unit, the main power of how saving under underload and the immunization with gD DNA vaccine.A target of PWM modulator is province's power consumption of optimization joint and reduces noise when frequency of oscillation falls into sonic-frequency band.
Fig. 1 illustrates and typically speeds to return (flyback) power supply unit circuit, wherein 100 controls of PWM controller and adjusting power output.When the power-on supply, PWM controls startup.Via 220 chargings of 210 pairs of capacitors of resistor, up to the supply voltage V of PWM controller 100 CCReach and start threshold value (start-threshold).PWM controller 100 begins output pwm signals subsequently, and drives whole power supply unit.After startup, the assisted bias winding of transformer 400 (auxiliary biaswinding) provide supply voltage V via rectifier 230 CC Resistor 240 is the voltage signal that is used for PWM control and power overload protection with the switch current information translation of transformer 400.In case the boost voltage of transformer 400 can't be provided for supply voltage V CCEnough power so that supply voltage V CCBe lower than outage threshold (stop-threshold), thereby close PWM controller 100.Feedback voltage V FBBe taken from the output of optical coupler 250.The input of optical coupler 250 is connected to the output V of power supply via resistor 290 and Zener diode 280 O, to form feedback loop.Via the control of feedback loop, voltage V FBT turn-on time via PWM controller 100 control pwm signals ONDuration, and the decision power output.
The power loss of power supply unit is an important problem, and the main loss and the switching frequency F that comprise magnetic core of transformer loss, transistor handoff loss and buffer (snubber) power loss are proportional.Switching cycle T is the inverse of switching frequency F, T=1/F.Increase the loss of switching cycle T cpable of lowering power.Yet, be the size that prevents that transformer is saturated and dwindle power supply unit, necessarily require short T turn-on time ONWork as T ONDuration when unrestricted, magnet assembly (for example inductor and transformer) will cause saturated generation, and will cause the overstress of switching device shifter (for example transistor and rectifier) to damage (over-stress damage).Though the power consumption of power supply unit will reduce in response to reducing of switching frequency F, when switching frequency falls into sonic-frequency band (for example 200Hz to 8KHz) under underload and immunization with gD DNA vaccine, will produce audible noise.Therefore another target is to reduce noise under underload and immunization with gD DNA vaccine when switching frequency falls into sonic-frequency band.
Disclosed the certain methods that increases regulator efficiency in the prior art, for example changed switching frequency and enter " pulse-skip (pulse-skipping) " pattern according to loading condition.For example, United States Patent (USP) the 6th, 100, No. 675 " SWITCHING REGULATOR CAPABLE OF INCREASINGREGULATOR EFFICIENCY UNDER LIGHT LOAD " discloses a kind of oscillation frequency control circuit, and it can change the frequency of oscillation of pierce circuit in response to loading condition.And at United States Patent (USP) the 6th, 366, disclose another kind of method in 070B1 number " SWITCHING VOLTAGE REGULATOR WITH DUAL MODULATIONCONTROL SCHEME ", it has disclosed the adjuster that uses three kinds of operator schemes, this adjuster is operated with constant switching frequency under the heavy duty situation, under the medium load situation, use the double modulation controlling mechanism, and under light load condition, enter " pulse-skip ".The shortcoming of aforementioned prior art is: (1) changes switching frequency and does not limit and may cause the saturated of magnet assembly maximum turn-on time, and causes the overstress of switching device shifter (for example transistor and rectifier) to damage; (2) modulation of switching frequency is controlled by loading condition only, and and independent of power voltage.Because in order to save more power, so switching frequency can fall lowly excessively, so the assisted bias winding of transformer or inductor may not provide enough power to be used for the supply voltage of PWM controller under underload and immunization with gD DNA vaccine.PWM is controlled in this case and may works improperly.Therefore, frequency modulation(FM) is associated with two kinds of loading conditions and supply voltage; (3) under underload and immunization with gD DNA vaccine, switching frequency may be reduced to sonic-frequency band.If magnet assembly does not flood (impregnated) well, the sonic-frequency band switching frequency may produce noise so.
For preventing the above shortcoming of prior art, need preferably a kind of and muting device is used to improve efficient and saves power consumption under underload and immunization with gD DNA vaccine.
Summary of the invention
The invention provides a kind of Pwm controller that is used to save power and reduces the modulator of noise that has, it comprises: a bias current synthesizer, it has four input terminals and two lead-out terminals, first lead-out terminal of wherein said bias current synthesizer produces a bias current determining the turn-off time of a pulse width modulation switching cycle, and second lead-out terminal of described bias current synthesizer is exported a reference current; An oscillator, it has two input terminals, described first lead-out terminal that first input end of wherein said oscillator is connected to described bias current synthesizer is used for the pulse signal that pulse width modulation is switched with generation, the turn-on time of described pulse signal be turn-off time of constant and described pulse signal along with described bias current reduces to increase, second input terminal of described oscillator is used to enable/the described oscillator of stopping using; A control circuit, it has an input terminal and a lead-out terminal, the described input terminal of wherein said control circuit is connected to described reference current, described reference current is taken from described second lead-out terminal of described bias current synthesizer, and the described lead-out terminal of described control circuit is connected to described second input terminal of described oscillator; A rest-set flip-flop, it is used to produce on-off signal, and wherein said rest-set flip-flop is set by described pulse signal, and is reset by a FEEDBACK CONTROL; One and door, it has two input terminals, and wherein said first input end with door is connected to described pulse signal, and second input terminal described and door is connected to described on-off signal; A feedback voltage, it is connected to the first input end of described bias current synthesizer, wherein said feedback voltage is taken from the voltage feedback loop of power supply unit, in order to the described turn-on time of controlling described pulse width modulating signal and the output of regulating power supply unit; Threshold voltage, it is connected to second input of described bias current synthesizer, with the level under the decision light load condition; A deboost, it is connected to the level of the 3rd input of described bias current synthesizer with the decision low supply voltage, wherein when the pulse width modulation switching frequency reduces under described underload and immunization with gD DNA vaccine, described deboost changes in each pulse width modulation switching cycle, and this influences described bias current and produces variable pulse width modulation switching frequency; And supply voltage, it is connected to the four-input terminal of described bias current synthesizer, wherein said supply voltage is the supply voltage of described Pwm controller, wherein said bias current is described feedback voltage, described threshold voltage, the function of described supply voltage and described deboost, make when described feedback voltage is lower than described threshold voltage, described bias current begins along with reducing of described feedback voltage to reduce, if and described supply voltage is lower than described deboost, described bias current will begin along with reducing of described supply voltage to increase.
Bias current via oscillator in the modulation (PWM) controller reaches the modulation of realization turn-off time.Remain constant the maximum turn-on time of pwm signal.Reduce bias plasma and fail to be convened for lack of a quorum the turn-off time of increase switching cycle, so switching cycle is prolonged.To be used as variable to get in touch from the feedback voltage and the supply voltage of voltage feedback loop with the turn-off time chopping phase.Bias current is modulated to the function of feedback voltage and supply voltage.Threshold voltage is the constant of the underloaded level of definition.The low level of deboost definition supply voltage.Deduct threshold voltage and produce first differential signal by feedback voltage.Deduct the supply voltage of decay and produce second differential signal by deboost.First differential signal and second differential signal and through being converted into bias current.By the limiter limits bias current to set the minimum switching cycle under normal load and the full load situation.Be lower than threshold voltage in case feedback voltage is reduced to, bias current reduces so, and the turn-off time of switching cycle prolongs continuously.When supply voltage was lower than deboost, bias current increased, and the maximum turn-off time of decision switching cycle.
Control circuit provides two inlet voltages.Reference resistor will change voltage signal into from the reference current that bias current obtains and be input to the input of control circuit.The level of the first inlet voltage decision audio frequency switching frequency.When switching frequency falls into sonic-frequency band under underload and immunization with gD DNA vaccine, control circuit will export the OFF signal to cut out the oscillator of PWM controller.The level of second inlet voltage decision startup oscillator of PWM controller.In case supply voltage reduces or feedback voltage increases, and the input voltage of control circuit is greater than the second inlet voltage, and oscillator will restart work once more so.
Advantageously, the self adaptation turn-off time is modulated the power consumption of having improved efficient and save power supply under underload and immunization with gD DNA vaccine.Simultaneously, when switching frequency fell into sonic-frequency band, the control circuit of using among the present invention cut out oscillator, to have reduced noise significantly.
Should be appreciated that, aforementioned general describe and following detailed description is exemplary, and hope is the same with claims that further explanation of the present invention is provided.
Description of drawings
Comprise accompanying drawing so that further understanding of the present invention to be provided, and it incorporates and constitutes the part of this specification into.Graphic explanation embodiments of the invention, and together with describing in order to explain principle of the present invention.In graphic,
Fig. 1 illustrates the circuit of typically speeding to return of power supply unit.
Fig. 2 explanation is according to the block diagram of the preferred embodiment of self adaptation of the present invention turn-off time modulator.
Fig. 3 explicit declaration is according to the circuit diagram of the preferred embodiment of the oscillator shown in Fig. 2 of the present invention.
Fig. 4 illustrates the circuit diagram according to the preferred embodiment of the bias current synthesizer shown in Fig. 2 of the present invention.
Embodiment
Fig. 2 illustrates the block diagram of self adaptation turn-off time modulator according to an embodiment of the invention.Bias current synthesizer 10 produces the bias current I that is used for oscillator 30 MDecide the turn-off time of pwm signal.Adder 11 is with feedback voltage V FBDeduct threshold voltage V AThe back produces the first differential signal 11a.The output of adder 11 is connected to the input of limiter 22.Adder 12 is with deboost V XDeduct supply voltage V CCThrough attenuator α decay and voltage after produce the second differential signal 12a.The output of adder 12 is connected to the input of limiter 24.The output of limiter 22 and limiter 24 is connected respectively to two inputs of adder 13.The voltage 13a that voltage commentaries on classics current converter 15 will obtain from the output of adder 13 changes current signal 15a into.This current signal 15a is limited to produce modulated bias current I by limiter 26 MReduce bias current I MThe cycle of oscillation of oscillator 30 will be prolonged.Oscillator 30 output pulse signal V PWith driving S-R register 41, and the initial PWM cycle.As induction by current input V SBe higher than feedback voltage V FBThe time, via the comparator 45 S-R register 41 of resetting.Pulse signal V PFor logic low interval scale oscillator 30 is in the turn-off time.Guarantee to close with door (AND gate) 43 in the output of the turn-off time of oscillator 30 period P WM signal.
Bias current I MBe supply voltage V CCAnd feedback voltage V FBFunction.
S A＝(V FB-V A)×K A (1)
S B＝[V X-(α·V CC)]×K B (2)
I M＝(S A+S B)×K C (3)
In above equation, the scope of exporting is restricted to (0≤S A≤ N A), (0≤S B≤ N B) and (0≤I M≤ I MAX), K CIt is the transfer ratio that voltage changes current converter 15.
Limiter 22 is K in proportion AThe convergent-divergent first differential signal 11a, and with its export-restriction zero to the first maximum N AScope in.Limiter 24 is K in proportion BThe convergent-divergent second differential signal 12a, and with its export-restriction zero to the second maximum N BScope in.Limiter 26 changes voltage the export-restriction of current converter 15 and arrives maximum current I zero MAXScope in, under normal load and full load situation, to set minimum switching cycle.In case feedback voltage V FBReduce to and be lower than threshold voltage V A, bias current I so MAccording to K ASlope and N AAnd reduce.And the turn-off time of switching cycle increases continuously.When the supply voltage (α VCC) of decaying is lower than deboost V XThe time, bias current I MAccording to K BSlope and N BAnd increasing, and the maximum turn-off time of decision switching cycle.
Fig. 3 illustrates an embodiment according to oscillator 30 of the present invention shown in Figure 2.Obtain pulse signal V from the output of NAND gate (NAND gate) 35 PIn initial condition, be applied to capacitor C TBVoltage be zero.The output of comparator 31 outputs to logic high signal the input of NAND gate 34.The output of comparator 32 outputs to logic low signal the input of NAND gate 35.The output of NAND gate 35 keeps logic high.NAND gate 34 output logic low signals, and drive not gate (NOT gate) 33 connection switches 36.Constant current source I CBegin capacitor C TBCharging.Work as C TBOn voltage greater than V HBThe time, the high signal of NAND gate 34 outputs is with cut-off switch 36, and connection switch 37 comes capacitor C TBDischarge.Transistor 39 is from flowing through the bias current I of transistor 38 MThe mirror discharging current.This discharging current decision V PThe turn-off time of pulse signal.Therefore, regulate bias current I MCan realize the turn-off time modulation of oscillator 30.Control turn-on time of switching cycle by feedback loop, thereby regulate the power output of power supply.
Transistor 40 is used to block the bias current I of oscillator 30 MWhen switching frequency falls into sonic-frequency band, will connect transistor 40, and stop bias current to flow into oscillator 30.Constant current source I CThe maximum turn-on time of decision switching cycle.Only increase switching cycle and can prevent that magnet assembly (for example inductor and transformer) is saturated via the duration that increases the turn-off time.The maximum turn-on time of (T of switching cycle ON (max)) and turn-off time (T OFF), and the switching frequency of pwm signal (F) is expressed as follows:
T ON(max)＝[(V HB-V L)×C TB]/I C (4)
T OFF＝[(V HB-V L)×C TB)]/I M (5)
F = 1 T ON + T OFF - - - ( 6 )
Fig. 4 illustrates the embodiment of the bias current synthesizer 10 of PWM controller, and it comprises: constant current source I TFirst current mirror of forming by transistor 71 and transistor 73, second current mirror of forming by transistor 81 and transistor 83, the 3rd current mirror of forming by transistor 88 and transistor 89, first buffer amplifier (buffer amplifier), 77, the second buffer amplifiers, 87, the first operational amplifiers (op amp) 76, first voltage changes current transistor 75, second operational amplifier (op amp), 86, the second voltages change current transistor 85, the first resistors 72 (R72), second resistor 82 (R82), by the attenuator that the 3rd resistor 91 (R91) and the 4th resistor 92 (R92) are formed, first switch 95, comparator 93, second switch 96, reference resistor R FWith not gate 94.
Feedback voltage V FBBe connected to the positive input terminal of first operational amplifier 76.Threshold voltage V ABe connected to the positive input terminal of first buffer amplifier 77.The output of first buffer amplifier 77 is connected to the negative input end of first operational amplifier 76 via first resistor 72.The source electrode of first voltage commentaries on classics current transistor 75 is connected to the negative input end of first operational amplifier 76.The output of first operational amplifier 76 is connected to the grid that first voltage changes current transistor 75, is used to form first source follower (source-follow circuit) and drives first resistor 72.The drain electrode of first voltage commentaries on classics current transistor 75 is connected to the drain electrode of mirrored transistor 71.The grid of the drain and gate of mirrored transistor 71 and mirrored transistor 73 links together.The source electrode of the source electrode of mirrored transistor 71 and mirrored transistor 73 is connected to constant current source I T
Deboost V XBe connected to the positive input terminal of second operational amplifier 86.Supply voltage V CCBe connected to the positive input terminal of second buffer amplifier 87 via resistor 91.Resistor 92 is connected between the positive input terminal and ground connection of second buffer amplifier 87.The output of second buffer amplifier 87 is connected to the negative input end of second operational amplifier 86 via second resistor 82.The source electrode of second voltage commentaries on classics current transistor 85 is connected to the negative input end of second operational amplifier 86.The output of second operational amplifier 86 is connected to the grid that second voltage changes current transistor 85, drives second resistor 82 to be used to form second source follower.The drain electrode of second voltage commentaries on classics current transistor 85 is connected to the drain electrode of mirrored transistor 81.The grid of the drain and gate of mirrored transistor 81 and mirrored transistor 83 links together.The source electrode of the source electrode of mirrored transistor 81 and mirrored transistor 83 is connected to constant current source I T
The drain electrode of mirrored transistor 73 and mirrored transistor 83 links together and the output bias electric current I MIn first operational amplifier 76, feedback voltage V FBDeduct threshold voltage V AThe back produces first output, and this first is input to the grid of first voltage commentaries on classics current transistor 75 and is converted into first electric current I 1The first current mirror mirror, first electric current I 1And via the drain electrode output current I of mirrored transistor 73 FBDeboost V XDeduct supply voltage V via the attenuator decay CCThe back is to produce second output, and this second output is connected to second voltage to be changeed the grid of current transistor 85 and be converted into second electric current I 2The second current mirror mirror, second electric current I 2And the drain electrode output current I by mirrored transistor 83 VCCElectric current I FBWith electric current I VCCClose and form bias current I MWork as feedback voltage V FBLower and supply voltage V CCWhen higher, bias current I MLinearity reduces, and prolongs the turn-off time of the cycle of oscillation of the oscillator 30 shown in Fig. 2.On the contrary, work as feedback voltage V FBHigher and/or supply voltage V CCWhen low, I MIncrease gradually.
I FB＝[(V FB-V A)/R 72]×M A (7)
I VCC＝[(V X-α·V CC)/R 82]×M B (8)
I M＝I FB+I VCC (9)
In above equation, with I MScope be restricted to (0≤I M≤ I T), M ABe the transfer ratio of first current mirror, M BBe the transfer ratio of second current mirror, α equals [R92/ (R91+R92)].The minimum turn-off time of pwm signal is by constant current source I TDecision is as shown in equation (5) and (7) to (9).
The 3rd current mirror is made up of mirrored transistor 88 and mirrored transistor 89.The grid of mirrored transistor 88 is connected to the grid of mirrored transistor 71.The grid of mirrored transistor 89 is connected to the grid of mirrored transistor 81.The source electrode of the source electrode of mirrored transistor 88 and mirrored transistor 89 is connected to constant current source I TThe drain electrode of the drain electrode of mirrored transistor 88 and mirrored transistor 89 links together with output and bias current I MThe proportional reference current I of variation F
Control circuit 28 shown in Fig. 4 comprises comparator 93, first switch 95, second switch 96, reference resistor R FWith not gate 94.Reference resistor R FBe connected to the negative input end of comparator 93.The output of comparator 93 is connected to the control terminal of second switch 96 and the input terminal of not gate 94.The lead-out terminal of not gate 94 is connected to the control terminal of first switch 95.The first inlet voltage V T1Be connected to the input terminal of first switch 95.The second inlet voltage V T2Be connected to the input terminal of second switch 96.The output of first switch 95 and second switch 96 is connected to the positive input terminal of comparator 93 jointly.Under normal load condition, comparator 93 is output as logic low-voltage.Not gate 94 these logic low-voltages of conversion, and produce logic high voltage to connect first switch 95, this makes the inlet voltage V that wins T1Be connected to the positive input terminal of comparator 93.The first inlet voltage V T1The definition switching frequency falls into the threshold value of sonic-frequency band.In case switching frequency reduces and when falling into audio frequency under underload and immunization with gD DNA vaccine, reference current I FWill be along with bias current I MReduce reduce pro rata.Reference resistor R FWith reference current I FBe converted to the reference voltage V of comparator 93 negative input end FIn case voltage V FBe lower than the first inlet voltage V T1, just with high (OFF) signal that turn-offs of output logic, it disconnects first switch 95 and connects second switch 96 comparator.This OFF signal is connected to the grid of the transistor 40 shown in Fig. 3.The source electrode of transistor 40 is connected to ground connection.The drain electrode of transistor 40 is connected to the drain electrode of mirrored transistor 38.Logic high OFF signal turns on transistor 40 is also blocked the bias current of oscillator.The vibration of the oscillator 30 shown in Fig. 2 is not having bias current I MIn time, will stop.Make feedback voltage V when the load increase FBIncrease or supply voltage V CCWhen reducing, reference current I FWill with bias current I MIncrease pro rata.The second inlet voltage V T2The definition threshold value is to open the vibration of beginning oscillator 30 again.In case reference voltage V FThe high level cadre second inlet voltage V T2, comparator 93 with the output logic low-voltage to disconnect transistor 40 and second switch 96.The low logic voltage of not gate 94 counter-rotating to be connecting first switch 95, and makes the first inlet voltage V once more T1Be connected to the positive input terminal of comparator 93.Logic low OFF signal makes bias current I MFlow into once more in the oscillator 30.Therefore, oscillator 30 will restart vibration according to the variation of loading condition.
As previously discussed, the PWM controller that comprises the modulation of self adaptation turn-off time of the present invention can reduce the power consumption of power supply under underload and immunization with gD DNA vaccine.In addition, under underload and the immunization with gD DNA vaccine when the PWM frequency falls into sonic-frequency band, the control by control circuit will reduce noise significantly.
Be understood by those skilled in the art that, under the situation of scope of the present invention or spirit, can making various modifications and change structure of the present invention.In view of the above, wish the present invention contain fall into above claim and equivalent thereof scope in modification of the present invention and change.

Claims (4)

1.一种具有用于节省功率和减少噪声的调制器的脉冲宽度调制控制器，包括：1. A pulse width modulation controller with a modulator for power saving and noise reduction, comprising: 一个偏压电流合成器，其具有四个输入端子和两个输出端子，其中所述偏压电流合成器的第一输出端子产生一个偏压电流以决定一个脉冲宽度调制切换周期的关断时间，且所述偏压电流合成器的第二输出端子输出一参考电流；a bias current combiner having four input terminals and two output terminals, wherein the first output terminal of the bias current combiner generates a bias current to determine an off time of a pulse width modulation switching cycle, And the second output terminal of the bias current synthesizer outputs a reference current; 一个振荡器，其具有两个输入端子，其中所述振荡器的第一输入端子连接到所述偏压电流合成器的所述第一输出端子以产生用于脉冲宽度调制切换的一个脉冲信号，所述脉冲信号的接通时间为常数且所述脉冲信号的关断时间随着所述偏压电流减小而增加，所述振荡器的第二输入端子用于启用/停用所述振荡器；an oscillator having two input terminals, wherein a first input terminal of said oscillator is connected to said first output terminal of said bias current synthesizer to generate a pulse signal for pulse width modulation switching, The on-time of the pulse signal is constant and the off-time of the pulse signal increases as the bias current decreases, the second input terminal of the oscillator is used to enable/disable the oscillator ; 一个控制电路，其具有一个输入端子和一个输出端子，其中所述控制电路的所述输入端子连接到所述参考电流，所述参考电流取自所述偏压电流合成器的所述第二输出端子，所述控制电路的所述输出端子连接到所述振荡器的所述第二输入端子；a control circuit having an input terminal and an output terminal, wherein the input terminal of the control circuit is connected to the reference current taken from the second output of the bias current combiner terminal, the output terminal of the control circuit is connected to the second input terminal of the oscillator; 一个RS触发器，其用于产生接通-断开信号，其中所述RS触发器由所述脉冲信号设定，并由一个反馈控制所重置；an RS flip-flop for generating an on-off signal, wherein said RS flip-flop is set by said pulse signal and reset by a feedback control; 一个与门，其具有两个输入端子，其中所述与门的第一输入端子连接到所述脉冲信号，且所述与门的第二输入端子连接到所述接通-断开信号；an AND gate having two input terminals, wherein a first input terminal of the AND gate is connected to the pulse signal, and a second input terminal of the AND gate is connected to the on-off signal; 一个反馈电压，其连接到所述偏压电流合成器的第一输入端，其中所述反馈电压取自于电源供应器的电压反馈回路，用以控制所述脉冲宽度调制信号的所述接通时间并调节电源供应器的输出；a feedback voltage connected to the first input terminal of the bias current combiner, wherein the feedback voltage is obtained from a voltage feedback loop of a power supply to control the switching on of the pulse width modulation signal time and regulate the output of the power supply; 阈值电压，其连接到所述偏压电流合成器的第二输入端，以决定轻负载情况下的电平；a threshold voltage connected to the second input terminal of the bias current combiner to determine the level under light load conditions; 一个限制电压，其连接到所述偏压电流合成器的第三输入端以决定低电源电压的电平，其中当脉冲宽度调制切换频率在所述轻负载以及无负载情况下减小时，所述限制电压在每个脉冲宽度调制切换周期中改变，此影响所述偏压电流产生可变的脉冲宽度调制切换频率；以及a limiting voltage connected to the third input of the bias current combiner to determine the level of the low supply voltage, wherein when the PWM switching frequency is reduced under the light load and no load conditions, the the limiting voltage is varied in each PWM switching cycle, which affects the bias current to produce a variable PWM switching frequency; and 一个电源电压，其连接到所述偏压电流合成器的第四输入端，其中所述电源电压是所述脉冲宽度调制控制器的电源电压，其中所述偏压电流是所述反馈电压、所述阈值电压、所述电源电压以及所述限制电压的函数，使得在所述反馈电压低于所述阈值电压时，所述偏压电流随着所述反馈电压的减小而开始减小，且如果所述电源电压低于所述限制电压，所述偏压电流将随着所述电源电压的减小而开始增加。a supply voltage connected to a fourth input of the bias current combiner, wherein the supply voltage is the supply voltage of the pulse width modulation controller, wherein the bias current is the feedback voltage, the The function of the threshold voltage, the supply voltage and the limit voltage, so that when the feedback voltage is lower than the threshold voltage, the bias current starts to decrease as the feedback voltage decreases, and If the supply voltage is lower than the limit voltage, the bias current will start to increase as the supply voltage decreases. 2.根据权利要求1所述的脉冲宽度调制控制器，其中所述偏压电流合成器包括：2. The pulse width modulation controller of claim 1, wherein the bias current combiner comprises: 一个第一加法器，其操作地将所述反馈电压减去所述阈值电压；a first adder operative to subtract the threshold voltage from the feedback voltage; 一个衰减器，其用于衰减所述电源电压；an attenuator for attenuating the supply voltage; 一个第二加法器，其操作地将所述限制电压减去所述衰减器的输出；a second adder operative to subtract the output of the attenuator from the limiting voltage; 一个第一限制器，其用于将所述第一加法器的一输出按比例缩放并限制为一第一差分信号，其中所述第一差分信号的幅值在零至一第一最大值的范围内，其中所述第一最大值决定所述偏压电流随着所述反馈电压的变化而改变的斜率；a first limiter for scaling and limiting an output of the first adder to a first differential signal, wherein the amplitude of the first differential signal is between zero and a first maximum value range, wherein the first maximum value determines the slope of the bias current as the feedback voltage changes; 一个第二限制器，其用于将所述第二加法器的一输出按比例缩放并限制为一第二差分信号，其中所述第二差分信号的幅值在零至一第二最大值的范围内，其中所述第二最大值决定所述偏压电流随着所述电源电压的变化而改变的斜率；a second limiter for scaling and limiting an output of the second adder to a second differential signal, wherein the amplitude of the second differential signal is between zero and a second maximum value range, wherein the second maximum value determines the slope of the bias current as the supply voltage changes; 一个第三加法器，其将所述第一差分信号与所述第二差分信号相加；a third adder that adds the first differential signal to the second differential signal; 一个电压转电流转换器，其将所述第三加法器的一输出转换为一个电压转电流的电流；以及a voltage-to-current converter that converts an output of said third summer into a voltage-to-current current; and 一个第三限制器，其用于限制所述电压转电流的电流，以产生所述参考电流和所述偏压电流，其中所述偏压电流的幅值在零至电流最大值的范围内，以在正常负载和满负载情况下设定最小切换周期。a third limiter, which is used to limit the current of the voltage-to-current to generate the reference current and the bias current, wherein the magnitude of the bias current is in the range of zero to the current maximum value, To set the minimum switching period under normal load and full load conditions. 3.根据权利要求1所述的脉冲宽度调制控制器，其中所述偏压电流合成器包括：3. The pulse width modulation controller of claim 1, wherein said bias current combiner comprises: 一个第一运算放大器，其具有一个正输入端子、一个负输入端子以及一个输出端子，其中所述第一运算放大器的所述正输入端连接到所述反馈电压；a first operational amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first operational amplifier is connected to the feedback voltage; 一个第一缓冲放大器，其具有一个正输入端子、一个负输入端子以及一个输出端子，其中所述第一缓冲放大器的所述负输入端子连接到其所述输出端，且所述第一缓冲放大器的所述正输入端子连接到所述阈值电压；a first buffer amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the first buffer amplifier is connected to the output terminal thereof, and the first buffer amplifier The positive input terminal of is connected to the threshold voltage; 一个第一电压转电流晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第一电压转电流晶体管之所述栅极由所述第一运算放大器的所述输出端子驱动，且所述第一电压转电流晶体管的所述源极连接到所述第一运算放大器的所述负输入端子，从而形成一个第一源极跟随电路；a first voltage-to-current transistor having a gate, a source, and a drain, wherein the gate of the first voltage-to-current transistor is driven by the output terminal of the first operational amplifier, and the source of the first voltage-to-current transistor is connected to the negative input terminal of the first operational amplifier, thereby forming a first source follower circuit; 一个第一电阻器，其连接在所述第一缓冲放大器的所述输出与所述第一电压转电流晶体管的所述源极之间，其中所述反馈电压经由所述第一电阻器减去所述阈值电压，而产生一个第一电流；a first resistor connected between the output of the first buffer amplifier and the source of the first voltage-to-current transistor, wherein the feedback voltage is subtracted via the first resistor the threshold voltage to generate a first current; 一个衰减器；an attenuator; 一个第二运算放大器，其具有一个正输入端子、一个负输入端子以及一个输出端子，其中所述第二运算放大器的所述正输入端子连接到所述限制电压；a second operational amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second operational amplifier is connected to the limited voltage; 一个第二缓冲放大器，其具有一个正输入端子、一个负输入端子以及一个输出端子，其中所述第二缓冲放大器的所述负输入端子连接到其所述输出端子，且所述第二缓冲放大器的所述正输入端子经由所述衰减器连接到所述电源电压；a second buffer amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the second buffer amplifier is connected to the output terminal thereof, and the second buffer amplifier the positive input terminal of is connected to the supply voltage via the attenuator; 一个第二电压转电流晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第二电压转电流晶体管的所述栅极由所述第二运算放大器的所述输出来驱动，且所述第二电压转电流晶体管的所述源极连接到所述第二运算放大器的所述负输入端，从而形成一个第二源极跟随电路；a second voltage-to-current transistor having a gate, a source, and a drain, wherein said gate of said second voltage-to-current transistor is driven by said output of said second operational amplifier, and the source of the second voltage-to-current transistor is connected to the negative input terminal of the second operational amplifier, thereby forming a second source follower circuit; 一个第二电阻器，其连接在所述第二缓冲放大器的所述输出端子与所述第二电压转电流晶体管的所述源极之间，其中所述限制电压经由第二电阻器减去所述衰减器衰减的所述电源电压，而产生一个第二电流；a second resistor connected between the output terminal of the second buffer amplifier and the source of the second voltage-to-current transistor, wherein the limiting voltage is subtracted by the second resistor said power supply voltage attenuated by said attenuator to generate a second current; 一个第一输入晶体管，其具有一个栅极、一个源极以及一个漏极；a first input transistor having a gate, a source and a drain; 一个第一输出晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第一输入晶体管的所述源极和所述第一输出晶体管的所述源极连接在一起，其中所述第一电压转电流晶体管的所述漏极、所述第一输入晶体管的所述漏极、所述第一输入晶体管的所述栅极以及所述第一输出晶体管的所述栅极连接在一起以形成一个第一镜像放大器，其中所述第一电流驱动所述第一镜像放大器以产生一个镜射的回授电流；a first output transistor having a gate, a source and a drain, wherein the source of the first input transistor and the source of the first output transistor are connected together, wherein the The drain of the first voltage-to-current transistor, the drain of the first input transistor, the gate of the first input transistor, and the gate of the first output transistor are connected to together to form a first mirror amplifier, wherein the first current drives the first mirror amplifier to generate a mirrored feedback current; 一个第二输入晶体管，其具有一个栅极、一个源极以及一个漏极；a second input transistor having a gate, a source and a drain; 一个第二输出晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第二输入晶体管的所述源极和所述第二输出晶体管的所述源极连接在一起，其中所述第二电压转电流晶体管的所述漏极、所述第二输入晶体管的所述漏极、所述第二输入晶体管的所述栅极以及所述第二输出晶体管的所述栅极连接在一起以形成一个第二镜像放大器，其中所述第二电流驱动所述第二镜像放大器以产生一个镜射的电源电流；a second output transistor having a gate, a source and a drain, wherein the source of the second input transistor and the source of the second output transistor are connected together, wherein the The drain of the second voltage-to-current transistor, the drain of the second input transistor, the gate of the second input transistor, and the gate of the second output transistor are connected to together to form a second mirror amplifier, wherein the second current drives the second mirror amplifier to generate a mirrored supply current; 一个第三输出晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第三输出晶体管的所述栅极连接到所述第一输入晶体管的所述栅极，所述第三输出晶体管的所述源极连接到所述第一输入晶体管的所述源极；a third output transistor having a gate, a source and a drain, wherein the gate of the third output transistor is connected to the gate of the first input transistor, the third the source of an output transistor is connected to the source of the first input transistor; 一个第四输出晶体管，其具有一个栅极、一个源极以及一个漏极，其中所述第四输出晶体管的所述栅极连接到所述第二输入晶体管的所述栅极，所述第四输出晶体管的所述源极连接到所述第二输入晶体管的所述源极，所述第四输出晶体管的所述漏极和所述第三输出晶体管的所述漏极连接在一起以产生所述参考电流；以及a fourth output transistor having a gate, a source and a drain, wherein the gate of the fourth output transistor is connected to the gate of the second input transistor, the fourth The source of the output transistor is connected to the source of the second input transistor, the drain of the fourth output transistor and the drain of the third output transistor are connected together to generate the the above reference current; and 一个限制电流源，其连接到所述第一输入晶体管的所述源极、所述第一输出晶体管的所述源极、所述第二输入晶体管的所述源极、所述第二输出晶体管的所述源极、所述第三输出晶体管的所述源极以及所述第四输出晶体管的所述源极，用于限制所述偏压电流的最大输出电流，其中所述第一输出晶体管的所述漏极和所述第二输出晶体管的所述漏极连接在一起，以对所述镜射的回授电流与所述镜射的电源电流求和并产生所述偏压电流。a limited current source connected to said source of said first input transistor, said source of said first output transistor, said source of said second input transistor, said second output transistor The source of the third output transistor and the source of the fourth output transistor are used to limit the maximum output current of the bias current, wherein the first output transistor The drain of the second output transistor and the drain of the second output transistor are connected together to sum the mirrored feedback current and the mirrored supply current to generate the bias current. 4.根据权利要求1所述的脉冲宽度调制控制器，其中所述控制电路包括：4. The pulse width modulation controller of claim 1, wherein the control circuit comprises: 一个第一开关，其具有一个输入端子、一个输出端子以及一个控制端子；a first switch having an input terminal, an output terminal and a control terminal; 一个第二开关，其具有一个输入端子、一个输出端子以及一个控制端子；a second switch having an input terminal, an output terminal and a control terminal; 一个参考电阻器，其用于将所述参考电流转换为一个参考电压；a reference resistor for converting said reference current into a reference voltage; 一个非门，其具有连接到所述第一开关的所述控制端子的一个输出端子，以及一个输入端子；以及a NOT gate having an output terminal connected to said control terminal of said first switch, and an input terminal; and 一个比较器，其具有一个负输入端子、一个正输入端子以及一个输出端子，其中所述比较器的所述负输入端子连接到所述参考电阻器，所述比较器的所述正输入端子连接到所述第一开关和所述第二开关的所述输出端子，所述比较器的所述输出端子连接到所述非门的所述输入端子以及所述第二开关的所述控制端子，且所述输出端子用以启用和停用所述振荡器的振荡，所述第一开关的所述输入端子连接到一个第一入口电压，所述第二开关的所述输入端子连接到一个第二入口电压。a comparator having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal of the comparator is connected to the reference resistor and the positive input terminal of the comparator is connected to to the output terminal of the first switch and the second switch, the output terminal of the comparator is connected to the input terminal of the NOT gate and the control terminal of the second switch, And the output terminal is used to enable and disable the oscillation of the oscillator, the input terminal of the first switch is connected to a first input voltage, the input terminal of the second switch is connected to a first Two input voltages.
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