CN1938914A - A laser driver circuit for reducing electromagnetic interference - Google Patents

Abstract

A laser driver circuit for reducing electromagnetic interference is disclosed. The laser driver circuit includes a first differential amplifier circuit, a second differential amplifier circuit and a glitch smoothing circuit. The first differential amplifier circuit is coupled to a pair of differential input signals, and is configured to generate a first amplified signal. The second differential amplifier circuit is coupled to the pair of differential input signals, and is configured to generate a second amplified signal. The first and second amplified signals together form a differential pair of output signals. The glitch smoothing circuit has a first output terminal coupled to the first differential amplifier circuit and a second output terminal coupled to the second differential amplifier circuit. The glitch smoothing circuit is configured to reduce glitches on the differential pair of output signals when the pair of differential input signals switch states.

Description

Laser Driver Circuit for EMI Reduction

technical field

The invention relates to the field of high-speed data communication, in particular to a circuit and method for reducing electromagnetic interference in a data communication system.

Background technique

In high-speed optical communication systems, laser signals are used to transmit information. For example, a laser driver circuit may be used to drive and modulate the amount of current received by a laser diode. The laser diode emits a laser signal in response to the magnitude of the received current.

Conventional laser driver circuits are implemented with multiple differential amplifiers consisting of transistor pairs that drive a pair of differential current output signals. One problem with conventional laser driver circuits is that when the transistors of the differential amplifier switch from on to off or vice versa, they generate unwanted common-mode glitches. Common-mode glitches can reverberate within the laser driver circuit, causing the circuit to radiate electromagnetic noise. These common-mode glitches are difficult to terminate within the integrated circuit. One possible solution is to use an inductor external to the laser driver IC to terminate the above output signal. However, an external inductor will add to system cost and take up valuable board space. Therefore, there is a need for a laser driver circuit that minimizes common mode glitches when the differential amplifier of the laser driver circuit transitions between states.

Conventional laser driver circuits are slow in discharging charge accumulated in the differential amplifier circuit, thus resulting in slow laser turn-off performance. One design goal of the laser driver circuit is to ensure fast signal transitions of the pair of differential current output signals, especially for the high-to-low transitions used to turn off the laser diode. This design goal can be achieved using a difference amplifier with high amplification gain, ensuring fast signal transitions. However, having a high amplification gain will produce signal overshoot when the output signal transitions from low to high, and the overshoot will cause unwanted electromagnetic noise.

Another design goal of the amplifier circuit is to minimize the electromagnetic interference generated by the laser driver circuit. This design goal is achieved by using a difference amplifier with low amplification gain to drive the output laser signal. Therefore, a design trade-off must be made to choose between the difference amplifier having high or low amplification gain, and the design is a trade-off because a trade-off must be made between the adverse effects of electromagnetic interference or slower signal transitions choose. The adverse effects of electromagnetic interference may result in additional system costs for reducing interference problems. The adverse effect of slower signal transitions may result in lower system performance. Therefore, there is a need for a laser driver circuit with high amplification gain for improved signal conversion performance while reducing the adverse side effects of electromagnetic interference.

Contents of the invention

One embodiment of the invention includes a method of smoothing glitches caused by switching of differential signal pairs. The method includes receiving a pair of differential signals including a first signal and a second signal. The first and second signals are of opposite polarity. The method also includes delaying the transition of the first signal by an amount of time relative to the second signal. Then, the delayed first signal and the second signal are output together as a differential signal pair with reduced glitches.

Another embodiment includes a laser driver circuit for reducing electromagnetic interference. The laser driver circuit includes a first differential amplifier circuit, a second differential amplifier circuit, and a glitch smoothing circuit. A first differential amplifier circuit is coupled to a pair of differential input signals and is configured to generate a first amplified signal. A second differential amplifier circuit is coupled to the pair of differential input signals and is configured to generate a second amplified signal. The first and second amplified signals together form a pair of differential output signals. A first output terminal of the glitch smoothing circuit is coupled to a first differential amplifier circuit, and a second output terminal is coupled to a second differential amplifier circuit, and the glitch smoothing circuit is configured to operate between the pair of differential inputs Reduces glitches on the pair of differential output signals when the signals switch states.

The above description is only an overview of the technical solutions of the present invention. In order to better understand the technical means of the present invention and implement them according to the contents of the description, the preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

Description of drawings

In order to achieve the above and other advantages and features of the invention, a more particular description of the invention will be provided by reference to specific embodiments of the invention which are illustrated in the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are not to be considered as limiting its scope thereby, the invention will be described and explained with additional features and details by using the accompanying drawings, in which middle:

Figure 1 illustrates the subsystem used to drive an electrical signal to a laser diode.

FIG. 2 illustrates the laser driver circuit of FIG. 1 according to one embodiment of the invention.

3A illustrates an implementation of the glitch smoothing circuit and asymmetric biasing circuit of FIG. 2 .

FIG. 3B is a diagram of the output signal of the differential amplifier without the glitch smoothing circuit.

FIG. 3C is a diagram of an output signal of a differential amplifier with a glitch smoothing circuit.

FIG. 4A illustrates an implementation of the current modulator circuit of FIG. 2 .

FIG. 4B illustrates output waveforms of the first and second differential amplifiers of FIG. 4A.

FIG. 4C compares the combined output waveforms of the first and second differential amplifiers of FIG. 4A with and without resistor networks R2 and R3.

FIG. 5A illustrates an implementation of the pulse shaping circuit of FIG. 2 .

FIG. 5B illustrates output waveforms of the pulse shaping circuit of FIG. 2 .

FIG. 6A illustrates an implementation of the transition compensation circuit of FIG. 2 .

FIG. 6B is a conversion compensation output signal of the conversion compensation circuit in FIG. 6A .

FIG. 6C is an output waveform of the conversion and boosting circuit in FIG. 2 .

FIG. 7A illustrates the nonlinear integrator circuit of FIG. 2 .

FIG. 7B is a diagram of the output signal of the laser driver circuit without the conversion and boosting circuit technology.

FIG. 7C is the output signal of the improved laser driver circuit using the conversion and boosting circuit.

Detailed ways

Figure 1 illustrates the subsystem used to drive an electrical signal to a laser diode. The digital signal 102 is first converted to an analog signal by a digital interface circuit 104 and then transmitted to a laser driver circuit 106 . Laser driver circuit 106 drives and modulates current to laser diode 108 . Laser diode 108 emits light of varying intensities in response to current received from laser driver circuit 106 .

FIG. 2 illustrates the laser driver circuit 106 of FIG. 1 . The laser driver circuit includes a pair of laser driver input terminals 202, 203, a glitch smoothing circuit 206, an asymmetric bias circuit 208, a switching compensation circuit 210, a pulse shaping circuit 212, a current modulator circuit 214, a nonlinear integrator circuit 216 and a pair of laser driver output terminals 218,219. The pair of laser driver input terminals 202 , 203 receive a pair of laser driver input signals (Ip, In) from the digital interface circuit 104 . Glitch smoothing circuit 206 detects and smooths common-mode glitches generated by the simultaneous switching states of the differential amplifiers of laser driver circuit 106 . The current modulator circuit 214 generates a pair of current modulator output signals (Op, On) according to the received pair of differential bias signals (Bp, Bn). In some embodiments, two current modulator circuits 214 are provided, both copies of which are connected to receive the same bias signal Bp, Bn and contribute to the output signals LOp, LOn output at the laser driver output terminals 218, 219. contribute. In these embodiments, one copy of the current modulator circuit 214 typically has a larger output bias 214 signal Bp, Bn than the other copy (eg, twice the output drive). Furthermore, the current modulator circuit generates differently delayed input signals DLY1p, DLY1n or DLY2p, DLY2n. These delayed input signals are used as input to the conversion compensation circuit 210, as shown in FIG. 6A.

The asymmetric bias circuit 208 , the transition compensation circuit 210 and the pulse shaping circuit 212 together form the transition boost circuit 204 . The conversion boost circuit 204 generates a pair of conversion boost signals Cp, Cn to enhance the signal conversion of the pair of current modulator output signals Op, On. The pair of switched boost signals Cp, Cn is generated based on the pair of differential laser driver input signals In, Ip and based on the current modulator circuit 214 . During each signal transition of the current modulator circuit 214, the asymmetric bias circuit 208 generates an asymmetric pulse signal (Pulse) and an asymmetric reference pulse signal (Plsref) according to the pair of differential input signals Ip, In. The asymmetrical pulse signal is biased to control the pulse shaping circuit in order to boost the current modulator output signal Op, On by switching the boost signal Cp, Cn so that the negative signal transition of the current modulator output signal Op, On is provided with a higher than its positive signal transition. Signal conditioning for signal conversion. The pulse shaping circuit 212 adjusts the amplitude and bandwidth of the asymmetric pulse signal to generate a pair of pulse shaped output signals. Pulse shaping circuit 212 includes one or more pulse stretching circuits, typically connected in series. The conversion compensation circuit 210 generates and boosts the portion of the conversion boost signal Cp, Cn comprising a pair of conversion compensation signals according to the pair of differential laser driver input signals Ip, In. The pair of transition compensation signals includes a positive compensation pulse for each positive transition of the current modulator output signal and a negative compensation pulse for each negative transition thereof. Positive and negative compensation pulses boost the pair of current modulator output signals Op, On.

A nonlinear integrator circuit 216 is coupled to the output terminal of the current modulator circuit 214 and to the conversion boost circuit 204 . It is configured to receive the pair of current modulator output signals Op, On and the pair of conversion boost signals Cp, Cn. It converts the received voltage signal to produce a pair of differential current output signals which are summed with the output signals Op, On of the current modulator circuit 214 to produce the laser driver at the output terminals 218, 219. Output signals LOp and LOn. The pair of laser driver output terminals 218 , 219 is configured to deliver the pair of differential current laser driver output signals LOp, LOn to the laser diode 108 .

FIG. 3A illustrates an implementation of the glitch smoothing circuit 206 and asymmetric biasing circuit 208 of FIG. 2 . The glitch smoothing circuit comprises a pair of input buffer circuits 301 and 302 whose pair of input ports 202, 203 are respectively coupled to the pair of differential laser driver input signals Ip, In. The pair of input buffer circuits 301 and 302 isolates the glitch smoothing circuit 206 from the digital interface circuit 104 ( FIG. 1 ) and sets the operating voltage range of the glitch smoothing circuit 206 .

The pair of input buffer circuits 301, 302 includes transistors Q34 and Q36. Transistor Q34 has a collector terminal coupled to a supply voltage source (Vdd), a base terminal coupled to a first input signal (In) of the pair of differential laser driver input signals Ip, In, and an emitter terminal coupled to a first bias Current source (I _bias31 ). Transistor Q36 has a collector terminal coupled to a power supply (Vdd), a base terminal coupled to the pair of differential laser driver input signals Ip, In a second input (Ip), and an emitter terminal coupled to a second bias current source (Ip). _bias32 ). Transistors Q34 and Q36 are used as level shifters. In the embodiment shown in Figure 3A, these transistors also perform a signal delay function due to the RC combination of the transistor output capacitance in series with the resistors (R36, R37).

Glitch smoothing circuit 206 also includes a pair of resistor networks R36 and R37, transistors Q35 and Q37, and a third bias current source (I _bias33 ). The collector terminal of transistor Q35 is coupled to the first output terminal 303 of glitch smoothing circuit 206 through resistor R311, the base terminal is coupled to the emitter terminal of transistor Q34 through resistor network R36, and the emitter terminal is coupled to the third bias Current source (I _bias33 ). The collector terminal of transistor Q37 is coupled to the second output terminal 304 of glitch smoothing circuit 206 through resistor R313, the base terminal is coupled to the emitter terminal of transistor Q35 through resistor network R37, and the emitter terminal is coupled to the emitter terminal of transistor Q35. terminal and coupled to a third bias current source (I _bias33 ). In some embodiments, resistors R311 and R313 are replaced by direct connections between the collector terminals of transistors Q35 and Q37, respectively, and differential amplifier circuits 306, 308.

The asymmetric bias circuit 208 includes a pair of input terminals 202 and 203, a first differential amplifier circuit 306 formed by transistors Q30 and Q31, a second differential amplifier circuit 308 formed by transistors Q32 and Q33, and a pair of output terminals 314(Bp) and 315(Bn). The glitch smoothing circuit 206 is coupled to first and second differential amplifiers 306 , 308 . The glitch smoothing circuit 208 reduces common mode glitches caused by switching states of the first and second differential amplifier circuits 306 , 308 at output terminals 303 and 304 of the glitch smoothing circuit.

The base terminal of transistor Q30 is coupled to the first laser driver input terminal 202, the collector terminal is coupled to a reference voltage source (Vref) through a resistor network R31 and to a first asymmetric bias output terminal 312 (Pulse), and emits The extreme terminal is coupled to the first output terminal 303 of the glitch smoothing circuit 206 . The base terminal of transistor Q31 is coupled to the second laser driver input terminal 203, the collector terminal is coupled to a reference voltage source (Vref) through a resistor network R32 and to the second asymmetric bias output terminal through a third resistor network R33 313 (Plsref), while the emitter terminal is coupled to the emitter terminal of transistor Q30 and to the first output terminal 303 of the glitch smoothing circuit 206 . The base terminal of transistor Q32 is coupled to the second input terminal 203, the collector terminal is coupled to a reference voltage source (Vref) through a resistor network R31 and to a first asymmetric bias output terminal 312 (pulse), and the emitter terminal Coupled to the second output terminal 304 of the glitch smoothing circuit 206 . The base terminal of transistor Q33 is coupled to the first input terminal 202, the collector terminal is coupled to a reference voltage source (Vref) through a fourth resistor network R34 and to a second asymmetrically biased output terminal 313 through a resistor network R35 ( Plsref), while the emitter terminal is coupled to the emitter terminal of transistor Q32 and to the second output terminal 304 of glitch smoothing circuit 206 .

FIG. 3B is a diagram of the output signals of differential amplifiers 306 and 308 without the glitch smoothing circuit 206 of the present invention. Specifically, curve 320 and curve 322 represent positive bias signal Bp transition and negative bias signal Bn transition of differential amplifiers 306 and 308, respectively. When operating without the glitch smoothing circuit 206, the differential amplifiers 306, 308 are each connected to circuit ground (Vss) (not shown) through a pair of bias current sources. For example, when both the positive bias signal Bp and the negative bias signal Bn switch states, the first output terminal 303 experiences both the voltage change of the Bp signal from high to low and the voltage change of the Bn signal from low to high. Variety. The voltage at the first output terminal 303 follows the higher voltage signal level of the Bp signal or the Bn signal. In other words, when the Bp signal transitions from high to low, during the first half of the signal transition, the voltage at the first output terminal 303 follows the Bp signal; when the Bn signal transitions from low to high, during the second half of the signal transition During this period, the voltage at the first output terminal 303 follows the Bn signal. This transition of the voltage signal level at the first output voltage terminal 303 is represented by the dashed curve 324 . Every time the first and second differential amplifiers 306 and 308 switch states, the sudden drop in the voltage signal level at the first output voltage terminal 303 produces a common mode glitch. And, this common mode glitch propagates together with the bias signals Bp and Bn.

FIG. 3C is a graph of the output signals of the differential amplifiers 306 and 308 with the glitch smoothing circuit 206 . Similar to FIG. 3B , curve 330 and curve 332 represent positive bias signal Bp transition at terminal 314 and negative bias signal (Bn) transition at terminal 315 of first and second differential amplifier circuits 306 and 308 , respectively. First and second differential amplifier circuits 306, 308 are attached to glitch smoothing circuit 206 at first and second output terminals 303 and 304, respectively, as shown in FIG. 3A.

In one embodiment, glitch smoothing circuit 206 operates as follows to reduce common-mode glitches due to state transitions of differential amplifier circuits 306 and 308 . When the laser driver input signal In switches from low to high and Ip switches from high to low, the In signal causes transistors Q31 and Q32 to turn on and the Ip signal causes transistors Q30 and Q33 to turn off. If the emitter terminals of Q30 and Q31 are connected to circuit ground through a bias current source, the first output terminal 314 will follow transistor Q31 and be pulled low due to transistor Q31 being turned on. However, with the glitch smoothing circuit 206, even if the transistor Q31 is turned on, the bias signal Bp at the output terminal 314 does not drop until the transistor Q35 is turned on. The laser driver input signal In to transistor Q35 is delayed by resistor network R36, causing transistor Q35 to be turned on after a delay T, so bias signal Bp begins its transition after a delay T334. It should be noted that the amount of delay in the glitch smoothing circuit controls the amount of glitch reduction on the output signals of the differential amplifier circuits 306 and 308 . At the same time, the signal Ip transitions from high to low, causing the transistor Q33 to be turned off, and the second output terminal 315 is pulled high to the reference voltage source (Vref) without delay. Therefore, when the Bp signal transitions from high to low, the voltage at the first output terminal 303 follows the Bp signal during the first half of the signal transition, and when the Bn signal transitions from low to high, during the second half of the signal transition , the voltage at the first output terminal 303 follows the Bn signal. Consequently, reduced common-mode glitches are observed at the first output terminal 303 , as represented by the dashed curve 336 . It should be noted that the glitch smoothing circuit acts in a similar manner to reduce common mode glitches when the laser driver input signal (Ip) transitions from low to high and when the laser driver input signal (In) transitions from high to low.

FIG. 4A illustrates an implementation of the current modulator circuit 214 of FIG. 2 . The current modulator circuit includes a negative receiver signal path and a positive receiver signal path. One function of the positive and negative receiver signal paths is to isolate the current modulator circuitry from the glitch smoothing circuitry and other preceding laser driver circuitry. Another function of the positive and negative receiver paths is to set the operating range for modulating the bias signals Bp and Bn on the input nodes 314 and 315 . The negative receiver signal path includes transistor Q42, a first bias current source formed by transistor Q45 and resistor R410. Transistor Q42 has its base terminal coupled to node 315 to receive the Bn signal from the asymmetric bias circuit (FIG. 2), its collector terminal coupled to a power supply (Vdd), and its emitter terminal coupled to a first bias current source ( Q45, R410). Similarly, the positive receiver signal path includes transistor Q412, a second bias current source formed by transistor Q415 and resistor R416. The base terminal of transistor Q412 is coupled to node 314 to receive the Bp signal from the asymmetric bias circuit (FIG. 2), its collector terminal is coupled to the power supply Vdd, and its emitter terminal is coupled to a second bias current source (Q415 , R416).

The first differential amplifier 406 of FIG. 4A includes transistors Q40 and Q41, a resistor network R40, a bias current source formed by a transistor Q47 and a resistor R412. The bias current through transistor Q47 is determined by the bias voltage vbn on the base of transistor Q47 and the resistance of resistor R412. The base terminal of transistor Q40 is coupled to the first output port (b1) of the receiver circuit, its collector terminal is coupled to the power supply Vdd through resistor network R40 and to the first output port 218 of the current modulator circuit, and its emitter terminal coupled to a first bias current source (Q47, R412). The base terminal of transistor Q41 is coupled to the second output port (b2) of the receiver circuit, its collector terminal is coupled to the power supply Vdd through resistor network R41 and to the second output port 219 of the current modulator circuit 214, and its The emitter terminal is coupled to the emitter terminal of transistor Q40 and to a bias current source (Q47, R412). Resistor networks R40, R41 each include one or more resistors connected in series or in parallel.

The current modulator circuit 214 also includes a resistor network R42 and a resistor network R43. Resistor networks R42 and R43 each include one or more resistors connected in series or parallel. The resistor network R42 is coupled between the first output port ( b1 ) of the receiver circuit 404 and the first input port of the second differential amplifier circuit 408 . The resistor network R42 produces a first predetermined time shift at the first input port of the second differential amplifier circuit 408 . Similarly, a resistor network R43 is coupled between the second output port ( b2 ) of the receiver circuit and the second input port of the second differential amplifier circuit 408 . The resistor network R43 produces a second predetermined time shift at the second input port of the second differential amplifier circuit 408 . In some embodiments, the first and second predetermined time shifts are approximately the same.

The second differential amplifier 408 of FIG. 4A includes transistors Q410 and Q411, a resistor network R41, a second bias current source formed by a transistor Q417 and a resistor R414. The base terminal of transistor Q410 is coupled to receiver output port b1 through resistor network R42, the collector terminal is coupled to power supply Vdd through resistor network R40 and to the first output port 218 of the current modulator circuit, and the emitter terminal is coupled to to the second bias current source (Q417, R414). The base terminal of transistor Q411 is coupled to the receiver output port b2 through resistor network R43, the collector terminal is coupled to the power supply through resistor network R1 and to the second output port 219 of the second differential amplifier 408, and the emitter terminal is coupled to the emitter terminal of transistor Q410 and to a second bias current source (Q17, R14).

As previously mentioned, in some embodiments, there are two copies of circuit 214 shown in FIG. 4A , one of which is tailored to drive a larger current through output nodes 218 , 219 than the other. Also, one copy of circuit 214 generates delayed signals DLY1p and DLY1n, while the other copy generates delayed signals DLY2p and DLY2n. These delayed input signals are used as input to the conversion compensation circuit 210, as shown in FIG. 6A.

FIG. 4B illustrates output waveforms of the first and second differential amplifiers of FIG. 4A. Curve 422 represents the output of the first differential amplifier circuit 406 . Curve 424 is a dashed line and represents the corresponding output of second differential amplifier circuit 408 if current modulator circuit 214 did not include resistor network R42 and R43 (ie, replace R42 and R43 with a zero impedance closed circuit). Curve 426 represents the corresponding output of second differential amplifier circuit 408 when current modulator circuit 214 includes resistor network R42 and R43 . It should be noted that the output signal represented by curve 426 is delayed by a predetermined amount of time relative to the signal represented by curve 424 . The time difference between curves 424 and 426 is represented by AT 428 due to the delay to the input signal to second differential amplifier circuit 408 created by resistor network R42 and R43.

FIG. 4C compares the combined output waveforms of the first and second differential amplifiers 406 and 408 of FIG. 4A with and without resistor networks R42 and R43. Curve 430 is a dashed line and represents one of the output signals of current modulator circuit 214 when operating without resistor network R42 and R43. Curve 430 represents the sum of output signals 422 and 424 produced by first and second differential amplifier circuits 406 and 408, respectively. Although the combined output signal represented by the curve 430 is produced by a high amplification gain, this combined signal includes an undesired comparison at the beginning and end of the signal conversion due to the simultaneous switching of both the first and second differential amplifiers. higher order harmonics.

Curve 432 represents one of the output signals of the current modulator circuit when operated with resistor network R42 and R43. In one embodiment, at the beginning of signal conversion, when the first differential amplifier circuit 406 is switched on and the second differential amplifier circuit 408 is not yet switched on due to the delay of the resistor network R42 and R43, the output signal is alone in the first The slew rate of the output signal of a differential amplifier circuit 410 is switched. Similarly, at the end of the signal transition, when the first differential amplifier circuit 406 is off and the second differential amplifier circuit 408 is still on due to the delay of the resistor network R42 and R43, the output signals Op, On are independently The switching takes place at the slew rate of the output signal of the second differential amplifier circuit 408 . During periods when both the first and second differential amplifier circuits 406 , 408 are on, the output signals On, Op switch at the combined rate of the outputs of the first and second differential amplifier circuits 406 and 408 . Thus, the combined output signal (represented by curve 432) has fewer undesired higher order harmonics at the beginning and end of signal transitions, thus reducing simultaneous switching by the first and second differential amplifiers. generated electromagnetic interference.

FIG. 5A illustrates an implementation of the pulse shaping circuit 212 of FIG. 2 . Pulse shaping circuit 212 may include one or more pulse stretching circuits. In one embodiment, pulse shaping circuit 212 is coupled to node 312 (Pulse) and node 313 (Plsref). The pulse shaping circuit includes a first pulse stretching circuit 504 , a second pulse stretching circuit 506 , a first output terminal 508 and a second output terminal 510 . The first pulse stretching circuit 504 is connected in series with the second pulse stretching circuit 506 . The first and second input nodes 312, 313 are configured to receive the asymmetric pulse and asymmetric reference pulse signals generated by the asymmetric bias circuit 208 (see nodes 312, 313 in FIG. 3A). The first pulse stretching circuit 504 increases the amplitude of the asymmetric pulse signal and expands the bandwidth of the asymmetric pulse signal. The second pulse stretching circuit 506 further increases the amplitude of the asymmetric pulse signal and extends the bandwidth of the asymmetric pulse signal. The first and second output terminals 508, 510 are configured to drive a pair of pulse shaped output signals.

The first pulse stretching circuit 504 includes a buffer circuit formed by transistors Q50 and Q51 and their corresponding bias current sources _Ibias51 and _Ibias52 , and a differential amplifier formed by transistors Q52 and Q53 , as shown in Figure 5A. The base terminal of transistor Q50 is coupled to the second output terminal (313 of FIG. 3A ) of the asymmetric bias circuit, the collector terminal is coupled to a reference voltage source (Vref), and the emitter terminal is coupled to Vref through a bias current source _Ibias51 . Circuit Ground (Vss). The base terminal of transistor Q51 is coupled to the first output node (312 of FIG. 3A ) of the asymmetric bias circuit, the collector terminal is coupled to the base terminal of transistor Q51 and to the emitter terminal of transistor Q50 through a capacitor network C51, Whereas the emitter terminal is coupled to circuit ground through a bias current source _Ibias52 . The base terminal of transistor Q52 is coupled to the emitter terminal of transistor Q50, the collector terminal is coupled to a reference voltage source Vdd through a resistor and capacitor network RC51 and to the first output terminal of first pulse stretching circuit 504, and the emitter is coupled through A bias current source I _{bias 53} is coupled to circuit ground. The base terminal of transistor Q53 is coupled to the emitter terminal of transistor Q51, the collector terminal is coupled to a reference voltage source Vdd through a resistor and capacitor network RC52 and to the second output terminal of the first pulse stretching circuit 504, and the emitter terminal is coupled to the emitter terminal of transistor Q52 and to circuit ground through a bias current source _Ibias53 . The first pulse stretching circuit 504 shapes the input pulse signals Pulse and Plsref as follows. First, it delays the switching of the input signals Pulse and Plsref using the capacitor network C51. Subsequently, the input signals Pulse and Plsref are amplified to predetermined signal levels by differential amplifier circuits (Q52, Q53). Finally, the output signal at the output terminal of the first pulse stretching circuit is delayed by a resistor-capacitor network RC51 and RC52.

The second pulse stretching circuit 506 includes a second buffer circuit formed by transistors Q55 and Q56 and their corresponding bias current sources _Ibias55 and _Ibias56 . The second pulse stretching circuit also includes a differential amplifier circuit formed by transistors Q57 and Q58. The base terminal of transistor Q55 is coupled to the second output terminal of the first pulse stretching circuit, the collector terminal is coupled to the power supply Vdd, and the emitter terminal is coupled to circuit ground Vss through a bias current source I _bias55 . Transistor Q56 has a base terminal coupled to the first output terminal of the first pulse stretching circuit, a collector terminal coupled to the power supply Vdd, and an emitter terminal coupled to circuit ground through a bias current source I _bias56 . The base terminal of transistor Q57 is coupled to the emitter terminal of transistor Q55 through resistor network R51, the collector terminal is coupled to the first output terminal 508 of the second pulse stretching circuit, and the emitter terminal is passed through a bias current source _Ibias57 and via Capacitor network C52 is coupled to circuit ground. The base terminal of transistor Q58 is coupled to the emitter terminal of transistor Q56 through resistor network R52, the collector terminal is coupled to the second output terminal 510 of the second pulse stretching circuit, and the emitter terminal is coupled to the emitter terminal of transistor Q57 and Coupled to capacitor network C52. The second pulse stretching circuit 506 also shapes the output signal from the first pulse stretching circuit 504 as follows. First, the input signal from the first pulse stretching circuit 504 is delayed by resistor network R51 and R52. Next, the second pulse stretching circuit 506 amplifies the input signal to a predetermined signal level through the differential amplifier circuit (Q57, Q58). Finally, switching of the output signal is delayed by a capacitor network C52 attached between the differential amplifier circuit (Q7, Q5) and circuit ground Vss.

Typically, the supply voltage Vdd used by the second pulse stretching circuit 506 is greater than the reference voltage Vref used by the first pulse stretching circuit 504 , thus enabling the second pulse stretching circuit 506 to perform greater amplification than the first pulse stretching circuit 504 . In addition, the reference voltage Vref is the same in various circuits shown in the drawings. In some embodiments, Vdd is between about 2.9 and about 3.6 volts, and Vref is a regulated voltage of about 2.7 volts. The voltage of Vref is approximately constant for the entire range of Vdd voltages.

FIG. 5B illustrates the output waveform (Cn) of the pulse shaping circuit 212 of FIGS. 2 and 5A. More specifically, the output waveform Cn shown in FIG. 5B represents the current flowing from node 508 into the pulse shaping circuit of FIG. 5A. Waveform Cn includes pulses in a downward direction at each signal transition at the input terminals 202, 203 of the laser driver circuit 106, such as pulses 520 and 522 representing the pair of differential laser driver input signals Ip, In of the laser driver circuit 106. Such signal conversion. Each pulse 520, 522 is biased asymmetrically by the asymmetric biasing circuit 208 so that a high-to-low signal transition of the laser driver output signal can be compared to a low-to-high signal transition of the laser driver output signal Provide a wider range of signal modulation. Furthermore, the magnitude of each pulse 520, 522 has been amplified and the bandwidth of each pulse extended by the pulse shaping circuit 206. The output waveform of the pulse shaping circuit 212 and the output waveform of the switching compensation circuit 210 form the output waveform of the switching boost circuit 204Cp, Cn. The output waveform of the Cn, Cp conversion boost circuit 204 is used to enhance the output waveform of the Op, On current modulator circuit 214 . The resulting enhanced waveform is processed by nonlinear integrator circuit 216, which is described below with respect to Figures 7A, 7B and 7c.

FIG. 6A illustrates an implementation of the translation compensation circuit 210 of FIG. 2 . Conversion compensation circuit 210 is coupled to laser driver input terminals 202 and 203 and further includes a second pair of input terminals 604 and 605, an optional pair of input terminals 606 and 607, a first amplification circuit 612, a second amplification circuit 614, a second pair of Three amplifying circuits 616 and an optional fourth amplifying circuit 618 . The first amplification circuit 612 is configured to receive the pair of differential laser driver input signals (Ip, In) and generate a pair of switching compensation signals in response to the input signals Ip, In. The second amplifying circuit 614 is configured to receive a first delayed version of the pair of differential laser driver input signals (DLY1p, DLY1n) at input terminals 604 and 605, respectively, and the third amplifying circuit 616 is configured to receive the second amplifying circuit 614 output signal. The second and third amplifying circuits 614, 616 generate a pair of delayed and inverted transition compensation signals for canceling the pair of transition compensation signals of the first amplification circuit.

An optional fourth amplification circuit 618 is configured to receive a second delayed version of the pair of differential laser driver input signals ( DLY2p , DLY2n ) at input terminals 606 and 607 . The fourth amplifying circuit 618 is included only in embodiments where two current modulator circuits 214 are provided. Furthermore, in some embodiments, only one of circuits 614 or 618 is enabled, eg, by enabling only one of bias currents I _bias64 and I _bias66 . Thus, only one of circuits 614 or 618 is used to trigger third amplifying circuit 616 even though the output terminal of optional fourth amplifying circuit 618 is coupled in parallel to the output terminal of second amplifying circuit 614 . Since circuits 614 and 618 are driven by delayed input signals (DLY1p, DLY1n) and (DLY2p, DLY2n), the third amplifying circuit 616 triggers to correspond to the delay in those delayed input signals plus AND circuit 614 or 618 by the amount of delay (relative to the laser driver input signal Ip, In).

The conversion compensation circuit 210 also includes a first output terminal 508 and a second output terminal 510 . The first output terminal is configured to combine the first conversion-compensated output signal of the first amplification circuit 612 with corresponding first delayed and inverted conversion-compensated output signals of the second and third amplification circuits 614, 616 such that A first conversion compensation pulse signal is formed. The second output terminal is configured to combine the second conversion-compensated output signal of the first amplification circuit 612 with corresponding second delayed and inverted conversion-compensated output signals of the second and third amplification circuits 614, 616 such that A second switching compensation pulse signal is formed. The combined waveforms of the first amplifying circuit 612 and the third amplifying circuit 616 are shown and described with reference to FIG. 6B below.

The first amplification circuit 612 includes a first buffer circuit formed with transistors Q60 and Q61. Transistor Q60 has a base terminal coupled to input terminal 202, a collector terminal coupled to supply voltage source Vdd, and an emitter terminal coupled to circuit ground Vss through a bias current source I _bias61 . Transistor Q61 has a base terminal coupled to input terminal 203In, a collector terminal coupled to a supply voltage source, and an emitter terminal coupled to circuit ground through a bias current source _Ibias61 . The first amplifying circuit 612 also includes a differential amplifier circuit formed with transistors Q62 and Q63. The base terminal of transistor Q2 is coupled to the emitter terminal of transistor Q60 , the collector terminal is coupled to the first output terminal 508 of the first amplifier circuit, and the emitter terminal is coupled to circuit ground through a bias current source I _bias66 . The base terminal of transistor Q63 is coupled to the emitter terminal of transistor Q61, the collector terminal is coupled to the second output terminal 510 of the first amplifier circuit, and the emitter terminal is coupled to the emitter terminal of transistor Q62 and to a bias current source I _bias62 .

The second amplification circuit 614 includes a pair of resistor networks R61p and R61n coupled to input terminals 604 and 605, respectively. The second amplifying circuit 614 also includes a differential amplifier circuit formed with transistors Q64 and Q65. The base terminal of transistor Q64 is coupled to input terminal 604 through resistor network R61p, the collector terminal is coupled to reference voltage source Vref through resistor network R63 and to the first output terminal 621 of the second amplifying circuit, and the emitter terminal is coupled through A bias current source I _{bias 64} is coupled to circuit ground (Vss). The base terminal of transistor Q65 is coupled to input terminal 605 through resistor network R61n, the collector terminal is coupled to reference voltage source Vref through resistor network R64 and to the second output terminal 622 of the second amplifier circuit, and the emitter terminal is coupled to to the emitter terminal of transistor Q64 and is coupled to a bias current source I _bias64 . The resistor network R61p, R61n, R63 and R64 includes one or more resistors connected in series or in parallel.

Optional amplification circuit 618 is similar to second amplification circuit 614 . Optional amplification circuit 618 includes a pair of resistor networks R62p and R62n coupled to input terminals 606 and 607, respectively. Optional amplifier circuit 618 also includes a differential amplifier circuit formed with transistors Q66 and Q67. The base terminal of transistor Q66 is coupled to the input terminal 606 through a resistor network R62p, the collector terminal is coupled to a reference voltage source through a resistor network R63 and to the first output terminal 621 of the second amplifying circuit 614, and the emitter terminal is coupled through A bias current source I _{bias 66} is coupled to circuit ground Vss. The base terminal of transistor Q67 is coupled to input terminal 607 through resistor network R62n, the collector terminal is coupled to reference voltage source Vref through resistor network R64 and to the second output terminal 622 of second amplifier circuit 614, and the emitter terminal is coupled to the emitter terminal of transistor Q66 and to a bias current source I _bias66 . Resistor network R62p and R62n includes one or more resistors connected in series or parallel.

The third amplifying circuit 616 includes a buffer circuit formed with transistors Q68 and Q69. Transistor Q68 has a base terminal coupled to first output terminal 621 of second amplifying circuit 614, a collector terminal coupled to supply voltage source Vdd, and an emitter terminal coupled to circuit ground Vss via bias current source I _bias68 . Transistor Q69 has a base terminal coupled to second output terminal 622 of second amplifier circuit 614 , a collector terminal coupled to supply voltage source Vcc, and an emitter terminal coupled to circuit ground Vss via bias current source I _bias69 . The third amplifying circuit 616 also includes a differential amplifier circuit formed with transistors Q610 and Q611. The base terminal of transistor Q610 is coupled to the emitter terminal of transistor Q68, the collector terminal is coupled to the first output terminal 508 of the third amplifying circuit 616 through a resistor network R65, the emitter terminal is coupled to the circuit through a bias current source _Ibias610 land. The base terminal of transistor Q611 is coupled to the emitter terminal of transistor Q69, the collector terminal is coupled to the second output terminal 510 of the third amplifying circuit 616 through a resistor network R66, and the emitter terminal is coupled to the emitter terminal of transistor Q610 and Coupled to bias current source I _bias610 . Resistor network R65 and R66 includes one or more resistors connected in series or parallel.

6B is a graph depicting the transition compensation output signal of the transition compensation circuit 210 of FIG. 6A. According to an embodiment of the present invention, the first amplifying circuit 612 operates as follows. When the laser driver input signal Ip at the laser driver input terminal 202 is switched from low to high and the laser driver input signal In at the laser driver input terminal 203 is switched from high to low, the transistor Q60 is turned on by the laser driver input signal Ip, and Transistor Q61 is turned off by the laser driver input signal In. Accordingly, the base terminal of transistor Q62 is pulled high, turning on transistor Q62; and the base terminal of transistor Q63 is pulled low by bias current source _Ibias62 . When transistor Q62 is turned on, the bias current pulls output terminal 508 low, causing the transition compensation signal at terminal 508 to transition from high to low. When transistor Q63 is turned off, output terminal 510 is pulled high (via diode 708 of nonlinear integrator circuit 216, FIG. 7A), causing the transition-compensation signal at terminal 510 to transition from low to high.

The second and third amplifying circuits 614, 616 operate as follows. When the laser driver input signal Ip transitions from low to high, the laser driver input signal In transitions from high to low. After a predetermined amount of delay, the input signals (DLY1p and DLY1n) at the input terminals 604 and 605 of the second amplifying circuit 614 operate as follows. The input signal (DLY1p) transitions from low to high, while the input signal (DLY1n) transitions from high to low. Signal (DLY1p) causes transistor Q64 to turn on and signal (DLY1n) causes transistor Q65 to turn off. Accordingly, the base terminal of transistor Q68 is pulled low by bias current source _Ibias64 , turning off transistor Q68; and the base terminal of transistor Q69 is pulled high, turning on transistor Q69. When transistor Q68 turns off, bias current source I _bias68 pulls down the base terminal of transistor Q610, causing transistor Q610 to turn off. On the other hand, when transistor Q69 is turned on, the base terminal of transistor Q611 is pulled high, causing transistor Q611 to turn on. Thus, when transistor Q610 is turned off, output terminal 508 is pulled high by diode 706 of nonlinear integrating circuit 216 (FIG. 7A), causing output terminal 508 to transition from low to high. When transistor Q611 is turned on, the output terminal 510 is pulled low, causing the output terminal 510 to transition from high to low.

At the output terminals 508 and 510, the output signals of the first amplification circuit 612 and the third amplification circuit 616 are combined together. Thus, when the laser driver input signal Ip transitions from low to high and the laser driver input signal In transitions from high to low, the first amplifying circuit 612 issues an output signal at the output terminal 510, enabling it to pass through the diode 708 (FIG. 7A) From low to high, and after a predetermined period of time, the third amplifying circuit 616 pulls the output signal at the output terminal 510 from high back to low, thereby generating a first pulse 620 in a positive direction as shown in FIG. 68 . On the other hand, when the laser driver input signal Ip transitions from low to high and the laser driver input signal In transitions from high to low, the first amplifying circuit 612 pulls the output signal at the output terminal 508 from high to low, and in a After a predetermined period of time, the third amplifying circuit 616 stops drawing current from the output terminal 508 to allow the output terminal 508 to transition back to a higher voltage, thereby generating a negative direction pulse (not shown) on the output terminal 508 . It should be noted that in the opposite direction, when the laser driver input signal Ip transitions from high to low and the laser driver input signal In transitions from low to high, a negative direction pulse is generated at the output terminal 510, as shown by the second pulse 622 in FIG. 6B and a positive direction pulse (not shown) is generated at the output terminal 508.

FIG. 6C is the output waveforms Cp and Cn of the conversion and boosting circuit 204 . The output waveforms combine the corresponding output signals of the switching compensation circuit 210 and the pulse shaping circuit 212 in FIGS. 6A and 5A , respectively. Specifically, the pulse signal 624 is a combination of the pulse signal 520 in FIG. 5B and the pulse signal 620 in FIG. 6B ; and the pulse signal 626 is a combination of the pulse signal 522 in FIG. 5B and the pulse signal 622 in FIG. 6B . It should be noted that the combined pulse signals 624 and 626 provide a greater modulation range of the laser driver output signal in the negative direction (for turning off the laser diode) than in the positive direction (for turning on the laser diode).

FIG. 7A illustrates an implementation of the nonlinear integrator circuit 216 of FIG. 2 . A nonlinear integrator circuit 216 is coupled to output terminals 508 and 510 and includes a first diode 706 , a second diode 708 , a differential amplifier circuit formed with transistors Q0 and Q1 , and a pair of output terminals 218 and 219 . At node 508, the first input terminal is configured to receive a corresponding first input signal from pulse shaping circuit 212 and transition compensation circuit 210 (FIG. 2A); while at node 510, the second input terminal is configured to receive A corresponding second input signal from the pulse shaping circuit and the transition compensation circuit.

The first and second diodes 706 and 708 act as nonlinear integrators that perform nonlinear modulation on the received input signal. A first diode 706 is coupled between a supply voltage source Vdd and node 508 . The first diode 706 is configured to integrate the input signal received from the pulse shaping circuit 212 and the corresponding output node 508 of the transition compensation circuit 210 . The second diode 708 is coupled between the supply voltage source Vdd and the second node 510 . Similarly, second diode 708 is configured to integrate the input signal received from node 510 of pulse shaping circuit 212 and transition compensation circuit 210 . The base terminal of transistor Q70 is coupled to the first input terminal 508, the collector terminal is coupled to the first laser driver output terminal 218 of the nonlinear integrator circuit 216, and the emitter terminal is coupled to circuit ground through a bias current source _Ibias71 ( Vss). The base terminal of transistor Q71 is coupled to second input terminal 510, the collector terminal is coupled to second laser driver output terminal 219 of nonlinear integrator circuit 216, and the emitter terminal is coupled to the emitter terminal of transistor Q70 and to bias Set the current source I _bias71 . The first and second laser driver output terminals 218 and 219 are capacitively coupled (also referred to as AC coupled) to the laser diode 108 through a pair of capacitors C71 and C72 and a pair of transmission lines. These laser driver output terminals 218 and 219 are also coupled to a current modulator circuit 214, which includes output pull-up resistor networks R70 and R71 (see FIG. 4A).

FIG. 7B is a diagram of the output signal of the laser driver circuit without applying the technology of the conversion and boosting circuit 204 . The dashed line represents an ideal square wave waveform 720 . Curve 722 is a solid line representing the output signal of a laser driver circuit without conversion boost circuit 204 . It should be noted that both positive and negative signal transitions deviate from the ideal square wave shape 720 , especially for high-to-low signal transitions. Inherent to conventional laser driver circuits is that it takes longer to discharge the current modulator circuit to turn off the output signal driving the laser diode than to turn on the same output signal.

FIG. 7C is a graph of the output signal of a modified laser driver circuit in which a conversion boost circuit is applied to the input of the nonlinear integrator circuit 216 . Similar to FIG. 7B , the dashed line represents an ideal square wave waveform 720 . Curve 724 , shown as a solid line, represents the output signal of the laser driver circuit with conversion boost circuit 204 . As shown in FIG. 7C, the low-to-high signal transition is enhanced to tend towards the ideal square wave shape 720, and the performance of the positive signal transition is improved. This improvement occurs due to the application of the asymmetrical transition adjustment pulse 624 of FIG. 6C to the positive transition of the output signal of the current modulator circuit 214 . Similarly, high-to-low signal transitions are enhanced to tend towards an ideal square wave shape 720, and the performance of negative signal transitions is also improved. This improvement occurs due to the application of the asymmetric transition adjustment pulse 626 of FIG. 6C to the negative transition of the output signal of the current modulator circuit 214 .

Those skilled in the relevant art will recognize that many possible modifications can be made to the operative embodiments while still employing the same basic mechanisms and methods of the present invention. For example, the amplification circuit may be implemented using different types of transistors, such as FET or MOS transistors. Thus, "base", "collector" and "emitter" as used above will correspond to "gate", "source" and "drain" in some other embodiments. The conversion boost circuit may be implemented using one or more amplification stages. The current modulator circuit can be implemented using one or more pairs of differential amplifiers to drive the pair of current output signals to the laser diode.

Embodiments may be described functionally with reference to various means for performing specified functions. For example, one embodiment includes an apparatus for smoothing glitches caused by switching of differential signal pairs. The apparatus includes means for receiving a pair of differential signals comprising a first signal and a second signal. The first and second signals are of opposite polarity. Structures corresponding to means for receiving a pair of differential signals may include various connectors or printed circuit board traces and/or input terminals, such as input terminals 202 and 203 shown in FIGS. 2 and 3A .

Embodiments may also include means for delaying the transition of the first signal by an amount of time relative to the second signal. Structure corresponding to means for delaying the transition of the first signal by an amount of time relative to the second signal may include, for example, resistor networks R56 and R57 and transistors Q55 and Q56.

Embodiments may further include means for outputting the delayed first signal and the second signal together as a glitch-reduced differential signal pair. The structure corresponding to the means for outputting the delayed first signal and the second signal together as a differential signal pair may include, for example, the output terminals 303 and 304 shown in FIG. 3A .

Embodiments may also include means for buffering the first signal and the second signal to isolate circuitry for performing receiving, delaying, and outputting activities from the digital interface circuitry. The structure corresponding to the buffer device may include, for example, buffer circuits 301 and 302 as shown in FIG. 3A . The buffer circuits 301 and 302 may also correspond to a structure serving as means for setting the operating voltage range of the circuit system.

One embodiment includes means for generating a converted boost signal to enhance a digitally modulated signal. The structure corresponding to the device may include, for example, the conversion and boosting circuit 204 shown in FIG. 2 . The means for generating a transition boost signal may include means for generating a transition compensation signal. The conversion compensation signal is configured to enhance conversion of the digitally modulated signal. The structure corresponding to the device for generating the conversion compensation signal may include, for example, the conversion compensation circuit 210 shown in FIG. 2 . The means for generating a transition boost signal may also include means for generating a pulse shaped output signal comprising pulses at transitions of the digitally modulated signal. The structure corresponding to the means for generating a pulse-shaped output signal may include, for example, the pulse-shaping circuit 212 shown in FIG. 2 . The means for generating a converted boosted signal may also include means for combining the converted compensation signal and the pulse shaped output signal to form a converted boosted signal. The structure corresponding to the means for combining the converted compensation signal and the pulse-shaped output signal may include, for example, various traces, connectors, and/or non-linear integrator circuit 216 shown in FIG. 2 .

Embodiments may include means for driving a laser diode with a differential signal pair with reduced glitches. The structure corresponding to the means for driving the laser diode with the differential signal pair may include elements such as the current modulator circuit 214 and/or the nonlinear integrator circuit 216 shown in FIG. 2 .

The description for explanation has been described above with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The foregoing embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and the various embodiments as are suited to the particular use contemplated. Various examples of modifications.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments should be considered in all respects as illustrative only and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be included in the scope of the claims.

Claims (21)

1. one kind smoothly by the method for the right glitch that switching produced of differential wave, and described method comprises:

It is right to receive a differential wave, and it comprises first signal and secondary signal, and wherein said first and second signals are reversed polarity;

To postpone the conversion of described first signal with respect to a time quantum of described secondary signal;

The differential wave that described delayed first signal and described secondary signal have been reduced as glitch is to output together.

2. method according to claim 1, it further comprises: cushion described first signal and described secondary signal will be used to carry out the Circuits System and the digital interface circuit isolation of reception, delay and output behavior.

3. method according to claim 1, it further comprises: set and to be used to carrying out receptions, to postpone and the operating voltage range of the Circuits System of the behavior of output.

4. method according to claim 1, it further comprises:

The generation conversion promotes signal, wherein produces conversion lifting signal and comprises:

Produce the conversion compensating signal, described conversion compensating signal is configured to strengthen the conversion of digital modulation signals;

Produce the shaping pulse output signal, the pulse when described shaping pulse output signal comprises the conversion that is in described digital modulation signals;

Make up described conversion compensating signal and described shaping pulse output signal and promote signal to form described conversion;

Generation promotes the output signal that signal is formed by described digital modulation signals and described conversion.

5. method according to claim 1, it further comprises: the time quantum by the control lag conversion is controlled the glitch reduction.

6. method according to claim 1, wherein said first signal are positive signal and described secondary signal is a negative signal.

7. method according to claim 1, wherein when described first signal by height during to low conversion, to postpone the conversion of described first signal with respect to a time quantum of described secondary signal.

8. method according to claim 1, it comprises that further the differential wave that has reduced with described glitch is to the driving laser diode.

9. laser driver circuit that is used to reduce electromagnetic interference, it comprises:

Be coupled to first differential amplifier circuit of pair of differential input signals, wherein said first differential amplifier circuit is configured to produce first amplifying signal;

Be coupled to this second differential amplifier circuit to differential input signal, wherein said second differential amplifier circuit is configured to produce second amplifying signal, and wherein said first and second amplifying signals form the pair of differential output signal together; And

The glitch smoothing circuit, its first lead-out terminal is coupled to described first differential amplifier circuit and second lead-out terminal is coupled to described second differential amplifier circuit, and wherein said glitch smoothing circuit is configured to reduce this to the glitch on the differential output signal at this during to differential input signal switching state.

10. laser driver circuit according to claim 9, wherein said glitch smoothing circuit be coupled into reception from digital interface circuit should be to differential input signal, and wherein said laser driver circuit is configured to the pair of differential current signal to laser diode is driven.

11. laser driver circuit according to claim 9, wherein said first differential amplifier circuit comprises:

The first transistor, its base terminal are coupled to this first input to differential input signal, and collector terminal is coupled to reference voltage source by first resistor network, and emitter terminal is coupled to first lead-out terminal of described glitch smoothing circuit; And

Transistor seconds, its base terminal is coupled to this second input to differential input signal, collector terminal is coupled to described reference voltage source by second resistor network, and emitter terminal is coupled to the emitter terminal of described the first transistor and be coupled to first lead-out terminal of described glitch smoothing circuit.

12. laser driver circuit according to claim 11, wherein said second differential amplifier circuit comprises:

The 3rd transistor, its base terminal are coupled to this first input to differential input signal, and collector terminal is coupled to described reference voltage source by the 3rd resistor network, and emitter terminal is coupled to second lead-out terminal of described glitch smoothing circuit; And

The 4th transistor, its base terminal is coupled to this second input to differential input signal, collector terminal is coupled to the collector terminal of described the first transistor, and emitter terminal is coupled to the described the 3rd transistorized emitter terminal and be coupled to second lead-out terminal of described glitch smoothing circuit.

13. laser driver circuit according to claim 9, wherein said glitch smoothing circuit comprises:

Be coupled to this pair of input terminals to differential input signal respectively, this comprises first input end and second input terminal to input terminal;

First delay element;

Second delay element;

The first transistor, its collector terminal is coupled to described first lead-out terminal by first resistor, and base terminal is coupled to described first input end by described first delay element, and emitter terminal is coupled to first bias current sources; And

Transistor seconds, its collector terminal is coupled to described second lead-out terminal by second resistor, and base terminal is coupled to described second input terminal by described second delay element, and emitter terminal is coupled to the emitter terminal of described the first transistor.

14. laser driver circuit according to claim 9, it further comprises:

A pair of input buffer circuit, its a pair of input port are coupled to this respectively to differential input signal and the pair of output mouth is coupled to described glitch smoothing circuit, and wherein said input buffer circuit is configured to set the working range of described glitch smoothing circuit.

15. according to the described laser driver circuit of claim 144, this comprises input buffer circuit:

The first transistor, its base terminal are coupled to this first input to differential input signal, and emitter terminal is coupled to first input end of described glitch smoothing circuit and is coupled to first current source; And

Transistor seconds, its base terminal are coupled to this second input to differential input signal, and emitter terminal is coupled to second input terminal of described glitch smoothing circuit and is coupled to second current source.

16. laser driver circuit according to claim 9, it further comprises:

Acceptor circuit, it is configured to receive pair of differential input signals;

The 3rd differential amplifier circuit, it is coupled to the pair of output mouth of described acceptor circuit, and wherein said the 3rd differential amplifier circuit is configured to produce first and amplifies the differential wave and the second amplification differential wave;

The 4th differential amplifier circuit, its be coupled to described acceptor circuit by delay circuit this to output port, wherein said the 4th differential amplifier circuit is configured to produce the 3rd and amplifies differential wave and the 4th and amplify differential wave; And

Pair of output, it comprises first output node and second output node, wherein said first output node is configured to amplify differential wave and the described the 4th with described first and amplifies the differential wave combination and have the first differential output signal of level and smooth conversion with generation, and described second output node is configured to amplify differential wave and the described the 3rd with described second and amplifies the differential wave combination and have the second differential output signal of level and smooth conversion with generation.

17. according to the described laser driver circuit of claim 166, wherein said laser driver circuit be coupled into reception from digital interface circuit should be to differential input signal, and wherein said laser driver circuit is configured to the pair of differential current signal to laser diode is driven.

18. according to the described current modulator circuit of claim 166, wherein said acceptor circuit comprises:

The first transistor, its base terminal are coupled to first input of described acceptor circuit, and collector terminal is coupled to power supply, and emitter terminal is coupled to first bias current sources and be coupled to first output port of described acceptor circuit;

Transistor seconds, its base terminal are coupled to second input of described acceptor circuit, and collector terminal is coupled to described power supply, and emitter terminal is coupled to second bias current sources and be coupled on second output port of described acceptor circuit.

19. according to the described current modulator circuit of claim 166, wherein said the 3rd differential amplifier circuit comprises:

First lead-out terminal, the collector terminal that the first transistor, its base terminal are coupled to described acceptor circuit is coupled to power supply by first resistor and is coupled to first output of described current modulator circuit and emitter terminal is coupled to first bias current sources;

Transistor seconds, its base terminal is coupled to second lead-out terminal of described acceptor circuit, collector terminal is coupled to described power supply by second resistor and is coupled to second output of described current modulator circuit, and emitter terminal is coupled to the emitter terminal of described the first transistor.

20. current modulator circuit according to claim 19, wherein said the 4th differential amplifier circuit comprises:

The 3rd transistor, its base terminal is coupled to first output of described delay circuit, collector terminal is coupled to described power supply by described second resistor and is coupled to second output of described current modulator circuit, and emitter terminal is coupled to second bias current sources;

The 4th transistor, its base terminal is coupled to second output of described delay circuit, collector terminal is coupled to described power supply by described first resistor and is coupled to first output of described current modulator circuit, and emitter terminal is coupled to the described the 3rd transistorized emitter terminal.

21. current modulator circuit according to claim 16, wherein said delay circuit comprises:

First resistor network, it is coupling between second input port of first output port of described acceptor circuit and described the 4th differential amplifier circuit, and wherein said first resistor network is configured to amplify the described the 4th and produces scheduled time displacement on the differential wave; And

Second resistor network, it is coupling between the first input end mouth of second output port of described acceptor circuit and described the 4th differential amplifier circuit, and wherein said second resistor network is configured to amplify the described the 3rd and produces scheduled time displacement on the differential wave.

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