CN1938954A - Method for reducing intersymbol interference, sigma-delta converter for implementing the method and storage medium for transmitting information generated by the method - Google Patents

Abstract

A method and arrangement are provided for reducing inter-symbol interference that occurs in digital-to-analog conversion of a 1-bit digital signal stream. In a sigma-delta converter, during the generation of a 1-bit digital signal, the edge density of the digital signal is measured, the result of the measurement is multiplied with the digital signal, and the result of the multiplication is added to the input of a quantizer for generating the digital signal. The invention also relates to a storage medium comprising a 1-bit digital signal generated according to the invention.

Description

Method for reducing intersymbol interference, sigma-delta converter for performing the method and storage medium for transmitting information generated by the method

The invention relates to a method for reducing the intersymbol interference which occurs during the digital-to-analog conversion of a 1-bit digital signal stream.

via a 1-bit DA converter. A highly linear digital-to-analog conversion can be obtained, where it is not used for inter-symbol interference (ISI), the distortion of which is caused by the DA converter. Intersymbol interference occurs when the actual analog output of the DA converter depends not only on the actual digital input code, but also on the previous digital input code. As a result of this "memory" effect, components not present in the digital input code appear in the analog output of the DA converter.

Intersymbol interference can be caused, for example, by parasitic capacitances of the DA converter switching reference (e.g. current source), as well as by the DC offset of the operational amplifier to which the switching reference is provided, with the result that, each time the DA converter switches, no Avoid having extra charge packets dumped out to the output. When the digital signal is a 1-bit digital signal stream, the DA converter used to return the signal in analog form will switch multiple times between the signal zero crossing and less than the signal peak. Since one cycle of a sine wave has two zero crossings and two peaks, the extra charge packets represent even (second) order distortion.

In some cases, the DA converter loads its reference with the result that the reference itself contains even (second) order components. This DA-referenced second-order signal is multiplied by the input code, resulting in odd (third-order) harmonic distortion at the output of the DA converter.

In the prior art, a method for reducing inter-symbol interference is to turn on the DA reference in a part of the clock cycle, and turn off the DA reference in another part of the clock cycle. Then, in each clock cycle there are additional charge packets which contribute to the DC signal at the output of the DA converter. The disadvantage of this method is that the output signal of the DA converter becomes smaller, so that it has to be increased to obtain the same output level, at the same time, switching consumes power, so that additional switching means additional power loss, and, The circuitry following the DA converter must be able to handle "rippled" input signals. At the same time, the sensitivity to timing jitter increases.

The present invention provides a method that does not exhibit these disadvantages, and at the same time, according to the present invention, provides a method for reducing intersymbol interference, wherein said generation of a 1-bit digital signal stream includes the following steps: trellis-delta structure, converting the input signal into said 1-bit digital signal stream, the output of the low-pass filter is connected to the input of the quantizer, and the output of the quantizer is fed back to the low-pass filter Therefore, the method is characterized in that generating a control signal representing the edge density of the 1-bit digital signal stream at the output of the quantizer; multiplying the control signal by said 1-bit digital signal stream; and The result of the multiplication, along with the output of the low-pass filter, is applied to the input of the quantizer. The present invention provides a method for substantially reducing the edges of a 1-bit digital signal stream during signal zero crossings, thereby more evenly distributing the edges, thus reducing the signal content of intersymbol interference. Note that in the prior art method described above, the reduction of ISI is done in the DA conversion, ie after the generation of the 1-bit digital signal stream, with all the disadvantages as mentioned above. In contrast, according to the present invention, the reduction of intersymbol interference is achieved by controlling the generation of the 1-bit digital stream itself.

US patent 6351229 shows a sigma-delta converter in which a signal-dependent pseudo-random sequence is added at the input of the quantizer. The purpose of this method is to avoid tones which would otherwise occur due to the regular nature of the bit sequence produced by the converter, and the method does not sufficiently reduce the density of edges in this sequence.

It is also known to reduce the edges of pulse width modulated signals intended for class D power amplifiers. Because in a Class D power amplifier, each edge dissipates a certain amount of energy, it is important to keep the number of edges as small as possible. However, this known method would cause large audio distortions or require complex digital circuits.

Methods and arrangements according to the invention result in substantially less audio distortion and/or are easier to implement. Also, the method and arrangement according to the invention are particularly suitable for reducing edges at the beginning of digital transfer, ie during analog-to-digital conversion of a signal. Then, these edge-reduced signals can be conveniently recorded on a storage medium in the form of 1-bit numbers.

The present invention also provides a 1-bit Sigma-Delta converter for converting an input signal into a 1-bit digital signal stream, said converter comprising a quantizer having an input and an output; a low-pass filter , whose output is connected to the input of the quantizer, and the input is connected to the output of the quantizer, thereby forming a feedback configuration with a quantizer; means for providing an input signal to the feedback configuration, and from the quantizer A device that obtains a 1-bit digital signal stream at its output. The converter is characterized by an edge density controller connected to the output of the quantizer for providing a control signal indicating the edge density of the 1-bit digital signal stream; a multiplier for multiplying said control signal by the quantized a 1-bit digital signal stream to the quantizer; and means for applying the output of the multiplier to the input of the quantizer.

The 1-bit Sigma-Delta converter according to the present invention is also characterized in that the edge density controller includes an edge-extractor (edge-extractor) connected to receive the 1-bit digital signal stream of the quantizer; The pass filter is used to receive the output signal of the edge extractor and provide the control signal. This second low-pass filter suppresses inter-symbol interference in the frequency band of interest and shapes this interference to higher frequencies, just as the low-pass filter of an ordinary Sigma-delta modulator suppresses quantization in the frequency band of interest noise, and shaping that noise to higher frequencies. In the case of the low-pass filter of the sigma-delta modulator, the second low-pass filter will suppress more interference if the order of the second low-pass filter is higher.

The 1-bit sigma-delta converter according to the invention is also characterized in that the source of the reference signal is connected to a second low-pass filter for providing a reference for the level of the control signal. This reference signal allows controlling the reduction of inter-symbol interference that can be achieved. The reference signal can be a DC value with a positive or negative value. The reference signal may also contain time-dependent components. The reference signal may be applied to the input, or output, or somewhere between the input and output of the second low pass filter.

A simple implementation of the 1-bit Sigma-delta converter according to the invention is characterized in that the second low-pass filter is an integrator and that the reference signal is applied to the integrating input terminal of the device. In this structure, any edge in the digital bit stream of the quantizer will cause the control signal to increase, and the absence of any edge will cause the control signal to decrease. The net result is that the ratio between the amplitude of the edge extractor pulse and the amplitude of the reference signal determines the ratio between the clock period without an edge and the clock period with an edge, and is related to whether the input signal to the converter is in Doesn't matter at peak or zero crossing.

Obviously, preferably, the edge extractor extracts all edges of the digital bit stream. However, it is also possible for the decimator to decimate only part of the edges, eg only rising edges or only falling edges. Then, the reference signal should be adjusted accordingly.

As mentioned above, the main advantage of the present invention is a more even distribution of edges over the clock period of the digital output signal. This results in a substantial reduction in inter-symbol interference in the frequency band of interest. One aspect that has to be considered is the inherent drop in the maximum input signal level of the converter caused by this. Due to the addition of edges to the digital signal at the extremes of the signal, the maximum input signal level decreases relative to full scale. In order to limit the drop in the maximum input level, the setting of the inventive converter, in particular of the reference signal mentioned above, is preferably such that the average number of clock periods including edges is less than 40%. Typically, however, the 1-bit digital signal produced by prior art Sigma-delta converters includes edges in about 65% of the clock period, and the digital output signal produced according to the present invention preferably includes edges in about 20% of the clock period. has an edge. It may be noted that the invention also relates to a storage medium having at least one signal track stored thereon in the form of a 1-bit digital stream and which is characterized in that in the 1-bit digital stream of said signal track The number of clock cycles including edges is less than 40% of the total number of clock cycles of the 1-bit digital stream of the signal track. In this application, the term "signal track" means an audio or video signal of at least one minute duration. When the program is read from the storage medium, the intersymbol interference occurring during the digital-to-analog conversion of the 1-bit digital stream is substantially less than that occurring during the digital-to-analog conversion of the 1-bit digital stream from the prior art storage medium.

It must be noted that the 1-bit digital stream may undergo an encoding step before being written to the storage medium to make the signal more suitable for the writing process. While reading the storage medium, and before the DA conversion of the signal, corresponding decoding is carried out. In this case, the advantages of the invention are maintained, since it is not the edges in the storage medium, but the edges applied to the DA converter, which are the cause of the inter-symbol interference. Also, if said encoding step is used to compress a signal stored on a storage medium, the compression itself will also be improved due to the reduction of edges in the compressed signal.

Since only one reference (current source) is involved in the DA conversion of such signals, 1-bit digital signals have the advantage of optimal linearization. However, the main disadvantage of 1-bit digital signals is that a large amount of quantization noise is included in the generation of the signal. If a multi-bit digital signal is used, then the amount of quantization noise will be substantially minimized. The problem with multi-bit digital signals is that DA conversion requires multiple references, and any inequalities between these references cause non-linear distortion of the analog signal.

Non-linear distortions are substantially reduced by dynamic unit matching, which is a well-known algorithm that uses each of multiple references in the DA conversion of each signal value. From Norsworthy S.R.and Schreier R.and Temes G.C.Delta-SigmaConverters, Theory, Design and Simulation.IEEE Press, New York, 1997pp260-264 It can be known that in the implementation of this algorithm, multi-bit Sigma-Delta can be used A converter comprising a plurality of interconnected 1-bit Sigma-delta converters, wherein each 1-bit Sigma-delta converter has: a low-pass filter in a feedback configuration, and the feedback A configuration having one of a plurality of interconnected quantizer means; means for providing an input signal to said plurality of quantizer means; and means for obtaining a multi-bit digital signal from an output of the plurality of quantizer means. According to another aspect of the invention, the multi-bit Sigma-delta converter is characterized in that each output of the plurality of quantizer means is connected to an edge detector for providing a control signal indicating an edge of the 1-bit digital stream at the output; a multiplier for multiplying the control signal by the 1-bit digital stream at the output; and means for applying the result of the multiplication to respective inputs of the quantizer means .

The present invention will be described with reference to the accompanying drawings.

Shown here:

Fig. 1 is a 1-bit Sigma-delta converter according to the present invention;

FIG. 2 is a diagram for explaining the operation of a 1-bit Sigma-Delta converter according to the present invention; and

Figure 3 is an example of a multi-bit Sigma-delta converter according to the present invention.

The 1-bit Sigma-Delta converter of FIG. 1 comprises a Sigma-Delta modulator SD having an analog signal input I and a digital signal output O. The analog signal S _I at the input I is applied to an analog low-pass filter F via an addition point _P1 , and the filtered signal _SF is applied to a 1-bit clocked quantizer Q via a second addition point _P2 , in this case , the quantizer can be in the form of a simple clocked comparator. The quantizer generates a +1 pulse every time during a clock pulse the input signal to the quantizer exceeds a predetermined reference level ("zero"), and a -1 when the signal remains below said predetermined level pulse. The 1-bit digital output pulse So of the quantizer Q is converted into an analog pulse in the DA converter H and subtracted from the analog input signal S _I at the addition point _P1 . A well-known consequence of this Sigma-delta configuration is that there are multiple +1 pulses in the output signal So when the input signal S _I is most positive and many -1 pulses when the input signal is most negative , alternates between +1 and -1 pulses when the input signal is at or near zero. If the Sigma-delta modulator is properly designed, the quantization noise generated by the quantizer will form a frequency band between the frequency band of the input signal and half the clock frequency. In order to give enough room to the quantization noise, therefore, the clock frequency should be chosen high enough.

In particular, a large number of edges in the output signal _SO during zero crossings of the input signal, not only in the DA converter H of the feedback path of the Sigma-delta modulator M, but also in any digital output signal So In the DA converter that converts back to analog signal form, both are serious sources of intersymbol interference. In order to reduce the large number of edges, especially during the zero crossings of the input signal, the arrangement of Fig. 1 comprises an edge decimator E whose input receives the output signal So of the Sigma-delta modulator. In one clock cycle, the edge extractor generates the signal S _E , when the signal So changes in the previous clock cycle, the signal S _E is "high", and when the signal does not change in the previous clock cycle, the signal S _E to "Low". The edge extractor E may for example comprise an XOR gate with two inputs, one of which receives the signal So directly and the other input receives the signal So via a clocked D flip-flop. The signal S _E is then applied to the summing point P ₃ , wherein the signal S _E can be regarded as an analog signal, for example "high" = 1 volt, "low" = 0 volts, at the summing point P ₃ , subtracted from the signal S _E The reference voltage _VP is, for example, 0.2 volts. When an edge has occurred in the previous clock cycle, then the result of the subtraction of _{SE -VP} is 0.8 volts, and when no edge occurred in the cycle, then the result of the subtraction of _{SE -VP} is -0.2 volts. Or, in other words, when the edge occurs in 20% of the clock period, then the average value of the signal _SE - _VP will be zero, when the edge occurs in more than 20% of the clock period, then the average value will be positive, when When edges occur in less than 20% of the clock period, then the average is negative.

The integrator N receives the signal _{S E} -V _P and generates a control signal S _C whose value rises when an edge appears in the output signal So for more than 20% of the clock period, and when it is lower than If an edge occurs in 20% of the clock cycle, the value of control signal S _C falls. In the multiplier M, the control signal S _C is multiplied by the 1-bit signal S _O from the Sigma-Delta modulator, and in the second addition point P ₂ , the output signal of the multiplier S _O × S _C is combined with the filter The outputs of F are summed.

Referring to Fig. 2, the combined operation of quantizer Q, multiplier M and adding point _P2 is explained. The figure shows the output value S _O (+1 or -1) of the quantizer on the vertical axis, and the value of the output signal S _F of the low-pass filter F on the horizontal axis. The values given below are only examples and relate to the value of the output pulse.

If the control signal S _C is zero, then the output of the multiplier M is also zero and the quantizer output S _O will switch between points A and C of Fig. 2 under the control of a small change in the filter output signal S _F. This is depicted in Figure 2 by bold lines.

However, now assume that the edge density controller G delivers a control signal S _C with a value of 0.3.

a. When the quantizer output signal S _O =-1 (and the filter output signal S _F is substantially zero), the multiplier M transmits the signal S _O × S _C =-0.3 to the quantizer, and the quantizer state remains unchanged ( At point A) in Figure 2. Even if the filter output signal S _F changes by a small value, the output of the multiplier -0.3 will keep the output of _P2 negative, so that the state of the quantizer remains unchanged.

b. Only when the filter signal S _F increases to S _F =+0.3, the output of the addition point P ₂ increases to 0 and the output of the quantizer switches to +1. The multiplier output becomes S _O × S _C = 0.3, and the output of P ₂ is further increased to S _F + S _O × S _C = 0.3 + 0.3 = 0.6 (point B).

c. The quantizer state is maintained when the filter signal S _F drops eg to zero (point C of Fig. 2), or even when the filter signal drops to -0.25.

d. Only when the filter signal S _F drops to -0.3, the output of the addition point _P2 drops to 0, the quantizer Q switches to S _O = -1, and the output of the multiplier becomes S _O × S _C = -0.3, The output of P ₂ drops further to -0.6 (point D).

From the above it is evident that the switching behavior of the quantizer has hysteresis and is significantly reduced due to positive values of the control signal S _C . Only when the value of the filter signal S _F is above the value 0.3 or below -0.3, the quantizer switches and an edge appears in the output of the quantizer. The larger the value of the control signal S _C , the larger the value of the filter signal S _F for quantizer switching should be.

On the other hand, it can be easily seen that the quantizer Q switches easily at half the clock frequency when the control signal S _C is negative, even when the filter signal S _F is zero. In this case, the quantizer Q, multiplier M, and summing point _P2 together form an oscillator that generates an edge at each clock pulse. However, this large number of edges will quickly lead to the formation of positive values of the control signal _SC , so that by the above-mentioned mechanism, the number of edges will be greatly reduced.

A control circuit with an edge density controller G and a multiplier M limits the number of edges in the digital output signal _S0 to a certain average value. In the configuration of Fig. 1, this average value can be easily found, since the average value of the input signal to the integrator N must be zero (otherwise the output signal _SC of the integrator will rise or fall steadily). For example when the value of the signal S _E is 1 with an edge and 0 without an edge, and when the value of the reference voltage V _P is 0.2, then, since the signal S _E of the integrator N _-VP should necessarily have a zero DC component, so the signal _SE will have _SE = 1 in 20% of the clock cycles and SE ₌ 0 in 80% of the clock cycles. So, the control circuit has reduced the number of edges so that the edges only occur in 20% of the clock cycles. For more edges the reference voltage _VP has to be increased, for fewer edges the voltage will be chosen lower.

The effect of the control circuit on the maximum input signal level of the converter is described below.

Assume that the reference voltage _VP is set such that the output signal of the converter has edges in 20% of the clock period. The signal can then consist of the following loop of 10 clock cycles:

a. When the input signal of the converter is positive extreme value: +1, +1, +1, -1, +1, +1, +1, +1, +1, +1. The loop has two edges in 10 clock cycles, so that the number of clock cycles with edges is 20%. The value of the output signal is 9*(+1)+1*(-1)=8, ie 8/10=80% of the maximum value, so that the maximum input signal level has dropped to 80% of the full scale value.

b. When the input signal of the converter is zero: -1, -1, +1, +1, +1, +1, +1, -1, -1, -1. The loop again has 2 edges out of 10 clock cycles, so that the number of clock cycles with edges is still 20%. The output is 5*(+1)+5*(-1)=0.

c. When the input signal is negative extreme value: -1, -1, +1, -1, -1, -1, -1, -1, -1, -1. The loop again has two edges in 10 clock cycles, so that 20% of the clock cycles have edges. The value of the output signal is 9*(-1)+1*(+1)=-8, which is again 80% of the negative maximum value, so that the maximum input level has dropped to 80% of the full scale value.

For comparison, assuming that the converter is set up so that the edge occurs 50% of the clock cycle, the following cycle can be produced:

a. When the input signal of the converter is positive extreme value: +1, -1, +1, +1. This loop has two edges in 4 clock cycles, so that the number of clock cycles with edges is 50%. The value of the output signal is 3*1+1*(-1)=2, ie 2/4 of the maximum value=50%, so that the maximum input signal level has dropped to 50% of the full scale value.

b. When the input signal of the converter is zero: -1, +1, +1, -1. The loop again has 2 edges in 4 clock cycles, so that the number of clock cycles with edges is 50%. The output is 2*(+1)+2*(-1)=0.

c. When the input signal is negative extreme value: -1, -1, +1, -1. This loop has two more edges in 4 clock cycles, so that the number of clock cycles with edges is 50%. The value of the output signal is 3*(-1)+1*(+1)=-2, which is again 50% of the negative maximum, so that the maximum input signal level has dropped to 50% of the full scale value.

These examples clearly show that the reduction of the edges results in an increase in the maximum signal level contained in the output signal. This reduction will also further reduce the inter-symbol interference generated during the digital-to-analog conversion of the signal.

The edge-reduced digital output signal stream _SO may be applied to any suitable digital signal processor, such as a storage medium, represented by disc J in FIG. 1 . The digital signal read from the storage medium is applied to a digital-to-analog converter K. Any intersymbol interference generated in the DA converter K is sufficiently shifted out of the frequency band of interest by a more uniform distribution of edges in the digital signal, and by a reduction in the average number of edges in the signal that any intersymbol interference generated in the DA converter K Intersymbol interference is substantially reduced.

It can be noted that various modifications can be made to the structure of the edge density controller G without departing from the scope of the present invention. For example, the reference voltage source _Vp may occasionally be omitted when the pulses delivered by the edge extractor E are below zero and no edges are present. Also, the loop filter N does not have to be an integrator. A second-order low-pass filter was tried and found to have better ISI suppression performance than a first-order low-pass filter. In the case of a first-order or second-order low-pass filter, instead of the input signal from the low-pass filter, the reference signal _Vp can be subtracted from its output signal. The reference signal V _P does not have to be only a DC value. Adding time-dependent components to this reference signal broadens or narrows the spectral output components of the oscillator composed of elements Q, M, _P2 and G.

In FIG. 1, the present invention has illustrated an analog Sigma-delta modulator and an analog control circuit. The invention is also applicable to digital Sigma-delta modulators and/or digital control circuits. In that case, operations such as addition, multiplication, low-pass filtering and edge decimation can be performed using appropriate digital codes.

In the multi-bit Sigma-delta converter of FIG. 3, elements corresponding to those in FIG. 1 bear the same reference numerals. The converter of Figure 3 is intended to directly drive multiple 1-bit DA converters. The DA converter (not shown) is switched by the 1-bit output signal on the outputs _O1 , _O2 , _O3 of the multi-bit converter. The input S _I of the converter is a 2-bit digital signal with 4 possible values 0,1,2,3. These values can be recovered in analog form by three 1-bit DA converters. Since the references (current sources) of these DA converters are usually not exactly equal to each other, during the digital-to-analog conversion, non-linear distortion occurs. These errors can be reduced by the known method "dynamic cell matching". With this method, each analog reference is switched alternately to generate each analog value.

To this end, the multi-bit converter of Figure 3 effectively consists of three 1-bit Sigma-Delta converters, each with: its own low-pass filter F, and in It has its own quantizer in the feedback configuration, which has its own low-pass filter. The three quantizers are combined into a vector quantizer VQ. The vector quantizers include a controller that is driven by the input signal _SI and controls each quantizer in turn according to the required DEM algorithm.

According to the present invention, each 1-bit input of the vector quantizer includes an addition point P ₂ , an edge decimator E, an addition point P ₃ for a reference value V _P , an integrator N and a multiplier M, as shown in Fig. 1 connection shown. In this way, multi-bit converters are provided that not only perform "dynamic element matching" to account for unequal references to DA converters, but also reduce inter-symbol interference caused by memory effects inherent in these DA converters .

The multi-bit converter of Figure 3 is given only by way of a simple example, where the example has a 2-bit input signal and a 3-bit output. In general, a 1-bit Sigma-delta converter with a greater number of interconnections has a greater corresponding number of bits for the input and output signals.

Claims (7)

1, a kind of minimizing appears at the method for the intersymbol interference in the digital-to-analogue conversion of one bit digital signal stream, described one bit digital signal stream (S _o) generation comprise the steps: sigma-delta configuration (SD) by low pass filter (F), input signal is converted to described one bit digital signal stream, the output of this low pass filter is connected to the input of quantizer (Q), the output of this quantizer feeds back to the input of this low pass filter, it is characterized in that: produce control signal (S _C), on behalf of output (O) place of described quantizer, this control signal state the edge density of one bit digital signal stream; With described control signal (S _C) multiply by described one bit digital signal stream (S _o); And the input that the output of multiplication result and described low pass filter (F) is put on together described quantizer (Q).

2, a kind of 1 sigma-delta transducer is used for input signal (S _I) convert one bit digital signal stream (S to _o), described transducer comprises: quantizer (Q) has input and output; Low pass filter (F), the output of this low pass filter is connected to the input of described quantizer, and the input of this low pass filter is connected to the output of described quantizer, constitutes thus to have the feedback configuration of described quantizer; Be used for providing input signal (S to described feedback configuration _I) device (P ₁); And the device (O) that is used for obtaining from the output of described quantizer described one bit digital signal stream, it is characterized in that: be connected to the edge density controller (G) of the output (O) of described quantizer, be used to provide control signal (S _C), this control signal is indicated described one bit digital signal stream (S _o) edge density; Multiplier (M) is used for described control signal (S _C) multiply by the described one bit digital signal stream (S of described quantizer _o); And the device (P that is used for the output of this multiplier is put on the input of described quantizer ₂).

3,1 sigma-delta transducer as claimed in claim 2 is characterized in that, described edge density controller (G) comprises edge withdrawal device (E), and it connects to receive the described one bit digital signal stream (S of described quantizer _o); Second low pass filter (N) is used to receive the output signal (S of described edge withdrawal device _E), and described control signal (S is provided _C).

4,1 sigma-delta transducer as claimed in claim 3 is characterized in that derived reference signal (V _P), be connected to described second low pass filter (N), be used to described control signal (S _C) level reference is provided.

5,1 sigma-delta transducer as claimed in claim 3 is characterized in that, described second low pass filter (N) is an integrator, and the input that reference signal is put on this integrator with the polarity opposite with the withdrawal device pulse of described edge.

6, a kind of multidigit sigma-delta transducer, be used for input signal (SI) is converted to multistation digital signal, described transducer comprises: 1 sigma-delta transducer of a plurality of interconnection, wherein each 1 sigma-delta transducer has the low pass filter (F) in the feedback configuration, and this feedback configuration have a plurality of (VQ) interconnection quantizer means in one; Input signal is put on the device of described a plurality of quantizer means; With output (O from described a plurality of quantizer means ₁, O ₂, O ₃) obtain the device of multistation digital signal, it is characterized in that: each output of described a plurality of quantizer means is connected to edge density controller (G), is used to provide control signal, and this control signal is indicated the edge of the described 1 bit digital stream of described output; Multiplier (M) is used for described control signal be multiply by the described 1 bit digital stream of described output; And the device (P that multiplication result is put on each input of described quantizer means (VQ) ₂).

7, a kind of storage medium (J), store the streamed signal track of at least one 1 bit digital on it, it is characterized in that, comprise the clock periodicity at the edge in the described 1 bit digital stream of described signal track, less than 40% of the total clock cycle number of the described 1 bit digital stream of described signal track.

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