CN1933328A - Pulse generating circuit, electronic device using this pulse generating circuit, and information transmitting method using this circuit - Google Patents

Abstract

The invention provides a pulse generating circuit, equipment using the circuit and an information transmission method. The pulse generation circuit can easily generate a high-frequency band pulse with low power consumption using a simple circuit, and can be realized without using a high-cost semiconductor process. The pulse generating circuit is constituted by: inverting circuits (101-109) connected in cascade in a predetermined number of stages; ～109) in the input and output side of an inverting circuit is connected, produces the pulse of the time width equivalent with the delay amount of the inverting circuit (102,104,106,108) of this connected stage; And NOR circuit ( 114) which takes the OR of the outputs of these NAND circuits (110-113).

Description

The equipment and the information transferring method of pulse-generating circuit and this circuit of use

Technical field

The present invention relates to be suitable for UWB (Ultra Wide Band: ultra broadband) Tong Xin pulse-generating circuit and the electronic installation of this circuit of use and the information transferring method that uses this circuit.

Background technology

UWB communication is the communication mode that utilizes the frequency band of non-constant width to carry out the high-speed high capacity data communication.Utilize the communication mode of broadband signal that in the past method and OFDM (OFDM) method based on spread spectrum are arranged, yet UWB utilize the unusual communication mode of the ultra broadband of short pulse of time, is called the communication of impulse radio (IR) mode again.In the IR mode, irrelevant with in the past modulation, only need just can carry out modulation by the operating time axle, think simplification or the low power consumingization (with reference to patent documentation 1,2,3) that can expect circuit.

Here, the impulse waveform of using is carried out simple declaration in the IR mode.Pulsewidth P shown in Figure 16 (a) _D, period T _PPulse train be well-known, the frequency spectrum of this pulse train is that envelope is at BW=1/P shown in Figure 16 (b) _DFrequency the time have a sinc function at initial zero point.

Under the situation of this pulse, because frequency spectrum is from the current extended DC to BW, thereby be difficult to use, preferably the centre frequency f of the frequency spectrum shown in Figure 17 (b) is in the pulse of high position.

That is, this pulse has the impulse waveform shown in Figure 17 (a), is that frequency f is multiply by in the pulse of Figure 17 (a) _O=1/2P _WSquare wave and pulse that frequency spectrum is moved towards eminence.Yet this waveform comprises direct current (DC) component shown in the chain-dotted line 1701 of Figure 17 (a), says exactly, does not have with the frequency spectrum shown in the figure (b).Communication is that desirable impulse waveform has also been done various designs to UWB, and different with the waveform here, yet because production method is simple, thereby frequent the use.

Figure 18 (a) is the examples of circuits in the past (non-patent literature 1) that is used to produce pulse shown in Figure 17 (a).

As shown in the figure, two inverters 1801,1802 and NOR circuit (NOR) 1803 are " vacation " (L: in the time of low level), constitute 3 grades of ring oscillators at another input C of NOR 1803.That is, the sequential chart shown in the image pattern 18 (b) is such, and C only vibrates during L, and output NR1, the N1 of NOR 1803 and inverter 1701,1802, time of delay, t propagated respectively in the variation of N2.Here, for simplicity, suppose that the rise time of NOR 1803 and inverter 1701,1802 and fall time all equate.Therefore, { Pw} of Figure 17 (a) is 3t to the pulsewidth that produces in this circuit.That is, 3 of the time of delay of the element of forming circuit times is producible short pulse duration.

[patent documentation 1] US Pat.6421389

[patent documentation 2] Pub.No.:US2003/0108133A1

[patent documentation 3] Pub.No.:US2001/0033576

[non-patent literature 1] A CMOS IMPULSE RADIO ULTRA-WIDE BANDTRANCEIVER FOR 1Mb/s DATA COMMUNICATION AND ± 2.5cmRANGE FINDINGS T.Teradaet.al, 2005 Symposium on VLSI CircuitsDigest of Technical Papers, pp.30-33

Yet, in the time will using above-mentioned pulse-generating circuit in the past to obtain required high frequency band pulse, must use element, yet in reality, obtain this element and be unusual difficulty with abundant speed, or impossible.

And generally speaking, in the time will making the element high speed motion, power consumption increases, and therefore, in the time will using that sort circuit was obtained very short pulse in the past, the increase of power consumption is inevitable.And, even the reduction of power consumption also is strong expectation under following situation, that is: wireless and carry out as allowing between a plurality of housings that the form of relative displacement cut apart about posture or position or the signal transmitting and receiving in point blank in the same housing to be combined into.

Summary of the invention

Therefore, the purpose of this invention is to provide a kind of high frequency band pulse and simple in structure, few pulse-generating circuit of power consumption and information providing method of using the electronic installation of this circuit and using this circuit of being easy to generate.

In order to solve above-mentioned problem, following listed technology has been proposed in this application.

Pulse-generating circuit according to a mode of the present invention, it is characterized in that, a plurality of delay key elements are carried out cascade to be connected to constitute the regulation loop, when the input pulse of regulation is provided for the top portion of this cascade connection, use the signal of discovery among a plurality of of regulation in each one of the terminal part that logical circuit is connected with this cascade the node portion between these a plurality of delay key elements to implement effective frequency multiplication processing, obtain the output pulse higher than above-mentioned input pulse frequency.

In this pulse-generating circuit, connect the pulse output that obtains assigned frequency with a plurality of delay key elements that constitute the regulation loop by having carried out cascade, the signal of a plurality of discoveries of the regulation in each one of the terminal part that this pulse output is connected with this cascade the node portion between a plurality of delay key elements by logical circuit is implemented effective frequency multiplication processing, obtains the high output pulse of desired frequency.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: progression has carried out the delay circuit that cascade connects in accordance with regulations; A plurality of the 1st logical circuits, it is connected with the output of this delay circuit, produces the pulse of the time width suitable with per 1 grade retardation of this delay circuit; And the 2nd logical circuit, its obtain these the 1st logical circuits output " or ".

Therefore, owing to can use logical circuit to extract the retardation of delay circuit out a plurality of synthesizing, thereby can make the pulsewidth that produces pulse narrow to the retardation of delay circuit.In the prior art, 3 times of the retardation of delay circuit is the narrowest obtainable pulsewidth, by contrast, can realize significantly improving.Delay circuit can be made of the buffer circuit of semiconductor element etc., as long as use the fast element of response speed, and the time of delay in the time of just making pulsewidth shorten to the fast motion of this element.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: delay circuit, its buffer circuit that can carry out electric control to retardation progression in accordance with regulations carry out cascade and are formed by connecting; A plurality of the 1st logical circuits, it is connected with the output of this delay circuit, produces the pulse of the time width suitable with per 1 grade retardation of this delay circuit; The 2nd logical circuit, its obtain these the 1st logical circuits output " or "; Comparison circuit, the retardation of its above-mentioned delay circuit and benchmark retardation compare; And the circuit of controlling the retardation of above-mentioned buffer circuit according to the output of this comparison circuit.

Therefore, realize owing to delay circuit can connect by the cascade of simple buffer circuit, thereby implement easily.And, because its retardation compares with the retardation that becomes benchmark and be controlled, thereby can produce high-precision pulse.Particularly, also can solve the problem that difference that semiconductor technology causes etc. is made easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: delay circuit, its 1st buffer circuit that can carry out electric control to retardation progression in accordance with regulations carry out cascade and are formed by connecting; A plurality of the 1st logical circuits, it is connected with the output of this delay circuit, produces the pulse of the time width suitable with per 1 grade retardation of this delay circuit; The 2nd logical circuit, its obtain these the 1st logical circuits output " or "; Oscillating circuit, it is equipped with the 2nd buffer circuit with electrical characteristic similar to above-mentioned the 1st buffer circuit; And phase-locked loop, it comprises this oscillating circuit, and comes the retardation of above-mentioned the 2nd buffer circuit is carried out FEEDBACK CONTROL by the relatively output and the reference frequency of this oscillating circuit, so that the frequency of oscillation of this oscillating circuit is phase-locked to reference frequency; Described pulse-generating circuit is controlled to the retardation of above-mentioned the 1st buffer circuit identical with the FEEDBACK CONTROL of above-mentioned phase-locked loop.

Therefore, realize owing to delay circuit can connect by the cascade of simple buffer circuit, thereby implement easily.And, because its retardation is subjected to control with the result that the frequency that becomes benchmark compares using with the frequency of oscillation of the oscillating circuit of the equal element of the element that constitutes delay circuit, thereby can be easy to generate high-precision pulse.Particularly, also can solve the problem that difference that semiconductor technology causes etc. is made easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: delay circuit, its buffer circuit that can carry out electric control to retardation progression in accordance with regulations carry out cascade and are formed by connecting; A plurality of the 1st logical circuits, it is connected with the output of this delay circuit, produces the pulse of the time width suitable with per 1 grade retardation of this delay circuit; The 2nd logical circuit, its obtain these the 1st logical circuits output " or "; Switch element, it is connected the input of the output of buffer circuit of regulation level of above-mentioned delay circuit and this delay circuit and forms annular oscillation circuit; Phase-locked loop, it comprises this annular oscillation circuit; And the signal during to reference frequency remains the unit of control signal of the retardation of above-mentioned buffer circuit by this pll lock; Described pulse-generating circuit is the action timing setting of the above-mentioned the 1st and the 2nd logical circuit the moment that above-mentioned phase-locked loop is disengaged and the retardation of the above-mentioned buffer circuit retardation when being controlled so as to locking with above-mentioned phase-locked loop equates.

Therefore and since constitute the retardation of the buffer circuit of pulse-generating circuit be used for by switch this buffer circuit constitute phase-locked loop, and the pulse of control voltage when keeping locking produce, thereby can produce accurate pulse.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: oscillating circuit, and it is formed by connecting multilevel delay circuit and 1 gate circuit in the form of a ring; A plurality of the 1st logical circuits, it produces the pulse of the time width suitable with this retardation at different levels according to the output at different levels of this oscillating circuit; And the 2nd logical circuit, its obtain these the 1st logical circuits output " or ".

Therefore, can use the vibration of gate circuit control annular oscillation circuit, and, use the 1st and the 2nd logical circuit to extract the pulse train suitable out and generate narrow pulse train with retardation at different levels in this oscillating circuit duration of oscillation.And, because during this oscillating circuit persistent oscillation, can continue the generation pulse, thereby can produce the pulse train more than the exponential quantity and do not increase the number of elements of circuit.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, above-mentioned delay circuit constitutes: can control retardation, and this retardation can be controlled so as to setting.

Therefore, because the retardation may command of delay circuit, thereby can obtain the pulse that becomes the regulation of target pulsewidth easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: oscillating circuit, and it can be formed by connecting in the form of a ring to a plurality of buffer circuits and the gate circuit that retardation is carried out electric control; A plurality of the 1st logical circuits, it produces the pulse of the time width suitable with this retardation at different levels according to the output at different levels of this oscillating circuit; The 2nd logical circuit, its obtain these the 1st logical circuits output " or "; Comparison circuit, its above-mentioned retardation at different levels and benchmark retardation compare; And the circuit of controlling the retardation of above-mentioned buffer circuit according to the output of this comparison circuit.

Therefore, realize owing to oscillating circuit can connect by the cascade of simple buffer circuit, thereby implement easily.And, because its retardation compares with the time of delay that becomes benchmark and be controlled, thereby can produce high-precision pulse.Particularly, also can solve the problem that difference that semiconductor technology causes etc. is made easily.And, because during this oscillating circuit persistent oscillation, can continue the generation pulse, thereby can produce the pulse train more than the exponential quantity and do not increase the number of elements of circuit.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: oscillating circuit, and it can be formed by connecting in the form of a ring to a plurality of the 1st buffer circuits and the gate circuit that retardation is carried out electric control; A plurality of the 1st logical circuits, it produces the pulse of the time width suitable with this retardation at different levels according to the output at different levels of this oscillating circuit; The 2nd logical circuit, its obtain these the 1st logical circuits output " or "; Oscillating circuit, it is equipped with the 2nd buffer circuit with electrical characteristic similar to above-mentioned the 1st buffer circuit; And phase-locked loop, it comprises this oscillating circuit, and comes the retardation of above-mentioned the 2nd buffer circuit is carried out FEEDBACK CONTROL by the relatively output and the reference frequency of this oscillating circuit, so that the frequency of oscillation of this oscillating circuit is phase-locked to reference frequency; Described pulse-generating circuit is controlled to the retardation of above-mentioned the 1st buffer circuit identical with the FEEDBACK CONTROL of above-mentioned phase-locked loop.

Therefore, realize owing to oscillating circuit can connect by the cascade of simple buffer circuit, thereby implement easily.And, because its retardation compares with the time of delay that becomes benchmark and be controlled, thereby can produce high-precision pulse.Particularly, also can solve the problem that difference that semiconductor technology causes etc. is made easily.And, because during this oscillating circuit persistent oscillation, can continue the generation pulse, thereby can produce the pulse train more than the exponential quantity and do not increase the number of elements of circuit.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, above-mentioned controllable buffer circuit is made of CMOS inverter and unit that the electric current that flow in this CMOS inverter is controlled.

Therefore, owing to can use simple MOS circuit to realize the control of time of delay, thereby implement easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, above-mentioned controllable buffer circuit is the buffer circuit with cmos current mode logic circuit, and the inflow current control by this buffer circuit makes delay amount variable.

Therefore, because delay circuit is made of cmos current mode logic circuit, thereby can moves and increase operating power not significantly with the maximum speed of cmos circuit.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, the above-mentioned the 1st and the 2nd logical circuit has cmos current mode logic circuit.

Therefore, because logical circuit is made of cmos current mode logic circuit, thereby can moves and increase operating power not significantly with the maximum speed of cmos circuit.And, also be easy to generate the low-amplitude signal of the degree that can in common UWB communication, use.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, this pulse-generating circuit has: the delay circuit of the N+1 level that cascade connects; The 1st "AND" circuit, it obtains the output D of the i level of above-mentioned delay circuit _i" non-" XD with the output of the i-1 level of above-mentioned delay circuit _I-1Between " with "; The 2nd "AND" circuit, it obtains the output D of the i level of above-mentioned delay circuit _i" non-" XD _iOutput D with the i+1 level of above-mentioned delay circuit _I+1Between " with "; And switch element, when it is " very " in above-mentioned the 1st "AND" circuit output, be connected, when above-mentioned the 2nd "AND" circuit output is " very " with the 1st potential level, be connected with the 2nd potential level, in addition, be connected with the 3rd potential level, wherein, N is a positive integer, and i is the even number of 1≤i≤N.

According to said structure of the present invention, the i level of the delay circuit of the N+1 level (N is an integer) that connects according to cascade (between 2≤i≤output N) and " non-" of its previous output " with ", the pulse of the width that generation is suitable with the retardation of each grade of above-mentioned delay circuit, during this each pulsewidth, alternately be connected with the 2nd potential level with the 1st potential level, and when the output of above-mentioned "AND" circuit is not " very ", be connected with the 3rd potential level, thereby can produce pulse with DC component.And, because circuit does not have the analog circuit of handling small-signal, thereby can use and utilize the logical circuit of simple cmos semiconductor integrated circuit to realize, realize low power consumingization and cost degradation easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, above-mentioned delay circuit can be controlled retardation, and this retardation is controlled so as to setting.

According to said structure of the present invention, therefore the retardation at different levels of may command delay circuit, can obtain the pulse train that becomes the regulation of target pulsewidth.

And, pulse-generating circuit according to a mode of the present invention, it is characterized in that, above-mentioned delay circuit is made of the MOS inverter of N+1 level and the unit that the source current that flow in the above-mentioned MOS inverter is controlled, by the control of source current, this retardation of above-mentioned delay circuit is controlled to setting.

According to said structure of the present invention, because delay circuit can be made of simple MOS inverter, and its retardation can simply be adjusted by the source current that control flow in the above-mentioned inverter, thereby simple in structure, and can be set at setting to the retardation of this delay circuit easily.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, the above-mentioned the 1st or the 2nd "AND" circuit has the unit that the transit time of the output signal of making is not controlled with overlapping.

According to said structure of the present invention, because switch element is controlled so as to the transit time of the output signal that makes "AND" circuit and does not overlap, thereby can not make between above-mentioned the 1st, the 2nd potential level because of above-mentioned switch element short circuit, can reduce the electric current that flows into useless circuit, promptly there is big effect the low power consuming aspect of the circuit of so-called short circuit current.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, obtains the 2nd grade output D of delay circuit in above-mentioned the 1st "AND" circuit ₂" non-" XD with the 1st grade output of above-mentioned delay circuit ₁Between " with " "AND" circuit and above-mentioned the 2nd "AND" circuit in obtain the output D of the N level of above-mentioned delay circuit _N" non-" XD _NOutput D with the N+1 level of above-mentioned delay circuit _N+1Between " with " "AND" circuit have the time set that it is output as " very " and become than other short unit.

According to said structure of the present invention, the time set that can be connected with the 1st or the 2nd potential level at the forward position and the back edge handle of output pulse must be short.Therefore, even when the load, particularly condensive load of the output circuit of signal is heavy, also can export the good signal waveform.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, by the 2nd grade the output D that obtains delay circuit in above-mentioned the 1st "AND" circuit ₂" non-" XD with the 1st grade output of above-mentioned delay circuit ₁Between " with " "AND" circuit and above-mentioned the 2nd "AND" circuit in obtain the output D of the N level of above-mentioned delay circuit _N" non-" XD _NOutput D with the N+1 level of above-mentioned delay circuit _N+1Between " with " the above-mentioned switch element of "AND" circuit control, its conduction impedance is configured to bigger than other switch elements.

According to said structure of the present invention, because on forward position that produces pulse and edge, back, when above-mentioned switch element conducting, its conduction impedance is compared with other and is set greatly, thereby may command speed that output load electric capacity is discharged and recharged.Therefore, can adjust the distortion of output pulse, obtain good impulse waveform.

And the pulse-generating circuit according to a mode of the present invention is characterized in that, omits the elementary of above-mentioned delay circuit, and connection inputs to the input signal of above-mentioned delay circuit and replaces primary output signal.

According to said structure of the present invention, owing to the elementary of delay circuit omits, thereby can reduce the circuit elements number of packages, have the advantage on the cost and reduce the effect that consumes energy, although quantity is few.And, because the present invention can be made of the logical circuit that utilizes the CMOS integrated circuit, thereby can constitute: do not increase operating power and simple and move, can be easy to generate available high-frequency wideband pulse in UWB communication with the maximum speed of cmos circuit.

On the other hand, electronic installation according to a mode of the present invention, it is characterized in that, being used for being combined into by combining mechanism portion about posture or position allowing relative displacement and be equipped with separately between a plurality of housings of electronic circuit, the radio section that wirelessly carries out signal transmitting and receiving is provided in the above-mentioned housing of each correspondence, and above-mentioned radio section is used any one pulse-generating circuit in the above-mentioned variety of way and constituted.

In this electronic equipment, because can be by the wireless transmitting-receiving of carrying out the information needed between two housings, thereby can realize the simplification of combining mechanism portion, and any one pulse-generating circuit of using in the above-mentioned variety of way owing to radio section constitutes, thereby can realize miniaturization, the reduction effect of power consumption is also big.

And the portable telephone according to a mode of the present invention is characterized in that, this portable telephone has: the 1st housing and the 2nd housing, and it is combined into about posture or position by combining mechanism portion allows relative displacement and electronic circuit is installed separately; And each radio section, it is separately positioned in above-mentioned the 1st housing and the 2nd housing, is used for wirelessly carrying out between above-mentioned the 1st housing and the 2nd housing signal transmitting and receiving; And corresponding above-mentioned radio section is used any one pulse-generating circuit in the above-mentioned variety of way and is constituted.

Although what this portable telephone was corresponding is so-called clam shell type and rotary-type portable telephone, yet because can be by the wireless transmitting-receiving of carrying out the information needed between two housings, thereby can realize the simplification of combining mechanism portion, and any one pulse-generating circuit of using in the above-mentioned variety of way owing to radio section constitutes, thereby can realize miniaturization, the reduction effect of power consumption is also big.

And the personal computer according to a mode of the present invention is characterized in that, this personal computer has: the 1st housing and the 2nd housing, and it is combined into about posture or position by combining mechanism portion allows relative displacement and electronic circuit is installed separately; And each radio section, it is separately positioned in above-mentioned the 1st housing and the 2nd housing, is used for wirelessly carrying out between above-mentioned the 1st housing and the 2nd housing signal transmitting and receiving; And corresponding above-mentioned radio section is used any one pulse-generating circuit in the above-mentioned variety of way and is constituted.

In this personal computer, because can be by the wireless transmitting-receiving of carrying out the information needed between two housings, thereby can realize the simplification of combining mechanism portion, and any one pulse-generating circuit of using in the above-mentioned variety of way owing to radio section constitutes, thereby can realize miniaturization, the reduction effect of power consumption is also big.

And, electronic installation according to a mode of the present invention, it is characterized in that, the regulation that this electronic installation has a plurality of circuit blocks that are used in being installed on same housing or a circuit substrate each other, by wireless at least one pair of radio section that carries out signal transmitting and receiving, and corresponding above-mentioned radio section is used any one pulse-generating circuit in the above-mentioned variety of way and is constituted.

In this electronic installation, owing to can utilize the mutual chien shih signal transmitting and receiving wireless penetration of the regulation of electromagnetic wave in a plurality of circuit blocks or circuit substrate, signal transmits at spatial transmission, thereby do not need to use the wiring of flexible substrate or connector etc., eliminated the cost height that causes because of these wirings or the doubt of reliability decrease.

And, information transferring method according to a mode of the present invention, this information transferring method is being combined into by combining mechanism portion about posture or position allowing relative displacement and be equipped with separately between a plurality of housings of electronic circuit, wirelessly carry out signal transmitting and receiving, it is characterized in that any one pulse-generating circuit of using in the above-mentioned variety of way carries out above-mentioned wireless signal transmitting-receiving.

In this information transferring method, because can be by the wireless transmitting-receiving of carrying out the information needed between two housings, thereby can realize the simplification of combining mechanism portion, and use the signal transmitting and receiving that any one pulse-generating circuit in the above-mentioned variety of way carries out radio section, thereby the reduction effect of power consumption is also big.

Description of drawings

Fig. 1 is the figure and the action timing diagram of the pulse-generating circuit of the 1st execution mode of the present invention.

Fig. 2 is the figure of the pulse-generating circuit of the 2nd execution mode of the present invention.

Fig. 3 is the figure of the pulse-generating circuit of the 3rd execution mode of the present invention.

Fig. 4 is the figure of the pulse-generating circuit of the 4th execution mode of the present invention.

Fig. 5 is the figure and the action timing diagram of the pulse-generating circuit of the 5th execution mode of the present invention.

Fig. 6 is the oscillogram of the pulse that will be produced by pulse-generating circuit of the present invention.

Fig. 7 is the circuit diagram of the pulse-generating circuit of the 6th execution mode of the present invention.

Fig. 8 is the sequential chart that the action to the pulse-generating circuit of the 6th execution mode of the present invention and the 2nd execution mode describes.

Fig. 9 is the circuit diagram of the pulse-generating circuit of the 7th execution mode of the present invention.

Figure 10 is sequential chart and the circuit diagram that the action to the pulse-generating circuit of the 8th execution mode of the present invention describes.

Figure 11 be expression use referring to figs. 1 through the illustrated pulse-generating circuit of Figure 10 electronic circuit is installed separately and by two housings of portion of mechanism combination between carry out the block diagram as the structure example of the electronic installation of embodiments of the present invention of signal transmitting and receiving by radio communication.

Figure 12 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of clam shell type portable telephone.

Figure 13 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of rotary portable telephone.

Figure 14 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of notebook personal computer.

Figure 15 is the figure of structure that the liquid crystal projection apparatus of one of embodiment as electronic installation of the present invention is shown.

Figure 16 is the key diagram that the pulse of using in UWB communication is described.

Figure 17 is the key diagram that another pulse of using in UWB communication is described.

Figure 18 is the figure and the action timing diagram of pulse-generating circuit in the past.

Embodiment

Below, with reference to accompanying drawing embodiments of the present invention are described.

(the 1st execution mode)

Fig. 1 (a) is the circuit diagram of wanting portion that the pulse-generating circuit of the 1st execution mode of the present invention is shown, and (b)～(d) is to be used for sequential chart that its action is described.Yet,, use impulse waveform shown in Fig. 6 (a) and use at time P as an example _DIn include the situation (P of four pulses _D=8P _W) be that exponential quantity is that 4 pulse describes.

Symbol 101～109th shown in Fig. 1 (a) has carried out the negative circuit that cascade connects.Each input and output terminal is endowed the terminal name as D0～D9.

When input terminal D0 as shown in the figure (b) when high level (H) changes to low level (L), each output is followed t to postpone and is propagated.

When D1 and D2, D3 and D4, D5 and D6, D7 and D8 both sides were H respectively, NAND (NAND) circuit 110～113 was exported L from terminal ND1～ND4 shown in figure (c).When having one to be L among ND1～ND4, nondisjunction (NOR) circuit (NOR circuit of negative logic) 114 is exported H shown in figure (d).By the above-mentioned target pulse waveform of obtaining.

In addition, in figure (d), output level does not have overshoot.Yet the signal strength signal intensity of using in UWB communication is subjected to legal restrictions, and for the level of the overshoot of common logical circuit, this intensity is too strong.In this case, must insert attenuator circuit separately, diminished pulse is towards signal level.Thus, the signal of overshoot is not convenient on the contrary.

And although there is not the output of the negative circuit 109 of the last level of use, yet this is exported by input, makes the fan-out (load) that connects with the negative circuit 101～108 of its prime consistent, thereby makes retardation at different levels constant.Equally, the negative circuit 101 of prime also can be used the inverter with other circuit identical characteristics, so that the signal that is input to NAND circuit 110 is as far as possible by the inverter drive of same characteristic.

As long as the signal that descends once at the time T p shown in Fig. 6 (a) is input to terminal D0, just can obtains the pulse train of the period T p shown in Fig. 6 (a).

Here, the pulsewidth of the pulse of NAND circuit 110～113 output only is that the input from negative circuit 102,104,106,108 rises to td time of delay that output descends, and comparing with in the past 3td has 3 times effect.

That is,, can be created in the short pulse that to obtain in the circuit in the past with high fdrequency component according to the pulse-generating circuit of the 1st execution mode.And, the simple circuit structure that this pulse-generating circuit gets up each combination of circuits of negative circuit, NAND circuit, NOR circuit owing to employing, thereby can use by the obtained semiconductor integrated circuit of easy CMOS technology and realize the UWB communication system.

(the 2nd execution mode)

Fig. 2 is the circuit diagram of wanting portion that the pulse-generating circuit of the 2nd execution mode of the present invention is shown.

202, the 203rd, the controllable negative circuit of retardation is equivalent to the negative circuit 101,102 of the formation delay circuit of the 1st execution mode.Same circuits arranged by required level use.In Fig. 2,3rd level will not be numbered later on.This negative circuit 202 constitutes by the combination of PMOS transistor M3 and nmos pass transistor M1.

PMOS, nmos pass transistor M4, M2 are connected with the source electrode of each transistor M3, M1, control the magnitude of current that flow into the negative circuit of using M3, M1, its retardation of may command by using this M4, M2.

The grid of transistor M2 is connected with control voltage terminal 211, and, the grid of transistor M4 by current mirror circuit 204 with control voltage terminal 211 and be connected, make controlling voltage that voltage terminal 211 applied and being connected from the voltage that VDD reversed.

In addition, this negative circuit structure also is identical in by the circuit shown in the each side of other symbol M 5～M8, M9～M12, M13～M16.

The negative circuit of above-mentioned formation connected by required progression constitute delay circuit.D0～Dn of Fig. 2 (n is required progression) is equivalent to D0～D9 of Fig. 1 etc., and the same (omitting among the figure), the generation target pulse of being connected with "AND" circuit respectively with the 1st execution mode.Terminal 201 is trigger terminal, is equivalent to the D0 of Fig. 1, produces target pulse according to the pulse that is input to this terminal 201.

For the retardation of control lag circuit, when the voltage that control voltage terminal 211 applied by following explanation decision, can realize accurate control, the pulse that can produce the high accuracy pulsewidth.

The 209th, the annular oscillation circuit that constitutes by negative circuit with electrical characteristic identical with negative circuit 202,203.This annular oscillation circuit 209 also can be controlled its retardation by the electric current that control flow into the inverter that constitutes this oscillating circuit, thereby can change frequency of oscillation.That is, this frequency of oscillation changes according to the voltage that terminal 212 is applied.

The output 213 of annular oscillation circuit 209 is carried out bit comparison mutually with the reference frequency that is applied by 206 pairs of reference frequency terminals 210 of phase-comparison circuit, and exports its phase difference.Charge pump 207 outputs to low pass filter 208 to electric charge according to the phase signal from phase-comparison circuit 206 outputs.The output of the DC component of low pass filter 208 is applied in the control voltage terminal 212 to annular oscillation circuit 209.Therefore, annular oscillation circuit 209, phase-comparison circuit 206, charge pump 207 and low pass filter 208 constitute phase-locked loop 205.

The frequency of oscillation that the voltage of control voltage terminal 211 is controlled so as to the output 213 that makes annular oscillation circuit 209 is always consistent with the reference frequency that reference frequency terminal 210 is applied.The retardation control of the negative circuit 202,203 by this voltage also being used to constitute delay circuit etc. can obtain the identical retardation of retardation with the negative circuit of annular oscillation circuit 209.The negative circuit of annular oscillation circuit 209 with as the negative circuit 202,203 of delay circuit owing to manufacture and make electrical characteristic identical, thereby its retardation unanimity.

In addition, in the 2nd execution mode, annular oscillation circuit 209 has been made diagram by the situation that 3 grades of delay circuits shown in symbol M 19～M32 constitute, yet as required, also can reduce frequency of oscillation, and make simple in structure by constituting more multistage oscillating circuit.And, usually, between the output of phase-comparison circuit 206 and annular oscillation circuit 209, insert frequency dividing circuit, so that be suitable for reference frequency value (not illustrating).

According to the pulse-generating circuit of the 2nd execution mode, can generate target pulse accurately.The pulsewidth of the pulse that this can not only free setting will export, and can also eliminate the various error essential factors that cause by the difference of the technology of the semiconductor integrated circuit of forming circuit etc., can improve fabrication yield, and, make easily, can also reduce manufacturing cost.

In the pulse-generating circuit of the 2nd execution mode, being all prerequisite mutually with the electrical characteristic of the negative circuit 202,203 of the negative circuit of annular oscillation circuit 209 and delay circuit is described, even yet the characteristic difference so long as similar, also can be eliminated the error essential factor of manufacturing variation etc.And, constructive method by change phase-locked loop 205, for example between the output of annular oscillation circuit 209 and phase-comparison circuit 206, insert the structure of frequency dividing circuit etc., can increase the degree of freedom of the design of the change of reference frequency or phase-locked loop 205, the scale of voltage generation circuit that can also reduce the retardation control usefulness of delay circuit alleviates its load.

Therefore, the pulse-generating circuit of the 2nd execution mode can use ball bearing made using to be easy to generate the high-accuracy pulse with wide and high frequency component to dash.And, can also eliminate the various error essential factors of the manufacturing variation etc. of semiconductor integrated circuit, also make easily.

(the 3rd execution mode)

Fig. 3 is the circuit diagram of wanting portion that the pulse-generating circuit of the 3rd execution mode of the present invention is shown.

311～314th, the buffer circuit that constitutes by current mode logic circuits.With buffer circuit 311 is that example describes its inside, and differential amplifier circuit constitutes M1, M2 by nmos pass transistor is differential.Nmos pass transistor M3 basis is come the restricting circuits electric current to the control voltage 310 that its grid applied, thus the control lag amount.PMOS transistor M4, M5 are the loads of outlet side, and apply voltage according to its grid and control output amplitude.Buffer circuit 311 drives input and output by the differential wave as the current mode logic circuits feature.

And terminal 301 is trigger terminal, is equivalent to the terminal D0 of the 1st execution mode, produces target pulse according to the pulse that is input to this terminal.In the present embodiment, be that the common logical signal rather than the situation of differential wave have been made illustration to triggering signal, owing to is connected with current mode logic circuits, thereby by negative circuit U1 generation differential wave D0.

Each buffer circuit 311～314 produces differential delay signal D1～Dn.In this circuit 311～314, D1 directly generates according to D0, and is different according to the condition that D1 generates with for example D2.That is, the D1 of buffer circuit 311 is driven and is generated by triggering signal that trigger terminal 301 is applied and negative circuit U1, and by contrast, D2 generates by the driving of D1.Under the worrying situation of this difference, as long as before D1, insert the buffer circuit of another grade identical characteristics.

D1～Dn is sent to logical circuit, generates target pulse.The 315th, obtain D1 and D2 " with " logical circuit, output " with " ND1.ND1 is the same with the 1st execution mode, and the output with other "AND" circuits is sent to OR circuit, generates target pulse (these circuit illustrate).

The retardation of the delay circuit of the output Dn of the buffer circuit 314 of the last level of delay circuit is compared by comparison circuit 307 and the reference pulse that is input to terminal 305.That is, the time before exporting Dn according to the triggering signal that is input to terminal 301 is compared by comparison circuit 307 with the pulsewidth that is input to the reference pulse of terminal 305, and this result is passed to control voltage generation circuit 308.In control voltage generation circuit 308, comparative result output control voltage 310 according to comparison circuit 307, be used to adjust the retardation of delay circuit, and this control voltage imposed on the grid of the electric current limit transistor (nmos pass transistor) of each buffer circuit 311～314 that constitutes delay circuit.

Simultaneously, owing to when the inflow current of each buffer circuit 311～314 changes, follow this variation, output amplitude also changes, thereby follow the variation of controlling voltage 310, the grid voltage 309 of the load transistor (PMOS transistor) of outlet side is changed, thereby output amplitude is controlled to be constant.For the pulse width control of the 3rd execution mode, although the initial pulse that produces has error, however after the 2nd time, owing to can proofread and correct control voltage according to result's last time, thereby can produce accurate pulse.In the application of UWB communication etc., the inaccuracy of this initial pulse does not also become problem very much.Can adopting as the present embodiment, the high pulse of simple structure generation precision is very effective.

And, but owing to use the CML of high speed motion, thereby can move to the frequency of the element function limit of forming circuit and with low power consuming with height.

Pulse-generating circuit according to the 3rd execution mode of above explanation can use ball bearing made using to produce the high pulse of high-frequency precision.Because the pulsewidth of the pulse that can not only free setting will export, and can also eliminate the various error essential factors that cause by the process variations of the semiconductor integrated circuit of forming circuit etc., thereby make easily, can also reduce manufacturing cost.

(the 4th execution mode)

Fig. 4 is the circuit diagram of wanting portion that the pulse-generating circuit of the 4th execution mode of the present invention is shown.

In above-mentioned the 2nd execution mode, have respectively delay circuit 202,203 ... with annular oscillation circuit 209, yet in the present embodiment, to coming shared example to be described by switching these circuit.With with the square frame of the identical numbering of Fig. 2 because identical with the 2nd execution mode, thereby omit explanation.

According to the signal that offers terminal 401 pulse-generating circuit is switched to correction mode and pulse generation pattern.Be provided under the situation of terminal 401 at the signal of specifying the formation pattern, switch 403 carries out switch motion, so that the input of delay circuit 202 is connected the annular oscillation circuit that constitutes regulation progression with the output of the regulation level of delay circuit, simultaneously, carry out switch motion, constitute phase-locked loop in the 2nd execution mode so that frequency dividing circuit 402 (not illustrating), phase-comparison circuit 206, charge pump 207 and low pass filter 208 activate.

If phase-locked loop is locked into the reference frequency that reference frequency terminal 210 is applied, then proofreaies and correct and finish.In addition, when correction mode, certainly, the logical circuit that makes pulse produce usefulness according to the signal that offers terminal 401 does not activate.

When the command signal of pulse generation pattern was imported into terminal 401, switch 403 carried out switch motion, so that the input of delay circuit 202 is switched to trigger terminal 201 sides, waited for that pulse produces signal.Meanwhile, the logical circuit that pulse produces usefulness is activated, and phase-locked loop is disengaged.Value when the output of low pass filter 208 keeps phase-locked loop locked.Delay circuit 202,203 ... proofread and correct phase-locked loop, and control voltage (voltage of the control terminal 211) driving when locked, thereby the dogging beam of its retardation when locked with phase-locked loop is identical with this phase-locked loop.Therefore, can produce the pulse of accurate pulsewidth.

(the 5th execution mode)

Fig. 5 (a) is the circuit diagram of wanting portion that the pulse-generating circuit of the 5th execution mode of the present invention is shown, and (b) is the sequential chart that its action is shown.

In the pulse-generating circuit of above-mentioned the 1st～the 4th execution mode, when triggering signal is applied in to trigger terminal, produce the pulse of the regulation exponential quantity that the progression according to delay circuit and "AND" circuit determines, stop then.When exponential quantity increases, follow this increase, the scale of required circuit also increases.Even present embodiment is the example that circuit scale does not also increase under the situation that produces the many pulses of exponential quantity.

In Fig. 5 (a), the 503rd, nondisjunction (NOR) circuit, and when signal Ci that trigger terminal 508 applied (L) time, is begun the action identical with inverter for " vacation ".Suppose that now Ci is L, shown in Fig. 5 (b), output NR1 postpones the td and become H time of delay of NOR 503.Inverter 501,502 sends the signal of the time of delay that has postponed each inverter according to the variation of the output NR1 of this output NOR 503, and with NOR 503 looping oscillating circuit starting oscillations.

N1, the N2 of Fig. 5 (b) represents the output of inverter 501,502 respectively.For simplicity, equate to describe the time of delay of back supposition inverter 501,502 and NOR 503, and the cycle of oscillation of annular oscillation circuit, N1, N2, the NR1 from figure was 6td as can be known.

When the both sides of NR1 and N1, N1 and N2, N2 and NR1 are H respectively, NAND (NAND) circuit 504,505,506 output L.In Fig. 5 (b), ND1, ND2, ND3 represent the output signal of NAND circuit 504,505,506 respectively.

The 507th, nondisjunction (NOR) circuit is as long as in the NAND circuit 504,505,506 has L, just from lead-out terminal 509 output H.In Fig. 5 (b), NR2 represents the output of NOR circuit 507.

From as can be known, export NR2 continues generation cycle 2td during Ci is L pulse with figure.As can be known, the width of the pulse of this generation is 1/3 a burst pulse in the past.

And, continue to produce pulse during (exponential quantity of pulse) can control according to Ci, can use the burst pulse that in circuit in the past, can not produce to produce the many pulse trains of exponential quantity, and not increase the number of elements of circuit.

In the 5th execution mode, be described with the example of using 3 grades of annular oscillation circuits, however the progression beyond the progression of annular oscillation circuit desirable 3.In this case, being necessary increases the NAND circuit quantity according to progression, and the input quantity of NOR circuit is equated with the NAND circuit quantity.In this case, although the number of elements of circuit increases, yet owing to the frequency of oscillation of annular oscillation circuit descends according to progression, thereby the current sinking of circuit changes hardly.

And, in the pulse-generating circuit of the 5th execution mode, as the 2nd～the 4th execution mode, also can compare annular oscillation circuit and the phase-locked loop that comprises oscillating circuit with identical characteristics, improve the precision of this cycle of oscillation, perhaps use current mode logic circuits to produce the pulse train in narrower cycle.

Below, before the later embodiments of the present invention of the 6th execution mode are described, the pulse shape that produces in the present invention and use is described.

Fig. 6 illustrates the pulse shape that will use the present invention to produce.With figure (a) is that (=1/f) sinusoidal wave carrier wave multiply by the resulting waveform of impulse waveform shown in Figure 16 (a) cycle 2Pw.

Equally, be that (=1/f) square-wave carrier multiply by the resulting waveform of impulse waveform shown in Figure 16 (a) cycle 2Pw with figure (b).Waveform with figure (b) uses the binary digit circuit to realize it being easy, and with figure (a) thus waveform since unwanted side wave few be easily.Yet waveform (b) promptly enables to use digital circuit easily to produce, because the frequency height, thereby as shown in the figure, also be difficult to generate the waveform of corner angle, obtain approaching the waveform of waveform shown in the figure (a) together naturally.

In this manual, describe as the situation of an example, yet the present invention is not limited only to this situation the waveform that produces following parameter.

Pulse spacing: Tp=5nsec

Carrier frequency: f=8GHz

Carrier wave pulsewidth: Pw=62.6psec

Pulsewidth: P _D=500psec

The umber of pulse that is comprised among the time P: 4 (P _D=8Pw)

Below, describe with reference to the pulse-generating circuit of accompanying drawing embodiments of the present invention.

(the 6th execution mode)

Fig. 7 (a) is the circuit diagram of wanting portion that the pulse-generating circuit of the 1st execution mode of the present invention is shown, and (b) is the figure that describes in detail as the inside of an embodiment of the delay circuit of its inscape, and Fig. 8 is used for sequential chart that action is described.

In Fig. 7 (a), 701～709th, 9 grades of inverters are carried out cascade connect and the delay circuit of formation.The structure of inverter inside at different levels describes shown in Fig. 7 (b) in the back.Be input to the pulsed D of terminal 731 ₀Shown in Fig. 8 (a)～(j), through each grade td time of delay and in, in delay circuit, propagate and from outputs at different levels by logic inversion.That is, suppose that the signal that input terminal 731 is applied is a positive logic, then in the i level, k is set at integer, when i=2k-1, output XD _2k-1, when i=2k, output D _2kIn addition, X represents signal " non-" and places before the signal name.

The 1st grade output XD when delay circuit ₁Output D with the 2nd grade ₂When being respectively high, N- channel MOS transistor 713 and 712 conductings make pulse output end 730 be connected with the 1st potential level V1.Then, as the 2nd grade output D of delay circuit ₂Output XD with 3rd level ₃Be respectively low (that is D, ₂NOT sum D ₃Both sides be high (" with " be " very ")) time, P channel MOS transistor 210 and 211 conductings make pulse output end 230 be connected with the 2nd potential level V2.

Equally, as the output XD of the 2k-1 level of delay circuit _2k-1Output D with the 2k level _2kWhen being respectively high, i.e. XD _2k-1And D _2k" with " when being " very ", N-channel MOS transistor 716,717,720,721,724 and 725 conductings make pulse output end 230 be connected with the 1st potential level V1.

Then, as the output D of the 2k level of delay circuit _2kOutput XD with the 2k+1 level _2k+1Be respectively when hanging down, i.e. D _2k" non-" XD _2kWith as XD _2k+1The D of " non-" _2k+1Between " with " when being " very ", P channel MOS transistor 714,715,718,719,722 and 723 conductings make pulse output end 730 be connected with the 2nd potential level V2.

By above action, can generate the impulse waveform shown in Fig. 8 (k).

Here, the 1st and the 2nd potential level can use the minus side of integrated circuit of forming circuit and power supply potential VSS, the VDD of positive side respectively, yet can set other any current potentials for.

P channel MOS transistor 727 and N-channel MOS transistor 728 are MOS resistance, and when cutting apart the 1st, the 2nd current potential V1, V2, when the switching circuit of MOS transistor 710～725 is not connected with any one party of above-mentioned the 1st, the 2nd current potential V1, V2, set the current potential of lead-out terminal 730.Usually, keep the constant symmetry of N, p channel transistor, be designed so that this current potential is the median of V1, V2.

Fig. 7 (b) is the figure that the inside of the inverter 701～709 that constitutes delay circuit is shown.P channel MOS transistor 741 and N-channel MOS transistor 742 constitutes negative circuits, and the signal that is input to terminal 744 is followed the time of delay of td and from terminal 745 counter-rotating outputs.

P channel MOS transistor 240 and N-channel MOS transistor 243 are connected respectively and are inserted into the transistorized source electrode that constitutes above-mentioned inverter, and are connected with minus side power supply VSS terminal 749 with positive side power vd D terminal 746 respectively.By controlling these transistorized grid potentials, may command flows into the source current of inverter.

By the responsiveness of this control may command inverter, may command td.In order to produce pulse, as long as the voltage control of terminal 747,748 is become to make Pw=td with target spectrum.When measuring the voltage that these terminals are applied from the VSS side and being assumed to Vpc, Vnc respectively, usually, when setting VDD-Vpc=Vnc for, can obtain the good output signal of symmetry.

And which side of transistor 740,743 can both omit.Because the lag characteristic of illustrative delay circuit is affected because of load here, thereby the output of switching circuit also can be connected via suitable buffer circuit.

By adopting said structure, most of circuit can be designed to the digital binary circuit, and are simple in structure.And because the circuit complimentary action, and when circuit is static, which side of P or N channel transistor all must be in nonconducting state, thereby becomes low-down consumed power by the power of circuitry consumes.

And, owing to output circuit is directly driven by MOS transistor 710～725, thereby distortion reduction, and can take out the powerful signal of large amplitude.

In addition, according to the axiom of Boolean algebra, according to the define method of logical value (the supposition electronegative potential is logical truth or vacation) etc., make " with " and " or " exchange, yet not need to prove that these principles are identical concepts.

(the 7th execution mode)

Fig. 9 (a) illustrates the 7th execution mode of the present invention.

In Fig. 9 (a), 901～909th, 9 grades of inverters are carried out cascade connect and the delay circuit of formation.The structure of inverter inside at different levels is with identical shown in Fig. 7 (b), and output at different levels is also identical with the 1st execution mode.

That is, be input to the pulsed D of terminal 931 ₀Shown in Fig. 8 (a)～(j), through each grade td time of delay and in, in delay circuit, propagate and from outputs at different levels by logic inversion.That is, suppose that the signal that input terminal 431 is applied is a positive logic, then in the i level, k is set at integer, when i=2k-1, output XD _2k-1, when i=2k, output D _2kIn addition, X represents negative logic and places before the signal name.

The 1st grade output XD when delay circuit ₁Output D with the 2nd grade ₂When low, N-channel MOS transistor 911 makes pulse output end 930 be connected with the 1st potential level V1 by 913 conductings of NOR circuit.Then, as the 2nd grade output D of delay circuit ₂Output XD with 3rd level ₃When high, the action conducting of P channel MOS transistor 910 by NAND circuit 912 makes pulse output end 930 be connected with the 2nd potential level V2.

Equally, as the output XD of the 2k-1 level of delay circuit _2k-1Output D with the 2k level _2kBe respectively when hanging down, i.e. XD _2k-1And D _2kNAND when being " very ", N-channel MOS transistor 915,919 and 923 conductings make pulse output end 930 be connected with the 1st potential level V1.

Then, as the output D of the 2k level of delay circuit _2kOutput XD with the 2k+1 level _2k+1When being respectively high, i.e. D _2kAnd XD _2k+1" with " when being " very ", P channel MOS transistor 914,918 and 922 conductings make pulse output end 430 be connected with the 2nd potential level V2.

By above action, can generate the impulse waveform shown in Fig. 8 (1).

In the 6th execution mode, to terminal D ₀Output pulse when the signal that applies descends, yet in the 7th execution mode, output pulse when rising.These are to observe D according to negative logic or positive logic ₀～D ₉Difference, as long as according to the axiom of Boolean algebra, equivalence.

According to above structure, to compare with the 1st execution mode, the transistor 910,911,914,915,918,919,922,923 that constitutes switching circuit makes the 1st, the 2nd potential level directly be connected with pulse output end 930.By contrast, in the 6th execution mode, for example, transistor 711 is connected with above-mentioned the 2nd potential level by transistor 710, in the time will reducing output impedance, becomes problem.In this embodiment, because transistor AND gate V1, V2 directly connect, thereby the design will reduce the output impedance of signal the time becomes easy.

And, in the 6th execution mode, for example, transistor 711 and 712 or 710 and 717 and same signal D ₂Or XD ₃Connect.As signal D ₂When high level changes to low level, because D ₂Current potential is in the middle of power supply, and transistor 710 and 713 conducting, thereby to make V1 and V2 short circuit, super-high-current be that so-called short circuit current is needle pattern and flows.

Equally, as signal XD ₃During variation, promptly when low level changes to high level, because XD ₃Current potential is in the middle of power supply, and transistor 211 and 216 conducting, thereby the current sinking that makes V1 and V2 short circuit, result make super-high-current be the mobile circuit of needle pattern increases.

In the 7th execution mode, because the grid of P, N channel transistor is not to drive according to same signal, thereby controlled the making of these grids be not to be in simultaneously conducting state, can alleviate the influence of short circuit current.Therefore, as long as make the output fall delay of NAND circuit 912,916,920,924, and make rising in advance, and make the output rising delay of NOR circuit 913,917,921,925, and decline is got final product in advance.

The NAND circuit constitutes: shown in Fig. 9 (b), the power vd D of p channel transistor 941,942 and positive side is connected in parallel, and the VSS of N channel transistor 943,944 and minus side is connected in series.And the NOR circuit constitutes: shown in Fig. 9 (c), N channel transistor 948,947 and power supply VSS are connected in parallel, and p channel transistor 945,946 and power vd D are connected in series.

When transistor series connects, owing to impedance is increased, thereby in the NAND circuit, have fall delay and the tendency in advance that rises, otherwise in the NOR circuit, having descends shifts to an earlier date and the tendency of rising delay.Therefore, adopt the connection of this execution mode, can alleviate short circuit current.As long as design the parallel transistor of NAND circuit or NOR circuit greatly, and design serial transistor for a short time, above-mentioned character is just further emphasized that effect also strengthens.

(the 8th execution mode)

Figure 10 (a) is shown schematically in obtained impulse waveform in above-mentioned the 1st, the 2nd execution mode.Under no load condition, should export 1001 such waveforms, yet waveform when being the light hours, becomes 1002 such waveforms because of the output load rust, when load is very heavy, become 1003 such waveforms.Particularly, suppose the pulse train that in 0.18 μ CMOS technology, will export about 8GHz, then can not obtain 1001 or 1002 waveform, and obtain 1003 waveform.

The 1003rd, the shape after quadraturing according to load capacity output waveform 1001 when zero load.Because the positive lateral area of waveform 1001 and minus side area equate, thereby this integrated waveform as shown is the waveform of deflection minus side.This waveform is not a target waveform, expectation be bipolarity waveform shown in Figure 6.

In the 8th execution mode, drive heavy load like this even show, circuit that also can undistorted ground export target waveform.In order to reach this purpose, shown in figure (b),, the waveform behind the integration is got final product in positive and negative two sides equalization as long as set the pulse on the forward position of output waveform and edge, back narrowly.

Followingly its operating principle is described in detail according to Figure 10 (b).In with figure (b), in order to compare, also to describe with the waveform shown in the figure (a), the waveform of identical numbering is identical with above-mentioned explanation on the notes.The explanation of these waveforms is owing to repetition is omitted.The 1006th, above-mentioned explanation in the front and back of output waveform along with the waveform after its reduced width.Under the situation that has driven heavy condensive load, this waveform is quadratured, and obtains as 1008 at the impartial waveform of positive and negative two sides.This waveform becomes the target output pulse waveform.

As waveform 1006 with the waveform of front and back after dwindle can by the retardation of the 2nd grade of the delay circuit of the 1st, 2 execution modes and last grade is set less the realization.

Being easily, is one with last level 709 or 909 transistors that are connected or the grid of delay circuit, and other outputs of fan-out duty ratio gently.Therefore, reduce the retardation of last level easily.

Equally, elementary inverter 701 or 901 fan-out load also are 1, and load is light, yet for pulsewidth is narrowed down, must reduce the retardation of inverter 702 or 902.Here, inverter 701,901 only is a buffer, and it doesn't matter with the waveform of being exported for the retardation of this grade.In order to reduce retardation, increase by the transistor 740 and 743 of comparing the rp unit that makes the delay circuit of Figure 10 (c) shown in once more with other levels, but simple realization.

And, shown in Figure 10 (b), make the forward position pulse narrowing of output waveform set the other method of impulse waveform and can be in Fig. 7 or Fig. 9 the signal delay component series connection be inserted in the node 732,932 and realize.This be because, the XD of (b) in Fig. 8 ₁The action of signal by above-mentioned delay element, follow delay, promptly the form that departs from a little to the right with the signal of (b) in the sequential chart with figure is sent in above-mentioned the 1st "AND" circuit.

And, use Figure 10 (d), describe preventing the other method that output pulse waveform is partial to positive and negative any one party as mentioned above because of condensive load.That is, in figure, as long as compare slack-off with other along the speed that 1001 pairs of load capacities of output pulse are discharged and recharged in the front and back of output pulse.That is,, and compare with waveform 1003 along 1005 in the back and to reduce the charging tendency and get final product as long as 1004 compare with the waveform 1003 under the situation that does not adopt any countermeasure and to reduce the discharge tendency ahead of the curve.Therefore, as long as these in front and back the switching transistor along conducting, 911,922 of 712,713,722,723 or Fig. 9 (a) of Fig. 7 (a) sets the increase of comparing with the conduction impedance of other switching transistors for, promptly reduces these transistorized sizes (channel width) and gets final product.

And as mentioned above, the elementary inverter 701,901 of the delay circuit of the 1st, 2 execution modes only plays the effect of buffer.Therefore, this part can be omitted.In this case, the input signal D of delay circuit ₀Be connected with the 1st "AND" circuit, and replace the elementary output XD of delay circuit ₁

The pulse that produces in pulse-generating circuit according to the above description only had for 3.5 cycles, and is slightly different with target pulse (pulse train by 4 cycles constitutes) shown in Figure 6.Append the remaining half period easily.That is, can append with delay circuit and realize with the switching transistor that first potential level is connected.In Fig. 7, in the back of delay circuit 709 delay circuit is set also, generate delay output D ₁₀Two N channel switch transistor are inserted in series connection between terminal 730 and 729, and make each transistorized grid and XD ₉, D ₁₀Connect.Perhaps in Fig. 9, a delay circuit also is set, generates delay output D in the back of delay circuit 909 ₁₀The N channel switch transistor is inserted in series connection between terminal 930 and 929, passes through XD ₉, D ₁₀NOR drive this transistorized grid.

Like this, as 1010 or 1012 of Figure 10 (e), append the residue half period.Waveform 1010 as mentioned above, pulsewidth is compared with other and is reduced, and adjusts the discharge time from load capacity, obtains 1011 such target pulse waveforms.And waveform 1012 adopts said method, that is, the conducting resistance of switching transistor is increased, and adjusts the discharge time from load capacity, obtains 1013 such target pulse waveforms.The waveform of obtaining does not so have DC component.And, must be that zero requirement is adjusted automatically and cancelled because the uneven a little DC component that is produced of the output pulse that causes because of the difference of the retardation of the conducting resistance of switching transistor or delay circuit etc. amounts to according to the quantity of electric charge that under stable state load capacity is discharged and recharged.

The above according to the present invention, uses ball bearing made using, even heavy condensive load also can be easy to generate the few short pulse of distortion.

(the 9th execution mode)

More than Shuo Ming pulse-generating circuit is owing to be that minimal type, power consumption are few, and can obtain that to use be desirable pulse signal in UWB communication, thereby can be to not producing useless influence on every side, and to use in the communication of the short-range micropower that is not easy to be subjected to other obstruction etc. also be extremely likely.

For example, also be fit to be applied to comprise, be combined into the device that wirelessly carries out the portion of mechanism (combining mechanism portion) of signal transmitting and receiving between the plural housing of allowing relative displacement about posture or position as universal joint or hinge etc.

Figure 11 be expression use referring to figs. 1 through the illustrated pulse-generating circuit of Figure 10 electronic circuit is installed separately and by two housings of portion of mechanism combination between carry out the block diagram as the structure example of the electronic installation of embodiments of the present invention of signal transmitting and receiving by radio communication.

In Figure 11, two housings constitute the sending part piece 1112 as one side, and as the opposing party's acceptance division piece 1113, from sending part piece 1112 data are sent to acceptance division piece 1113.In sending part piece 1112, pass through transtation mission circuit 1102 from the circuit key element 1101 of generation or reservation transmission information, from transmitting antenna 1110 radiation electromagnetic waves.

In this embodiment, constitute circuit part in transtation mission circuit 1102, this circuit part is used to use referring to figs. 1 through the illustrated pulse-generating circuit of Figure 10 offering transmitting antenna 1110 with the corresponding transmitted power of modulating of transmission information.

Propagate by aerial radio propagation path 1108 from the electromagnetic wave that this transmitting antenna 1110 is radiated.

Be provided with circuit key element 1104 in acceptance division piece 1113, this circuit key element 1104 receives the transmission information of propagating by radio propagation path 1108 by reception antenna 1111 and acceptance division 1106.In addition, between sending part piece 1112 and acceptance division piece 1113, constitute: in sending part piece 1112, be provided with interface circuit 1103, in acceptance division piece 1113, be provided with interface circuit 1105, can carry out the transmitting-receiving of a part of signal or power by the thread path 1107 that has that makes 1103,1105 connections of two interface circuits.

Having thread path to transmit low speed signal by this is easy, can transmits the synchronizing signal of wireless communication part.Therefore, the cumbersome process or the circuit that do not need seizure synchronously or follow the tracks of in wireless communication part can make circuit reduction.And, can also send the encryption key that is used for enhanced safety, carrying out radio communication in the change key arbitrarily.

Be configured to be no more than the upper limit from the electromagnetic field of transmitting antenna 1110 radiation by legal provisions.The radiation level of being allowed as the wireless office that does not need to permit is the level more much lower than the regulation of EMI, yet because communication distance is a point blank, thereby, can guarantee the communication path of abundant quality by suitably setting link budget.

Because the bulk information that needs to transmit at a high speed as the data that comprise image is not to transmit by holding wire, but in the space, propagate by wireless, thereby there is no need to use holding wire, can eliminate in the mechanism in connector or hinge arrangement (combining mechanism portion), electric variety of issue on going up or making thereupon.

And in the past holding wire transmits, have following shortcoming: follow high speed discharging and recharging of stray capacitance increased, power consumption increases, and increases from the radiant power that do not need of signal line emission, to the interference countermeasure of the surrounding devices difficulty that becomes.And, in holding wire transmits, owing to stipulated logic level, thereby can not reduce power consumption in essence, in order to reduce unwanted radiation, the countermeasure that method has only shielding to strengthen etc.

By contrast, according to the structure of this execution mode, because as long as guarantee sufficient communication quality in the point blank in same system, thereby the radiant power from transmitting antenna 1110 is dropped to about this value, the increase of power consumption improves in itself, and it is easy that the EMI countermeasure becomes.And, follow the restriction of the increase, component configuration, configuration etc. of the power consumption of the terminal that the impedance matching of communication line uses to be disengaged.

In addition, in the structure example of Figure 11, for convenience's sake, be described, carry out two-way communication yet also can constitute at two interblocks certainly to specially data being sent to acceptance division piece 1113 from sending part piece 1112.

(the 10th execution mode)

Figure 12 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of clam shell type portable telephone.Figure 12 (a) is the stereogram of the state when the clam shell type portable telephone being shown opening, and Figure 12 (b) is the stereogram of the state when this clam shell type portable telephone being shown closing.

In Figure 12 (a) and Figure 12 (b), in the surface configuration of the 1st housing section 1201 action button 1204 is arranged, and be provided with microphone 1205 in the lower end of the 1st housing section 1201, radio communication is installed with antenna 1206 in the upper end of the 1st housing section 1201.And, be provided with demonstration body 1208 on the surface of the 2nd housing section 1202 (face that under open mode, occurs), and be provided with loud speaker 1209 in the upper end of the 2nd housing section 1202.

And, be provided with demonstration body 1211 and imaging apparatus 1212 at the back side (outside in off position) of the 2nd housing section 1202.In addition, as above-mentioned demonstration body 1208 and 1211, for example, can use display panels, organic EL panel or plasma display etc.And,, can use CCD or cmos sensor etc. as imaging apparatus 1212.

In the 1st housing section 1201 and the 2nd housing section 1202, be respectively arranged with the internal radio communication antenna 1207 and 1210 that between the 1st housing section 1201 and the 2nd housing section 1202, carries out internal radio communication.As shown in the figure, the 1st housing section 1201 is connected by the hinge 1203 as combining mechanism portion with the 2nd housing section 1202, by being that fulcrum makes 1202 rotations of the 2nd housing section with hinge 1203, can be folded in the 2nd housing section 1202 on the 1st housing section 1201.

As mentioned above,, can use the 2nd housing section 1202 protection action buttons 1204, when carrying portable phone, can prevent that action button 1204 is by misoperation by the 2nd housing section 1202 is closed on the 1st housing section 1201.And, by opening the 2nd housing section 1202 from the 1st housing section 1201, can be when observing demonstration body 1208, operating operation button 1204, perhaps can when using loud speaker 1209 and microphone 1205, converse, perhaps can in operating operation button 1204, make a video recording.

And, by using the clam shell type structure, can be showing that body 1208 is configured on whole of roughly one side of the 2nd housing section 1202, harmless portability as portable telephone, the size of body 1208 capable of enlarged displaying can improve visibility.

In said structure, in this portable telephone, be characterised in that, constitute: internal radio communication antenna 1207 is set in the 1st housing section 1201, and internal radio communication is set with antenna 1210 in the 2nd housing section 1202, thereby by having used these internal radio communications to carry out data transmission between the 1st housing section 1201 and the 2nd housing section 1202 with the internal radio communication of antenna 1207 and 1210.

That is, in the portable telephone of Figure 12, internal radio communication is corresponding with the transmitting antenna 1110 in the electronic installation of antenna 1207 and Figure 11, and the reception antenna 1111 in the electronic installation of internal radio communication usefulness antenna 1210 and Figure 11 is corresponding.

In the portable telephone of Figure 12, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 with antenna 1207 sides (the 1st housing section 1201 sides) with the sending part piece 1112 of sending part 1102 corresponding circuit parts at internal radio communication.

And, same, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 with antenna 1210 sides (the 2nd housing section 1202 sides) at the internal radio communication of the portable telephone of Figure 12 with the acceptance division piece 1113 of acceptance division 1106 corresponding circuit parts.

In addition, such as described for the device of Figure 11, the supposition of transmitter side and receiver side is for convenience's sake, device can be constituted to carry out the two-way communication this point, also is fit in Figure 12 certainly.

According to said structure, for example, can be via external wireless communication antenna 1206, by having used the internal radio communication of internal radio communication with antenna 1207 and 1210, the view data or the voice data that are taken in the 1st housing section 1201 are sent to the 2nd housing section 1202, image is presented on the demonstration body 1208, perhaps from loud speaker 1209 output sounds.

And, can be by having used the internal radio communication of internal radio communication with antenna 1207 and 1210, from the 2nd housing section 1202 camera data of being made a video recording by imaging apparatus 1212 is sent to the 1st housing section 1201, and pass out to the outside with antenna 1206 by external wireless communication.As mentioned above, there is no need wired data of carrying out between the 1st housing section 1201 and the 2nd housing section 1202 and transmit, also there is no need to make the flexible circuit board of multitube pin by hinge 1203.

Therefore, can not cause the structure complicated of hinge 1203, therefore, can avoid numerous and diverseization of installation procedure, can be when suppressing the cost rising, realize the small-sized slimming of portable phone and the raising of reliability, and can't harm portability, can realize the big pictureization and the multifunction of portable phone as portable telephone.

Like this, even effect is also big when device interior uses radio communication to be used for signal to transmit, and, can give interference and anti-interference good radio communication when when having used pulse communication based on pulse-generating circuit of the present invention to be used for intercommunication.Promptly, even as portable telephone, have separately in the electronic equipment as the telecommunication circuit of the original target of equipment, also can be to as the influence or the obstruction of the radio communication of its original target or be suppressed to minimum from influence or obstruction that the radio communication as the original target of equipment is subjected to.

(the 11st execution mode)

Figure 13 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of rotary portable telephone.In Figure 13, in the surface configuration of the 1st housing section 1321 action button 1324 is arranged, and be provided with microphone 1325 in the lower end of the 1st housing section 1321, be provided with external wireless communication in the upper end of the 1st housing section 1321 with antenna 1326.And, be provided with demonstration body 1328 on the surface of the 2nd housing section 1322, and be provided with loud speaker 1329 in the upper end of the 2nd housing section 1322.

And, in the 1st housing section 1321, be provided with internal radio communication antenna 1327, and in the 2nd housing section 1322, be provided with internal radio communication with antenna 1330, constitute between the 1st housing section 1321 and the 2nd housing section 1322 and carry out internal radio communication.

The 1st housing section 1321 is connected by the hinge 1323 as combining mechanism portion with the 2nd housing section 1322, by being that fulcrum horizontally rotates the 2nd housing section 1322 with hinge 1323, can the 2nd housing section 1322 overlay configuration on the 1st housing section 1321, perhaps can make the 2nd housing section 1322 depart from the 1st housing section 1321.

As mentioned above, by the 2nd housing section 1322 overlay configuration on the 1st housing section 1321, can use the 2nd housing section 1322 protection action buttons 1324, when carrying portable telephone, can prevent that action button 1324 is by misoperation.And, horizontally rotate by making the 2nd housing section 1322, and make the 2nd housing section 1322 depart from the 1st housing section 1321, can be when observe showing body 1328 operating operation button 1324, perhaps can when using loud speaker 1329 and microphone 1325, converse.

In the portable telephone of Figure 13, be characterised in that, constitute: internal radio communication antenna 1327 is set in the 1st housing section 1321, and internal radio communication is set with antenna 1330 in the 2nd housing section 1322, thereby by having used the internal radio communication of these internal radio communications with antenna 1327 and 1330, the data of carrying out between the 1st housing section 1321 and the 2nd housing section 1322 transmit.

That is, in the portable telephone of Figure 13, internal radio communication is corresponding with the transmitting antenna 1110 in the electronic installation of antenna 1327 and Figure 11, and the reception antenna 1111 in the electronic installation of internal radio communication usefulness antenna 1330 and Figure 11 is corresponding.

In the portable telephone of Figure 13, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 with antenna 1327 sides (the 1st housing section 1321 sides) with the sending part piece 1112 of sending part 1102 corresponding circuit parts at internal radio communication.

And, same, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 with antenna 1330 sides (the 2nd housing section 1322 sides) at the internal radio communication of the portable telephone of Figure 13 with the acceptance division piece 1113 of acceptance division 1106 corresponding circuit parts.

In addition, such as described for the device of Figure 11, the supposition of transmitter side and receiver side is for convenience's sake, device can be constituted to carry out the two-way communication this point, also is fit in Figure 13 certainly.

According to said structure, for example, can be via external wireless communication antenna 1326, by having used the internal radio communication of internal radio communication with antenna 1327 and 1330, the view data or the voice data that are taken in the 1st housing section 1321 are sent to the 2nd housing section 1322, image is presented on the demonstration body 1328, perhaps from loud speaker 1329 output sounds.

As mentioned above, the data that there is no need to carry out between the 1st housing section 1321 and the 2nd housing section 1322 transmit wiredly, also there is no need to make the flexible circuit board of multitube pin by hinge 1323, the structure complicated that can suppress hinge 1323, and can avoid numerous and diverseization of installation procedure, can when suppressing cost and rising, realize the small-sized slimming of portable phone and the raising of reliability, and can't harm portability, can realize the big pictureization and the multifunction of portable phone as portable telephone.

Personal digital assistant), notebook personal computer etc. in addition, above-mentioned wireless communication technology also can be applied to video camera, PDA (Personal DigitalAssistance:.

(the 12nd execution mode)

Figure 14 be expression with reference to the illustrated wireless communications application of Figure 11 in the figure of the example of notebook personal computer.In Figure 14, this routine notebook personal computer is divided into main part 1405 and display part 1409, by as the hinge 1407 of combining mechanism portion and integrated.In main part 1405, be provided with: be responsible for the main part substrate 1403 of allomeric function control, as the keyboard 1404 of input unit, and the liquid-crystal controller 1408 that generates video data by the electronic circuit control on the main body substrate 1403.

And, in display part 1409, be provided with liquid crystal display 1406 as display unit.And, in main part 1405 and display part 1409, be respectively arranged with the transmitting antenna 1412 and the reception antenna 1410 that are used for carrying out mutually radio communication.And main part 1405 and display part 1409 are connected by the circuit 1411 that is used for carrying out mutually wire communication or power supply and supplies with.Having thread path to transmit low speed signal by this is easy, can transmits the synchronizing signal of wireless communication part.Therefore, the cumbersome process or the circuit that do not need seizure synchronously or follow the tracks of in wireless communication part can make circuit reduction.And, can also send the encryption key that is used for enhanced safety, carrying out radio communication in the change key arbitrarily.

In this notebook personal computer, particularly, the video data that is produced by liquid-crystal controller 1408 converts electromagnetic wave (electric wave) to through transmitting antennas 1412 and at spatial transmission from sending part 1410.The electromagnetic wave signal that is sent from transmitting antenna 1412 is received by reception antenna 1410, is sent to liquid crystal driver 1401 by acceptance division 1402, and is presented on the liquid crystal display 1406.

In said structure, the transmitting antenna 1110 in the electronic installation of transmitting antenna 1412 and Figure 11 is corresponding, and the reception antenna 1111 in the electronic installation of reception antenna 1410 and Figure 11 is corresponding.

In the notebook personal computer of Figure 14, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 with the sending part piece 1112 of sending part 1102 corresponding circuit parts in transmitting antenna 1412 sides (notebook personal computer main part 1405 sides).

And, same, be provided with the circuit part suitable that comprise in the electronic installation with Figure 11 in reception antenna 1410 sides (display part 1409 sides) of the notebook personal computer of Figure 14 with the acceptance division piece 1113 of acceptance division 1106 corresponding circuit parts.

In addition, such as described for the device of Figure 11, the supposition of transmitter side and receiver side is for convenience's sake, device can be constituted to carry out the two-way communication this point, also is fit in Figure 13 certainly.

In above-mentioned notebook personal computer, because between main part 1405 and display part 1409, should be presented at as the information on the liquid crystal display 1406 of display unit by the radio communication transmission, thereby can reduce the quantity that to pass through the holding wire of hinge 1407, can suppress the complicated of structure, and can avoid numerous and diverseization of installation procedure, can when suppressing cost and rising, realize the raising of reliability.

More than, the execution mode as notebook personal computer is described, yet also can be applied to identical technological thought the so-called mobile computer littler, the PDA that has stated and other mobile information terminal apparatus certainly than notebook type.

(the 13rd execution mode)

In the illustrated execution mode of reference Figure 11 to Figure 14, adopted following structure: use the pulse-generating circuit illustrated and carry out signal transmitting and receiving by radio communication being equipped with separately between electronic circuit and two housings by the combination of portion of mechanism referring to figs. 1 through Figure 10.

Yet technological thought of the present invention is not limited to be undertaken by radio communication the mode of signal transmitting and receiving between housing divided into two parts like this.

Promptly, can be in the following ways: in same housing, have with the sending part piece 1112 corresponding transmissions of Figure 11 with circuit parts and with the corresponding reception of acceptance division piece circuit part, between two circuit parts of this transmission and reception usefulness, use and communicate referring to figs. 1 through the illustrated pulse-generating circuit of Figure 10.Below, this execution mode is carried out illustration, technological thought of the present invention is described further.

Figure 15 is the figure of structure of liquid crystal projection apparatus that one of the embodiment of electronic installation of the present invention is shown, and Figure 15 (a) is the figure that wants portion that liquid crystal projection apparatus is shown, and Figure 15 (b) is the figure of the details of a light valve in the liquid crystal projection apparatus of expression Figure 15 (a).

In Figure 15 (a), the major part of the housing 1510 of projecting apparatus is occupied by optical system.That is, the light (white light) that is sent from light source 1501 resolves into three primary colors by optical system 1502 (in the dotted line).Here, optical system 1502 mainly is made of half-reflecting mirror HM, optical light filter and lens LZ.Each light carries out light modulation by the light valve 1505, light valve 1506 and the light valve 1507 that adopt liquid crystal, is synthesized by the optical system 1503 that adopts prism to constitute afterwards, and carries out enlarging projection by optical system 1504.

The circuit that is used to control light valve 1505, light valve 1506 and light valve 1507 is installed in substrate 1508,1509.The display data signal of 1512 pairs of light valve control of modulator usefulness is modulated, and radiates from transmitting antenna 1511 as electromagnetic wave.

In Figure 15 (b), employing receives the display data signal that is sent from the transmitting antenna 1511 of Figure 15 (a) to the liquid crystal driver 1522 (being made of a plurality of semiconductor integrated circuit usually) of the semiconductor integrated circuit that the photochopper 1521 that utilize to see through liquid crystal drives by reception antenna 1523, and according to the signal driving photochopper 1521 that the signal that this received has been carried out demodulation.

On the other hand, in this routine projecting apparatus, constitute: can receive the power that is used to drive photochopper 1521 or liquid crystal driver 1522 by connector 1524.

Based on electromagnetic display data signal from transmitting antenna 1511 multiplexing transmissions, employing is carried out method for addressing etc. based on the method for sign indicating number expansion, the method for using different electromagnetic modulating frequencies or decision time slot, designated specific regular receiving circuit piece (module) is so that the signal that these are multiplexing separates and can receive separately.

By taking this addressing method, the electromagnetic wave signal that is sent from transmitting antenna 1511 correctly is sent to three appointment light valves the light valve.The address is specified and can be carried out at each light valve, and, shown in Figure 15 (b), also can carry out the address on a light valve and specify at the each side that a plurality of liquid crystal drivers are installed.

More than, from as understanding easily with reference to the execution mode of the illustrated liquid crystal projection apparatus of Figure 15 (a) and Figure 15 (b), the electronic installation of present embodiment can be to send with circuit part (in the device of Figure 15, display data signal to light valve control usefulness is modulated, and offer the modulator 1512 of transmitting antenna 1511 and transmitting antenna 1511 etc. as electromagnetic wave, corresponding with the sending part piece 1112 of Figure 11) and receive with circuit part (in the device of Figure 15, be reception antenna 1523 and the signal that is received by this reception antenna 1523 separated the circuit part that transfers to obtain the signal that is used to drive photochopper 1521, corresponding with the acceptance division piece of Figure 11) be housed in the same housing and the electronic installation that constitutes.This transmission has with circuit part: become the electromagnetic wave converter section of electromagnetic wave signal and the sending part of wireless transmission electromagnetic wave signal sending conversion of signals.This reception has with circuit part: receive the acceptance division of above-mentioned electromagnetic wave signal and the electromagnetic wave recovery section that the electromagnetic wave signal that is received is returned to above-mentioned transmission signal.

In detail, obviously, above-mentioned technology have a plurality of circuit blocks that are used in being installed on same housing or circuit substrate regulation each other by wireless at least one pair of radio section that carries out signal transmitting and receiving, and corresponding above-mentioned radio section is to use any one pulse-generating circuit in the above-mentioned variety of way and the electronic installation that constitutes.

In said structure, send and not can be used as circuit substrate or circuit block with circuit part and reception with circuit part and carry out modularization and constitute.

Then, in the electronic installation of said structure, can be by the wireless signal transmitting and receiving that carries out of electromagnetic wave, signal transmits at spatial transmission, thereby does not need to use the wiring of flexible substrate or connector etc., the cost height that having eliminated connects up causes or the doubt of reliability decrease.

And, can also avoid following the problem of increase of power consumption of the high speed of terminal that impedance matching uses or data transfer rate.And, there is not the restriction of distributing and component configuration, can improve the design or the ease of use of electronic installation.

And, because the point blank that signal is transmitted in the same housing carries out, as long as thereby the electromagnetic wave that uses in signal transmits can be guaranteed in the interior communication of this distance, owing to can make the electromagnetic intensity decreases of radiation to the limit, thereby the EMI characteristic improves in itself, and it is easy that countermeasure becomes.

Particularly, under the situation of the illustrated liquid crystal projection apparatus of reference Figure 15, in the past, in liquid crystal projection apparatus, the major part of housing volume is occupied by optical system, must avoid light path and connect up, perhaps avoid light path and come arrangement components, and, since from heat storage that light source sent in housing, thereby also need the hot countermeasure that connects up.Here, by implementing the present invention, use electromagnetic wave that signal is carried out the space and transmit, thereby this difficulty is in the past significantly alleviated.

If the present invention uses in the UWB communication that utilizes short pulse, then its effect is big especially.

Claims (24)

1. A pulse generating circuit, characterized in that a plurality of delay elements are connected in cascade to form a prescribed loop, and when a prescribed input pulse is provided to the beginning of the cascaded connection, a logic circuit is used to Signals found in predetermined plural portions of the node portions between the plurality of delay elements and the terminal portions of the cascade connection are effectively frequency multiplied to obtain output pulses having a higher frequency than the input pulses. 2. A pulse generating circuit, characterized in that, the pulse generating circuit has: a delay circuit connected in cascade according to a prescribed number of stages; a plurality of the first logic circuits, which are connected with the output of the delay circuit, generate a pulse having a time width corresponding to the delay amount per one stage of the delay circuit; and a second logic circuit for obtaining an OR of the outputs of the plurality of first logic circuits. 3. A pulse generating circuit, characterized in that the pulse generating circuit has: a delay circuit, which is formed by cascade-connecting a buffer circuit that can electrically control the amount of delay; a plurality of first logic circuits , which is connected to the output of the delay circuit, and generates a pulse with a time width corresponding to the delay amount of each stage of the delay circuit; a second logic circuit, which obtains the "OR" of the outputs of the plurality of first logic circuits; a comparison circuit that compares the delay amount of the delay circuit with a reference delay amount; and a circuit that controls the delay amount of the buffer circuit based on an output of the comparison circuit. 4. A pulse generating circuit, characterized in that the pulse generating circuit has: a delay circuit, which is formed by cascade-connecting the first buffer circuits that can electrically control the amount of delay; a plurality of first a logic circuit, which is connected to the output of the delay circuit, and generates a pulse with a time width corresponding to the delay amount of each stage of the delay circuit; a second logic circuit, which obtains the "OR" of the outputs of the plurality of first logic circuits; "; an oscillating circuit equipped with a second snubber circuit having electrical characteristics similar to those of the first snubber circuit described above; and a phase-locked loop comprising the oscillating circuit and performing the above-mentioned operation by comparing the output of the oscillating circuit with a reference frequency. The delay amount of the second buffer circuit is feedback-controlled so that the oscillation frequency of the oscillation circuit is phase-locked to the reference frequency; the pulse generating circuit controls the delay amount of the first buffer circuit to be the same as the feedback control of the above-mentioned phase-locked loop . 5. A pulse generating circuit, characterized in that the pulse generating circuit has: a delay circuit, which is formed by cascade-connecting a buffer circuit that can electrically control the delay amount according to a prescribed number of stages; a plurality of first logic circuits , which is connected to the output of the delay circuit, and generates a pulse with a time width corresponding to the delay amount of each stage of the delay circuit; a second logic circuit, which obtains the "OR" of the outputs of the plurality of first logic circuits; A switch unit, which connects the output of the buffer circuit of the predetermined stage of the above-mentioned delay circuit to the input of the delay circuit to form a ring oscillation circuit; a phase-locked loop, which includes the ring oscillation circuit; The signal at the time of frequency is kept as the unit of the control signal of the delay amount of the above-mentioned buffer circuit; The amount of delay is controlled to be equal to the amount of delay at the time of locking of the above-mentioned phase-locked loop. 6. A pulse generating circuit, characterized in that, the pulse generating circuit has: an oscillating circuit, which is formed by connecting a multistage delay circuit and a gate circuit in a ring; a plurality of first logic circuits, which oscillate according to the The output of each stage of the circuit generates a pulse having a time width corresponding to the delay amount of each stage; and a second logic circuit that takes an OR of the outputs of the plurality of first logic circuits. 7. The pulse generating circuit according to claim 2 or 6, wherein the delay circuit is configured such that a delay amount can be controlled, and the delay amount can be controlled to a predetermined value. 8. A pulse generation circuit, characterized in that the pulse generation circuit has: an oscillation circuit, which is formed by connecting a plurality of buffer circuits and gate circuits that can be electrically controlled to the delay amount in a ring; a plurality of first logic circuits A circuit for generating a pulse of a time width corresponding to the delay amount of each stage based on the output of each stage of the oscillation circuit; a second logic circuit for obtaining an OR of the outputs of the plurality of first logic circuits; a comparison circuit , which compares the delay amount of each stage with a reference delay amount; and a circuit for controlling the delay amount of the buffer circuit based on the output of the comparison circuit. 9. A pulse generating circuit, characterized in that the pulse generating circuit has: an oscillating circuit, which is formed by connecting a plurality of first buffer circuits and gate circuits that can electrically control the delay amount; 1. a logic circuit that generates a pulse having a time width corresponding to the delay amount of each stage based on the output of each stage of the oscillation circuit; a second logic circuit that obtains the OR of the outputs of the plurality of first logic circuits; an oscillating circuit equipped with a second snubber circuit having electrical characteristics similar to those of the above-mentioned first snubber circuit; and a phase-locked loop including the oscillating circuit, and controlling the above-mentioned second snubber circuit by comparing an output of the oscillating circuit with a reference frequency The delay of the buffer circuit is feedback-controlled to phase-lock the oscillation frequency of the oscillation circuit to the reference frequency; the pulse generating circuit controls the delay of the first buffer circuit to be the same as the feedback control of the phase-locked loop. 10. The pulse generating circuit according to any one of claims 3 to 5 or claims 7 to 9, wherein the above-mentioned controllable buffer circuit is composed of a CMOS inverter and convection flowing into the CMOS inverter A unit that controls the current in the device. 11. The pulse generating circuit according to any one of claims 3 to 5, wherein the above-mentioned controllable buffer circuit is a buffer circuit with a CMOS current mode logic circuit, and the inflow current control of the buffer circuit, Make the amount of delay variable. 12. The pulse generating circuit according to any one of claims 2 to 11, wherein the first and second logic circuits include CMOS current mode logic circuits. 13. A pulse generating circuit, characterized in that, the pulse generating circuit has: a delay circuit of N+1 stages connected in cascade; a first "AND" circuit, which obtains the output D _i of the i-th stage of the delay circuit and "AND" between the output of the i-1th stage of the above-mentioned delay circuit XD _i-1 ; the 2nd "AND" circuit, which obtains the "not" of the output D _i of the i-th stage of the above-mentioned delay circuit "AND" between "XD _i and the output D _i+1 of the i+1 stage of the above-mentioned delay circuit; Level connection, when the output of the above-mentioned second "AND" circuit is "true", it is connected to the second potential level, otherwise, it is connected to the third potential level, wherein, N is a positive integer, and i is 1≤i Even number of ≤N. 14. The pulse generator circuit according to claim 13, wherein the delay circuit can control the delay amount, and the delay amount is controlled to a predetermined value. 15. The pulse generating circuit according to claim 13 or 14, wherein the delay circuit is composed of N+1 stages of MOS inverters and a unit that controls the power supply current flowing into the above-mentioned MOS inverters , by controlling the power supply current, the delay amount of the delay circuit is controlled to a predetermined value. 16. The pulse generating circuit according to any one of claims 13 to 15, wherein said first or second AND circuit has means for controlling transition times of output signals so that they do not overlap. 17. The pulse generating circuit according to any one of claims 13 to 16, wherein the first AND circuit obtains the output D2 of the second stage of the delay circuit and the first output _D2 of the delay circuit. The "AND" circuit of "AND" between the "NO" of the output of the stage XD ₁ , and the "NO" XD _N of the output D _N of the Nth stage of the above-mentioned delay circuit in the above-mentioned second "AND" circuit and the above-mentioned The AND circuit of the AND between the outputs DN+1 of the N ₊ 1-th stage of the delay circuit has a unit that sets the time for its output to be true to be shorter than the others. 18. The pulse generating circuit according to any one of claims 13 to 17, wherein the output D2 of the second stage of the delay circuit and the first output _D2 of the delay circuit are obtained from the first "AND" circuit in the above-mentioned first "AND" circuit. The "AND" circuit of "AND" between the output of the first stage XD ₁ , and the "NO" XD _N sum of the output _DN of the Nth stage of the above-mentioned delay circuit in the above-mentioned second "AND" circuit The ON resistance of the switch unit controlled by the AND circuit between the outputs DN+1 of the N ₊ 1-th stage of the delay circuit is set to be larger than that of the other switch units. 19. The pulse generating circuit according to any one of claims 13 to 18, wherein a primary side of the delay circuit is omitted, and an input signal input to the delay circuit is connected instead of a primary output signal. 20. An electronic device, characterized in that a wireless unit for wirelessly transmitting and receiving signals is provided between a plurality of casings that are combined by a coupling mechanism to allow relative displacement with respect to posture or position and each of which is equipped with an electronic circuit. It is provided in each of the corresponding housings, and the wireless unit is constituted by applying the pulse generating circuit according to any one of claims 1 to 19. 21. A mobile phone, characterized in that the mobile phone has: a first housing and a second housing, which are combined by a coupling mechanism to allow relative displacement with respect to posture or position and each of which is equipped with an electronic circuit; Each wireless unit is respectively arranged in the first housing and the second housing, and is used for wirelessly transmitting and receiving signals between the first housing and the second housing; and the corresponding wireless unit applies the claims The pulse generator circuit described in any one of 1 to 19. 22. A personal computer, characterized in that the personal computer has: a first housing and a second housing, which are combined by a coupling mechanism to allow relative displacement with respect to posture or position and each equipped with an electronic circuit; parts, which are respectively arranged in the first casing and the second casing, and are used for wirelessly transmitting and receiving signals between the first casing and the second casing; moreover, the corresponding wireless part applies claims 1 to 19 in any one of the pulse generation circuit. 23. An electronic device, characterized in that the electronic device has at least one pair of wireless parts for transmitting and receiving signals wirelessly between a plurality of circuit blocks or circuit boards mounted in the same housing. , and the corresponding wireless unit is constituted by applying the pulse generating circuit described in any one of claims 1 to 19. 24. An information transmission method for transmitting and receiving signals wirelessly between a plurality of housings that are coupled by a coupling mechanism to allow relative displacement with respect to posture or position and each of which is equipped with an electronic circuit, characterized in that, The above-mentioned wireless signal transmission and reception is performed by applying the pulse generating circuit according to any one of claims 1 to 19.

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