CN1925725A - Method for manufacturing circuit substrate - Google Patents
Method for manufacturing circuit substrate Download PDFInfo
- Publication number
- CN1925725A CN1925725A CN 200610142224 CN200610142224A CN1925725A CN 1925725 A CN1925725 A CN 1925725A CN 200610142224 CN200610142224 CN 200610142224 CN 200610142224 A CN200610142224 A CN 200610142224A CN 1925725 A CN1925725 A CN 1925725A
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- CN
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- Prior art keywords
- sides
- conductive metal
- wiring
- metal layer
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 45
- 239000000758 substrate Substances 0.000 title claims description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 239000004020 conductor Substances 0.000 claims abstract description 30
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 19
- 238000007747 plating Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 50
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 238000003475 lamination Methods 0.000 claims description 17
- 238000003466 welding Methods 0.000 claims description 16
- 238000009713 electroplating Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000084 colloidal system Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 239000011120 plywood Substances 0.000 claims description 2
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Chemical class [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Images
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Provided is a method of manufacturing a circuit board with which double-sided conductive metal layers are surely conducted in a double-sided circuit board and further, a cross-sectional shape of circuit wiring is not made worse. In a method of manufacturing a circuit board including a conduction structure formed from a through-hole or a bottomed via-hole, a conductive material is given by forming a conduction hole on a double-sided metal-clad laminate including conductive metal layers on both sides of an insulating base, a plating resist film 9 is formed excepting for said conduction hole and a land thereof, the plating resist film is released and removed after conducting the conductive metal layers and forming a circuit wiring pattern by plating, and the circuit wiring pattern is formed by removing the exposed conductive metal layers and electrically separating the circuit wiring pattern. The step of forming a plating layer for conduction between the double-coated conductive layers and the step of forming a plating layer for circuit wiring formation are performed separately from each other.
Description
Technical field
The present invention relates to a kind of manufacture method of circuit substrate, particularly relate to a kind of manufacture method of carrying out the two sides circuit substrate of high-density circuit wiring formation by plating.
Background technology
In wiring forms, in the general engraving method, become platform shape, in densification, have boundary in order to make the wiring section shape.Therefore, the past uses based on being more suitable in the Wiring method of the plating of high-density circuit formation always.
Show the manufacture method of this two sides circuit substrate to Fig. 5 (7) from Fig. 4 (1).That is, at first, shown in Fig. 4 (1), prepare the two sides metal shell of tension lamination that on the two sides of insulating substrate 21, has conductive metal layer 22 in advance, then, shown in Fig. 4 (2), by running through through hole or having end through hole that above-mentioned two sides metal shell of tension lamination is formed via 23.
Then, shown in Fig. 4 (3), the two sides metal shell of tension lamination that is formed with via 23 is added conductive material 24, then, shown in Fig. 4 (4), continue the two sides conductive metal layer 22 that has added conductive material 24 is formed platedresist film 25.
After this, shown in Fig. 5 (5),, when utilizing electric plating method to obtain the mutual conducting of two sides conductive metal layer 22, obtain the coating 26 of formation wiring for two sides metal shell of tension lamination with platedresist film 25.
Then, shown in Fig. 5 (6), remove and peel off and remove platedresist film 25, the conductive metal layer is exposed.Then, shown in Fig. 5 (7), remove the two sides conductive metal layer 22 that exposes,, make two sides wiring substrate by electric isolating circuit wiring figure 26 (forming the wiring figure).
Patent documentation 1: Japanese kokai publication hei 11-186716 communique
Patent documentation 2: TOHKEMY 2003-158364 communique
On the one hand, to having the two sides metal shell of tension lamination of platedresist film,, utilize electric plating method to add conductive material in order to obtain the conducting of two sides conductive metal interlayer.At this moment owing to remaining on the metal level on two sides conductive material is arranged, so in high-density circuit, take place the conductive metal layer with based between the wiring of plating connect airtight intensity decreases or the two is peeled off.
In order to eliminate these shortcomings, have a kind ofly after having added conductive material, be used to remove the technology of the etch processes of the conductive material on the conductive metal of two sides.In this case, the possibility that the conductive material on the inwall of the via that existence mustn't be removed also can be removed, and then want necessary strict control etch quantity.
On the other hand, have a kind of the utilization to add the technology of composition for the conductive material of the carbon of routine, coming adding ingredient is the method for the conductive material of carbon.But, compare than the conductive material of the Direct Electroplating of using tin palladium colloid, in little the running through through hole or have under the situation of end through hole of diameter, the method exists reliability to hang down such shortcoming for the electroplating processes that is used to obtain two sides metal interlevel conducting.
And, as shown in Figure 6, remain in wiring figure 26 on the conductive metal of two sides and the via 23 between the two sides conductive metal layer 22 by configuration, under thickness of coating on the inwall of the mutual via 23 of two sides conductive metal layer 22 changes big situation, satisfy the inwall thickness of coating of via of two sides conductive metal interlayer and the specification of the conductor thickness that parts are installed necessary wiring simultaneously and just have difficulties.In the case, on the no zone of wiring, the resist peristome is set, avoids the method for concentrating of (common name is pseudo-electroplates) power line to be used.
But, the design freedom of this process technology limit component configuration, and, situation can not be adapted to according to the necessary designed openings portion of character of installing component.For fear of concentrating of power line, the current density that reduces when electroplating is well-known, but because current density descends, causes the prolongation of electroplating processes time thereby productivity to descend.
In addition, under the situation that coating is thin on the inwall of the via 23 that two sides conductive metal layer 22 is mutual, the reliability decrease of electrical property not only, and, because under the thin situation of the coating that thickness of coating on the inwall of via 23 is removed than the etching of the electricity isolation of using the wiring figure 26 of platedresist film after removing, worry to produce poor flow 27 shown in Figure 7, therefore strengthened following burden, that is, also must fully carry out the burden of the affirmation of thickness of coating on the inwall of each regional via 23.
On the other hand, in order to prevent to expose insulating substrate 21 in the etching work procedure in the processing of adding conductive material as shown in Figure 8, the thickness of conductive metal layer 22 is compared with etch quantity must be bigger.But, its result, the problem that will exist the section shape of wiring to worsen.
Summary of the invention
Put in view of the above problems and carry out the present invention, the objective of the invention is to, the conducting between a kind of two sides conductive metal layer that can guarantee the two sides circuit substrate is provided and does not make the manufacture method of the circuit substrate that the section shape of wiring worsens.
In order to solve above-mentioned problem, the invention provides a kind of manufacture method of circuit substrate, in the two sides metal shell of tension lamination that on the two sides of insulating substrate, has the conductive metal layer, form via, and interpolation conductive material, the platedresist film of formation except above-mentioned via and welding disk thereof, and utilize electro-plating method to carry out after the formation of the conducting of above-mentioned conductive metal interlayer and wiring figure, peel off and remove the platedresist film, by removing the above-mentioned conductive metal layer that exposes, and the electric isolating circuit wiring figure forms the wiring figure, this circuit substrate has based on running through through hole or the conducting structure of end through hole being arranged
The manufacture method of this circuit substrate is characterised in that to have following operation:
Above-mentioned plywood has been added after the conductive material,, formed the two sides conducting resist film except above-mentioned via and welding disk thereof having added the two sides conductive metal layer of above-mentioned conductive material;
Use above-mentioned two sides conducting resist film, and implement to electroplate the conducting that obtains above-mentioned conductive metal interlayer;
Peel off and remove above-mentioned two sides conducting resist film;
By etching, attenuate contains the above-mentioned conductive metal layer of above-mentioned via and welding disk thereof;
To above-mentioned conductive metal layer, form except wiring figure formation portion and via with and welding disk the wiring resist film;
Use wiring with after resist film and enforcement plating and the formation wiring figure, peel off and remove the foregoing circuit wiring and use resist film, expose above-mentioned conductive metal layer;
By removing above-mentioned conductive metal layer, and the electric isolating circuit wiring figure, the wiring figure formed.
According to the present invention; when when removing formation wiring figure, becoming the conductive material on the conductive metal layer of unwanted two sides; owing to the conducting between the conductive metal layer is protected by electrodeposited coating; so the poor flow between the conductive metal layer of two sides can not take place; and owing to do not need strict etch quantity management, so productivity is good.
In addition, since implement at twice to be used for two sides conductive metal interlayer conducting plating and be used for the plating that the wiring figure forms, with regard to the formation of wiring figure, just do not need to consider that parts install the thickness of the two sides conductive metal layer of requirement, the decline of the current density in the time of preventing to be used to guarantee the plating of thickness and the productive decline that causes thus.
And, the generation of the poor flow that owing to electroplate, except becoming the thickness of coating that satisfies the conducting reliability, can also eliminate after removing the platedresist film, cause because of the etching that is used for the buffer circuit wiring figure by twice execution.And, owing to can fully guarantee thickness of coating, just there is not the burden of confirming thickness of coating.
And, before utilizing electro-plating method to form the wiring figure, because attenuate two sides conductive metal layer, so also can prevent the deterioration of wiring section shape.
Description of drawings
Fig. 1 represents the process profile of an embodiment of the invention.
Fig. 2 is the process profile of hookup 1.
Fig. 3 is the process profile of hookup 2.
Fig. 4 represents the process profile of existing manufacture method.
Fig. 5 is the process profile of hookup 4.
Fig. 6 is the profile according to the circuit substrate of existing manufacture method.
Fig. 7 is the profile according to the circuit substrate of existing manufacture method.
Fig. 8 is the profile according to the circuit substrate of existing manufacture method.
Embodiment
Hereinafter, referring to figs. 1 through Fig. 3, embodiments of the present invention 1 are described.
[execution mode 1]
Fig. 1 is the schematic diagram of each operation in the expression embodiment of the present invention 1.
At first, shown in Fig. 1 (1), prepare following two sides metal shell of tension lamination in advance, this two sides metal shell of tension lamination is on the two sides of the insulating substrate 1 of polyimide film etc., the Copper Foil of thickness 4 μ m is provided with as conductive metal layer 2 form.Then, shown in Fig. 1 (2),, form as the via 3 that runs through through hole to this two sides metal shell of tension lamination irradiation UV-YAG laser.
Then, shown in Fig. 1 (3),, add conductive material 4 by leading that orthicon (Conductron) is handled and waiting to having formed the two sides metal shell of tension lamination of via 3.Then, shown in Fig. 1 (4), to having added the two sides conductive metal layer 2 of conductive material 4, the dry film-type resist (not shown) of lamination (laminate) photonasty carries out graph exposure and development treatment.Thus, the two sides conducting resist film 6 of formation except via 3 and welding disk 5 thereof.
Then, shown in Fig. 2 (5),,, form the coating 7 that two sides conductive metal layer 2 mutual conducting are used by the copper sulphate electroplating processes to having the two sides metal shell of tension lamination of two sides conducting with resist film 6.In the present invention, in adding conductive material, can use the conduction processing of the Direct Electroplating that has adopted tin palladium colloid.
Then, shown in Fig. 2 (6), peel off and remove two sides conducting resist film 6.Then, shown in Fig. 2 (7),, utilize the mixed liquor of sodium peroxydisulfate class, the two sides conductive metal layer 2 that contains via 3 and welding disk 5 thereof is implemented the etch processes of 3 μ m, until the thickness that is thinned to 1 μ m removing the two sides conducting with after the resist film 6.
At this, as removing the two sides conducting with the etching after the resist film, can remove the unwanted conductive material on the two sides conductive metal layer except via and welding disk thereof, and, after etching, preferably make the two sides conductive metal layer of insulating substrate become the thickness that 0.5 μ m is above, 2.5 μ m are following.In addition, the thickness of interior wall coating that is used for the via of the mutual conducting of two sides conductive metal layer is preferably removed the two sides conducting with more than 2 times of etch quantity after the resist film 6.
After this, shown in Fig. 2 (8), two sides conductive metal layer 2 to attenuate, laminated photosensitive dry film type resist (not shown), carry out graph exposure and development treatment, thus, the formation wiring of formation except wiring figure formation portion 8 and via 3 and welding disk 5 thereof resist film 9.
Then, shown in Fig. 3 (9), utilize the copper sulphate electro-plating method, form wiring figure 10.Then, shown in Fig. 3 (10), peel off and remove wiring, conductive metal layer 2 is exposed with resist layer 9.
At last, shown in Fig. 3 (11), remove the two sides conductive metal layer 2 that exposes by etching, and electric isolating circuit wiring figure 10, substrate formed with wiring figure.
Be described more specifically this content according to embodiment 1.
At first, the two sides that " エ ス パ ネ Star Network ス " (the thickness 25 μ m) that prepare Nippon Steel's chemistry (strain) system in advance are used as polyimide film has the two sides of Copper Foil and does not have adhesion type copper shell of tension lamination, enforcement etches partially processing, so that the thickness of two sides conductive metal layer becomes 4 μ m.
Then, utilize UV-YAG laser, form the through hole of aperture 50 μ m.Then, utilize and lead the orthicon processing, carry out the interpolation of conductive material.
Then,, and carry out graph exposure and development treatment, form the two sides conducting resist film except via and welding disk thereof by the dry film of the thick photonasty of lamination 20 μ m.After this, by the copper sulphate electroplating processes, obtain more than the thickness 8 μ m as two sides conductive metal interlayer conduction, the coating below the 12 μ m.
Then, utilize NaOH, peel off and remove two sides conducting coating resist film.Then, utilize sodium peroxydisulfate class mixed liquor, the two sides conductive metal layer that contains via and welding disk thereof is carried out the etch processes of 3 μ m, until the thickness that is thinned to 1 μ m.By this processing, remove conductive material.
Then,, and carry out graph exposure and development treatment by laminated photosensitive dry film type resist, form except wiring figure formation portion and via with and welding disk the wiring resist film.
After this, by the copper sulphate electro-plating method, obtain the wiring figure that conductor thickness 9 μ m are above, 10 μ m are following.Handle by this, the conducting that just can make two sides conductive metal layer with thickness of coating become more than the 15 μ m, below the 20 μ m.Then, utilize NaOH, peel off and remove the wiring resist film, the conductive metal layer is exposed.
At last, remove the two sides conductive metal layer that exposes by the etch processes of utilizing sodium peroxydisulfate class mixed liquor, and the electric isolating circuit wiring figure, thereby acquisition has the wiring substrate of high-density circuit wiring figure.
Claims (4)
1, a kind of manufacture method of circuit substrate,
In the two sides metal shell of tension lamination that on the two sides of insulating substrate, has the conductive metal layer, form via, and interpolation conductive material, the platedresist film of formation except above-mentioned via and welding disk thereof, and utilize electro-plating method to carry out after the formation of the conducting of above-mentioned conductive metal interlayer and wiring figure, peel off and remove the platedresist film, by removing the above-mentioned conductive metal layer that exposes, and the electric isolating circuit wiring figure forms the wiring figure, this circuit substrate has based on running through through hole or the conducting structure of end through hole being arranged
The manufacture method of this circuit substrate is characterised in that to have following operation:
Above-mentioned plywood has been added after the conductive material,, formed the two sides conducting resist film except above-mentioned via and welding disk thereof having added the two sides conductive metal layer of above-mentioned conductive material;
Use above-mentioned two sides conducting resist film, and implement to electroplate the conducting that obtains above-mentioned conductive metal interlayer;
Peel off and remove above-mentioned two sides conducting resist film;
By etching, attenuate contains the above-mentioned conductive metal layer of above-mentioned via and welding disk thereof;
To above-mentioned conductive metal layer, form except wiring figure formation portion and via with and welding disk the wiring resist film;
Use wiring with after resist film and enforcement plating and the formation wiring figure, peel off and remove the foregoing circuit wiring and use resist film, expose above-mentioned conductive metal layer;
By removing above-mentioned conductive metal layer, and the electric isolating circuit wiring figure, the wiring figure formed.
2, the manufacture method of circuit substrate according to claim 1 is characterized in that:
Remove the two sides conducting with the etching after the resist film, can remove the unwanted conductive material on the two sides conductive metal layer except via and welding disk thereof, and, after etching, make the two sides conductive metal layer of insulating substrate become the thickness that 0.5 μ m is above, 2.5 μ m are following.
3, the manufacture method of circuit substrate according to claim 1 is characterized in that:
To two sides metal shell of tension lamination, the thickness of the interior wall coating of the via that is used for two sides conductive metal interlayer conduction that forms by electro-plating method is more than 2 times of the etch quantity described in the claim 2.
4, the manufacture method of circuit substrate according to claim 1 is characterized in that:
By the two sides metal shell of tension lamination that is formed with via is added the conductive material layer that conductive material forms, be to use the Direct Electroplating layer of tin palladium colloid.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005-255048 | 2005-09-02 | ||
| JP2005255048 | 2005-09-02 | ||
| JP2005255048A JP4624217B2 (en) | 2005-09-02 | 2005-09-02 | Circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1925725A true CN1925725A (en) | 2007-03-07 |
| CN1925725B CN1925725B (en) | 2010-11-03 |
Family
ID=37818110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101422241A Expired - Fee Related CN1925725B (en) | 2005-09-02 | 2006-09-01 | Method for manufacturing circuit substrate |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4624217B2 (en) |
| CN (1) | CN1925725B (en) |
| TW (1) | TW200721929A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783332B (en) * | 2009-01-16 | 2012-01-25 | 日月光半导体制造股份有限公司 | Circuit board and preparation process thereof |
| CN102427670A (en) * | 2011-11-08 | 2012-04-25 | 汕头超声印制板（二厂）有限公司 | Method for thinning copper layer of printed circuit board |
| CN104105361A (en) * | 2014-05-07 | 2014-10-15 | 深圳市环基实业有限公司 | Method for selective plating of conductive hole of circuit board |
| CN108235598A (en) * | 2017-12-13 | 2018-06-29 | 深南电路股份有限公司 | A kind of special gold plated pads manufacturing method |
| CN111712065A (en) * | 2020-07-08 | 2020-09-25 | 高德（江苏）电子科技有限公司 | Machining process for avoiding fracture of copper in holes of rigid-flex board |
| CN113396241A (en) * | 2018-12-20 | 2021-09-14 | 昭和电工材料株式会社 | Wiring substrate and method for manufacturing same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100962371B1 (en) * | 2008-07-02 | 2010-06-10 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
| JPWO2022097481A1 (en) * | 2020-11-05 | 2022-05-12 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3250579B2 (en) * | 1993-01-14 | 2002-01-28 | 住友電気工業株式会社 | Distortion correction circuit |
| JP3142270B2 (en) * | 1998-04-01 | 2001-03-07 | 三井金属鉱業株式会社 | Manufacturing method of printed wiring board |
| CN1223247C (en) * | 1998-09-18 | 2005-10-12 | 范蒂科股份公司 | Method for producing etched circuit |
| JP2000282245A (en) * | 1999-03-30 | 2000-10-10 | Ebara Udylite Kk | CONDITIONER COMPOSITION AND METHOD FOR INCREASING AMOUNT OF Pd-Sn COLLOIDAL CATALYST TO BE ADSORBED USING THE SAME |
| CN1494120A (en) * | 2002-10-28 | 2004-05-05 | 华泰电子股份有限公司 | Metal electroplating method for integrated circuit packaging substrate |
| JP4133560B2 (en) * | 2003-05-07 | 2008-08-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Printed wiring board manufacturing method and printed wiring board |
-
2005
- 2005-09-02 JP JP2005255048A patent/JP4624217B2/en not_active Expired - Lifetime
-
2006
- 2006-08-24 TW TW095131176A patent/TW200721929A/en unknown
- 2006-09-01 CN CN2006101422241A patent/CN1925725B/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783332B (en) * | 2009-01-16 | 2012-01-25 | 日月光半导体制造股份有限公司 | Circuit board and preparation process thereof |
| CN102427670A (en) * | 2011-11-08 | 2012-04-25 | 汕头超声印制板（二厂）有限公司 | Method for thinning copper layer of printed circuit board |
| CN104105361A (en) * | 2014-05-07 | 2014-10-15 | 深圳市环基实业有限公司 | Method for selective plating of conductive hole of circuit board |
| CN104105361B (en) * | 2014-05-07 | 2018-08-31 | 深圳市环基实业有限公司 | A kind of method of circuit board selective electroplating conductive hole |
| CN108235598A (en) * | 2017-12-13 | 2018-06-29 | 深南电路股份有限公司 | A kind of special gold plated pads manufacturing method |
| CN108235598B (en) * | 2017-12-13 | 2019-10-18 | 深南电路股份有限公司 | A kind of special gold plated pads manufacturing method |
| CN113396241A (en) * | 2018-12-20 | 2021-09-14 | 昭和电工材料株式会社 | Wiring substrate and method for manufacturing same |
| CN111712065A (en) * | 2020-07-08 | 2020-09-25 | 高德（江苏）电子科技有限公司 | Machining process for avoiding fracture of copper in holes of rigid-flex board |
| CN111712065B (en) * | 2020-07-08 | 2022-08-12 | 高德(江苏)电子科技股份有限公司 | Machining process for avoiding fracture of copper in holes of rigid-flex board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1925725B (en) | 2010-11-03 |
| JP2007067341A (en) | 2007-03-15 |
| JP4624217B2 (en) | 2011-02-02 |
| TWI357291B (en) | 2012-01-21 |
| TW200721929A (en) | 2007-06-01 |
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