CN1921358B - receiver and testing method thereof - Google Patents

Abstract

A receiver includes a clock/data recovery circuit, a serial-to-parallel converter and a test module. The clock/data recovery circuit is used to receive multiple test signal groups input in series, and follow the transmission frequency of these test signal groups to obtain a clock signal. The serial-to-parallel converter is used to receive these test signal groups output from the clock/data recovery circuit, and convert these test signal groups from serial input to parallel output of multiple test bit groups. The test module is used to receive these test bit groups and the clock signal, and compare two adjacent test bit groups. By judging whether the two adjacent test bit groups are exactly the same, it is known whether the operating state of the receiver is normal.

Description

Receiver and its test method

technical field

The present invention relates to a method for testing a receiver and a signal, and in particular to a method for testing a serial data receiver and a signal.

Background technique

Please refer to FIG. 1A , which is a schematic diagram of a known loop test. A south bridge chip 100 with a SAT (Serial Advanced Technology Attachment) port includes a receiver 112 and a transmitter 114 . In the known technology, the test signal D1 is continuously output from the transmitter 114 to the receiver 112 to achieve the purpose of the loop test. During the transmission of the test signal D1 , the transmitter 114 only transmits the data part of the test signal D1 to the receiver 112 . Therefore, the clock/data recovery circuit (not shown) of the receiver 112 follows the frequency at which the transmitter 114 transmits the test signal D1 as its own operating frequency.

Please refer to FIG. 1B , which is an example of the transmission diagram of the test signal in FIG. 1A . In order to test the correctness of the test signal D1 transmitted from the transmitter 114 to the receiver 112 , it is known to design multiple buffers 10 inside the transmitter 114 . These buffers 10 are used to pre-record a plurality of samples (patterns) A1-An of the signal to be tested, and when the test signal D1 output by the transmitter 114 is transmitted to the receiver 112, the test signal D1 and the data stored in the buffer 10 are combined. The signal samples under test are compared to determine whether the receiver 112 successfully receives the test signal D1.

In the known loop test method, the buffer in the receiver is used to pre-store the samples of the signal to be tested, but adding an extra buffer in the transmitter will not only cause difficulties in circuit design, but also increase the overall circuit cost and power. These are the disadvantages of known loop testing methods. Therefore, how to effectively and correctly test the function of the receiver is an unresolved problem.

Contents of the invention

In view of this, the present invention provides a receiver for receiving a plurality of test signal groups, each of which has a plurality of bits of data, the receiver includes: a clock/data recovery circuit for receiving The plurality of test signal groups input in series, and follow the transmission frequency of the plurality of test signal groups to obtain a clock signal, wherein the clock signal is used as the operating frequency of the receiver; a series of parallel converters for receiving The multiple test signal groups output by the clock/data recovery circuit, and convert the multiple test signal groups input serially into multiple test bit groups output in parallel, wherein the multiple test bit groups respectively have multiple bit data; and a test module for receiving the plurality of test bit groups and the clock signal, and comparing two adjacent ones of the plurality of test bit groups to determine the two adjacent multiple Whether the two test bit groups are identical, wherein the two adjacent test bit groups include a current test bit group and a next test bit group, the test module includes: a first buffer for storing the current test bit group A test bit group; a second buffer for storing the next test bit group; a data checking unit for receiving the current test bit group and the next test bit group, and comparing the current test bit group with the next test bit group Whether the data of the plurality of bits corresponding to the next test bit group are exactly the same; and a counter for when any one of the plurality of bits corresponding to the current test bit group When the data are different, an error record value is added by one, wherein when the error record value exceeds a threshold, it indicates that the receiver is abnormal.

The present invention also proposes a signal testing method, which is applicable to a receiver capable of receiving multiple test signal groups, and the multiple test signal groups respectively have multiple bits of data. The signal testing method includes: the multiple test signal groups The group is converted into a plurality of test bit groups output in parallel, wherein the plurality of test bit groups respectively have data of a plurality of bits; and comparing two adjacent ones in the plurality of test bit groups to determine whether the two adjacent Whether the plurality of test bit groups are the same, wherein, the two adjacent test bit groups include a current test bit group and a next test bit group, the method also includes: separately registering the current test bit group and the next test bit group; compare whether the data of the plurality of bits corresponding to the current test bit group and the next test bit group are completely the same; and when the current test bit group corresponds to the next test bit group When the data of any one of the multiple bits is different, an error record value is added by one, and when the error record value exceeds a threshold value, it indicates that the receiver is abnormal.

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, and the details are as follows:

Description of drawings

FIG. 1A shows a schematic diagram of a conventional loop test.

FIG. 1B is a schematic diagram of transmission of the test signal in FIG. 1A .

Fig. 2 shows a block diagram of a receiver of a preferred embodiment of the present invention.

FIG. 3 shows a schematic diagram of the test module of FIG. 2 .

Fig. 4 shows a flow chart of a preferred embodiment of the present invention.

Description of main component symbols

200: Receiver

210: Clock/data recovery circuit

220: serial parallel converter

230: Test Module

232: First buffer

234: Second buffer

236: Data checking unit

238: Counter

240: Word alignment module

Detailed ways

Please refer to FIG. 2, which is a block diagram of a receiver in a preferred embodiment of the present invention. The receiver 200 can be arranged in a chipset, such as a south bridge chip, to continuously receive multiple test signal groups with the same data D1. Each test signal group D1, such as data with a length of 10 bits, is input to the receiver 200 in a serial manner by the external device 20. The receiver 200 and the external device 20 form a data testing system. The receiver 200 Including a clock/data recovery circuit 210, a serial-to-parallel converter 220 and a test module 230. The receiver 200 also includes a word alignment module 240. The clock/data recovery circuit 210 is used to continuously receive these serially input test signal groups D1, And follow the transmission frequency of these test signal groups D1 to obtain a clock signal Clk. Wherein, the clock signal Clk is used as the operating frequency of the receiver 200. The serial-to-parallel converter 220 receives these test signal groups D1 from the clock/data recovery circuit 210, and These test signal groups D1 are converted from serial input to parallel output of multiple test bit groups TS. Since the test signal group D1 has 10-bit data, in a preferred embodiment, each test bit group TS also has 10 The data of the bit. The test module 230 is used for receiving these test bit groups TS and the clock signal Clk, and compares the current test bit group TS (1) with the next test bit group TS (2), to determine the respective Whether the data of the corresponding bits are identical. If the corresponding 10-bit data between the test bit group TS(1) and the next test bit group TS(2) are exactly the same, it means that the operating state of the receiver 200 is normal.

Let's take a closer look at how the testing module 230 achieves the purpose of signal testing. Please refer to FIG. 3 , which is a block diagram of the test module 230 in a preferred embodiment of the present invention. The test module 230 includes a first buffer 232 , a second buffer 234 , a data checking unit 236 and a counter 238 . The first buffer 232 is used to store the current test bit set TS(1). The second buffer 234 is used to store the next test bit set TS(2). The data checking unit 236 is used to receive the current test bit set TS(1) and the next test bit set TS(2), and compare the data corresponding to each bit in the two test bit sets TS(1) and TS(2) Is it exactly the same. The counter 238 is used for adding one to an error record value when the data of any one of the corresponding bit data between the two test bit groups TS(1) and TS(2) is different. When the 10-bit data of the first test bit set TS(1) and the second test bit set TS(2) are exactly the same, it means that the receiver 200 is operating normally and can receive the test signal correctly. Next, the test module 230 outputs the compared first test bit group TS (1) to the word alignment module 240, the second test bit group TS (2) is moved to the first buffer 232, and the next third test bit group The set TS(3) is stored in the second buffer 234 . In this manner, the testing module 230 continues to compare the second test bit set TS(2) with the third test bit set TS(3). In a preferred embodiment, the third test bit set TS(3) is the next two test bit sets after the first test bit set TS(1).

When the data of any one of the 10 bits in the first test bit set TS(1) and the second test bit set TS(2) are different, the counter 238 adds 1 to an error record value. If the error record value of the counter 238 reaches a predetermined number of times, such as a threshold, it can be determined that the receiver 200 cannot operate correctly. In this case, various settings of the receiver 200 can be readjusted, for example, parameter settings of the receiver 200 can be adjusted, and then the receiver 200 can be re-tested to find a suitable parameter setting for the receiver 200 . The threshold of the error record value can be determined according to the actual operating conditions.

When the receiver 200 is in a normal operating state (that is, a non-testing state), the word alignment module 240 is used to compare the received bit groups with a look-up table (not shown) stored therein, so as to align the received The received bit groups are converted into corresponding word groups (word). When the receiver 200 is in the state of testing, the word alignment module 240 is used to receive the compared test bit group TS, so that the new test bit group TS can enter the first buffer 232 and the second buffer 234 for Make a new comparison.

Please refer to FIG. 4 , which is a preferred embodiment of the signal testing method of the present invention, and please refer to FIG. 2 and FIG. 3 together. First in step S1, the clock/data recovery circuit 210 continuously receives a plurality of serially input test signal groups D1, and generates a clock signal Clk according to the transmission frequency of these test signal groups D1 as the operating frequency of the receiver 200 . In step S2, the serial-to-parallel converter 220 converts the serially input test signal set D1 into a parallel output test bit set TS. The number of data bits of the test bit set TS may be the same as the data length of the test signal set D1.

Then in step S3, the first two test bit groups TS (1) and TS (2) are respectively registered in the first buffer 232 and the second buffer 234, and in step S4, the data checking module 236 compares the two A test bit group TS(1) and TS(2) whether each corresponding bit has the same data.

If the comparison result of the test bit groups TS(1) and TS(2) has any different bit data, the counter 238 will add one to the error record value, as shown in step S5. After the comparison is completed, then in step S6, a pair of test bits is reloaded into the first buffer 232 and the second buffer 234 for another comparison. The test bit group TS (1) of the first buffer 232 will be output to the word alignment module 240, the test bit group TS (2) is then moved to the first buffer 232, and the test bit group TS (3) is stored in the second Buffer 234 . Then go back to step S4, compare whether each bit group of test bit group TS(2) and TS(3) are the same, and so on until all test bit groups TS are compared.

If the comparison result of the test bit sets TS(1) and TS(2) has no different bit data, then directly enter step S6 after the comparison is completed to perform a new comparison. After all the test bit groups are compared, if the error record value of the counter 238 is still within a threshold range, it means that the receiver 200 works normally. If during the test, the error record value of the counter 238 exceeds the threshold, it means that the receiver 200 is abnormal, and the comparison step can be stopped, and the receiver 200 can be reset.

In the embodiment of the present invention, the test module is used to check whether the data of each corresponding bit in two adjacent test signal groups is completely the same, so as to know whether the receiver is normal. Compared with the method of adding multiple buffers in the receiver to record multiple sets of test signal samples in the known technology, the test method of the present invention only needs to perform simple bit group comparison to complete the test. The circuit design of the present invention is also much simpler than the known method, and the number of buffers to be used is also reduced, so the circuit cost can be effectively saved.

In addition, since the test signal set received by the receiver in the prior art must be compared with the test signal samples in the buffer, the transmitter can only output the test signal set, so the control process for the transmitter and receiver is relatively complicated in the prior art . However, the present invention only needs to continuously transmit the same test signal group to the receiver, so there is no need to perform a complicated control process on the external device and the receiver, and the generation of the test signal group is very easy, and the content of the test signal group that can be used More flexible and more diverse. In addition, the test method of the present invention has the advantage of being able to quickly measure other more accurate characteristic information of the receiver, such as whether the jitter of the receiver exists, the sensitivity of the receiver, and the like.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is as defined by the appended claims.

Claims (5)

1. A receiver, in order to receive a plurality of test signal groups, the plurality of test signal groups respectively have data of a plurality of bits, the receiver comprises: A clock/data recovery circuit, used to receive the multiple test signal groups input serially, and follow the transmission frequency of the multiple test signal groups to obtain a clock signal, wherein the clock signal is used as the operating frequency of the receiver ; A serial-to-parallel converter, used to receive the multiple test signal groups output by the clock/data recovery circuit, and convert the serially input test signal groups into parallel output multiple test bit groups, wherein the A plurality of test bit groups respectively have data of a plurality of bits; and A test module, used to receive the plurality of test bit groups and the clock signal, and compare two adjacent ones of the plurality of test bit groups to determine whether the two adjacent test bit groups are exactly the same, Wherein the two adjacent test bit groups include a current test bit group and the next test bit group, and the test module includes: a first buffer for storing the current test bit group; a second buffer for storing the next test bit group; A data checking unit, used to receive the current test bit group and the next test bit group, and compare whether the data of the plurality of bits corresponding to the current test bit group and the next test bit group are completely the same; and A counter is used for adding one to an error record value when the data of any one of the plurality of bits corresponding to the current test bit group and the next test bit group is different, When the error record value exceeds a threshold, it indicates that the receiver is abnormal. 2. The receiver as claimed in claim 1, wherein the plurality of test signal groups are serially input to the receiver by an external device and have the same data content. 3. A signal test method, suitable for a receiver that can receive a plurality of test signal groups, the plurality of test signal groups respectively have a plurality of bit data, the signal test method comprises: converting the plurality of test signal groups into a plurality of test bit groups output in parallel, wherein the plurality of test bit groups each have a plurality of bits of data; and comparing two adjacent ones of the multiple test bit groups to determine whether the two adjacent multiple test bit groups are the same, Wherein, the two adjacent test bit groups include a current test bit group and the next test bit group, and the method also includes: separately registering the current test bit group and the next test bit group; comparing whether the data of the plurality of bits corresponding to the current test bit set and the next test bit set are identical; and When the data of any one of the plurality of bits corresponding to the current test bit group and the next test bit group is different, an error record value is added by one, When the error record value exceeds a threshold, it indicates that the receiver is abnormal. 4. The signal testing method as claimed in claim 3, wherein after the comparison of the two adjacent test bit groups is completed, it also includes outputting the former of the two adjacent test bit groups to continue The latter of the two adjacent test bit groups is compared with a test bit group adjacent thereto. 5. The signal testing method as claimed in claim 3, wherein the plurality of test signal groups are serially input to the receiver by an external device and have the same data.

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