CN1920903B - Pixel layout structure applied to flexible display - Google Patents

Abstract

A pixel layout structure for a flexible display is suitable for being arranged on a flexible substrate and driven by means of a data line and a scan line. The pixel layout structure includes a plurality of thin film transistors, and the pixel layout structure connects the plurality of thin film transistors in a plurality of different layout modes, so that when the flexible substrate is aligned and offset during the manufacturing process or the panel is bent during use, the problem that the pixel cannot work normally due to having only a single transistor in the pixel can be effectively solved, thereby improving the reliability of the pixel on the flexible substrate.

Description

Pixel layout structure applied to flexible display

technical field

The present invention relates to a pixel layout structure, in particular to a pixel layout that is applied on a flexible substrate of a flexible display and effectively improves the reliability of pixels on a flexible substrate by using various layout methods structure.

Background technique

In recent years, flat-panel displays continue to develop toward thinner, lighter, and smaller. However, the convenience of carrying and the richness of information display at the current stage cannot achieve the best of both worlds. In order to take into account the convenience of carrying and the richness of information display, it is very important to develop flexible or rollable soft displays. However, during the manufacturing process of the flexible substrate of the flexible display, the alignment of the pattern often occurs due to thermal expansion; or when the panel of the flexible display is deflected during use, the component structure in the pixel is prone to breakage. Both of the above situations will cause defective pixels and the image cannot be displayed normally.

In the pixel layout of a traditional display, a pixel structure usually includes only one thin film transistor, and whether the pixel can display normally depends on whether the thin film transistor can work normally. Please refer to FIG. 1A, on a known active thin film transistor array substrate 100, each pixel structure is driven by a data line 110 and a scan line 120, and includes a thin film transistor 130, wherein the thin film transistor 130 is connected to two electrodes 132 , oxide 134, and silicon material 136 are composed from bottom to top. However, as shown in FIG. 1B and FIG. 1C , when the pattern position alignment of the pixel structure is shifted left and right due to thermal expansion during the manufacturing process, or the component structure in the pixel is deformed or broken due to the deflection of the panel during use, it will As a result, the thin film transistor 130 cannot work normally, so that the pixel cannot display normally. The solutions to the above-mentioned problems in the known technologies mostly focus on solving the problem of metal wire and capacitor breakage, but do not solve the problem of component breakage on the panel, nor disclose any solution from the perspective of pixel layout design. Pattern position alignment The means by which side-to-side shifting or distortion of the pixel structure occurs.

Contents of the invention

The technical problem to be solved by the present invention is to improve the reliability of the pixels on the flexible substrate by reducing the chance of defective pixels caused by poor alignment or substrate deflection during the manufacturing process by improving the layout in the pixels.

The secondary purpose of the present invention is to ensure that at least one thin film transistor in the pixel structure can still work normally when the manufacturing process alignment is poor or the substrate is deflected without increasing the complexity of the manufacturing process by using various layout methods in the pixel, so as to achieve Pixel normal display function.

In order to achieve the above purpose, the present invention proposes a pixel layout structure applied to a flexible display, which is suitable for being arranged on a flexible substrate and driven by a data line and a scanning line, wherein the pixel layout structure It includes a plurality of thin film transistors, and each thin film transistor includes a gate, a channel and a source/drain, wherein the pixel layout structure connects the plurality of thin film transistors in a layout.

In the above-mentioned pixel layout structure, in the layout method, two thin film transistors are arranged on both sides of the data line, and the channels of the two thin film transistors are respectively parallel to the data line.

In the pixel layout structure described above, in the layout method, two thin film transistors are arranged on one side of the data line, and the channels of the two thin film transistors are respectively parallel to the data line.

In the above pixel layout structure, in the layout method, at least three thin film transistors are disposed on one side of the data line, and the channels of the thin film transistors are each parallel to the scanning line.

The above-mentioned pixel layout structure, wherein the layout method is to arrange two thin film transistors on one side of the data line and form an L-shape perpendicular to each other, and the channels of the two thin film transistors are respectively connected to the data line and the The scan lines are parallel.

The above pixel layout structure, wherein the layout method arranges four thin film transistors on both sides of the data line, each side of the data line has the two thin film transistors perpendicular to each other and the two thin film transistors on each side Channels of the two thin film transistors are parallel to the data line and the scanning line, and the thin film transistors are connected in a ㄇ shape.

In the above pixel layout structure, the flexible substrate is a plastic substrate.

In the above pixel layout structure, the flexible substrate is a metal foil substrate.

In the above pixel layout structure, the silicon material in the thin film transistor may be amorphous silicon material.

In the above pixel layout structure, the silicon material in the thin film transistor may be polysilicon material.

The pixel layout structure above, wherein the flexible display is a TFT LCD.

The pixel layout structure above, wherein the flexible display is AMOLED.

In the above pixel layout structure, the thin film transistor is a PMOS transistor.

In the above pixel layout structure, the thin film transistors are NMOS transistors.

In a word, the present invention proposes a pixel layout structure applied on a flexible substrate. The pixel structure is different from traditional pixels and includes a plurality of thin film transistors, and the plurality of thin film transistors are connected to each other in a variety of layouts, and The driving current of each thin film transistor is enough to drive the load resistance and capacitance of the pixel, so even if the process alignment is poor or the substrate is bent and deformed, as long as one of the transistors can work normally, the pixel can be guaranteed to display normally, and thus effectively Improve the reliability of pixels on flexible substrates.

Description of drawings

FIG. 1A is a schematic diagram of a pixel layout structure on a substrate of a known display;

FIG. 1B is a schematic diagram of a pixel structure of a known display that is shifted to the right in pattern position alignment during the manufacturing process;

FIG. 1C is a schematic diagram of a pixel structure of a known display that is shifted to the left in pattern position alignment during the manufacturing process;

2A is a schematic diagram of the first embodiment of the pixel layout structure applied to the flexible substrate of the present invention;

FIG. 2B is a schematic diagram of the pixel structure of the first embodiment of the present invention being shifted left and right in pattern position alignment during the manufacturing process;

FIG. 2C is a schematic diagram of the pixel structure of the first embodiment of the present invention being shifted up and down in pattern position alignment during the manufacturing process;

3A is a schematic diagram of the second embodiment of the pixel layout structure applied to the flexible substrate of the present invention;

FIG. 3B is a schematic diagram of the pixel structure of the second embodiment of the present invention when the pattern position alignment shifts to the left during the manufacturing process;

FIG. 3C is a schematic diagram of the pixel structure of the second embodiment of the present invention being shifted to the right in pattern position alignment during the manufacturing process;

4A is a schematic diagram of a third embodiment of the pixel layout structure applied to a flexible substrate according to the present invention;

4B is a schematic diagram of an upward shift in pattern position alignment during the manufacturing process of the pixel structure according to the third embodiment of the present invention;

FIG. 4C is a schematic diagram of a downward shift in pattern position alignment during the manufacturing process of the pixel structure of the third embodiment of the present invention;

5A is a schematic diagram of a fourth embodiment of the pixel layout structure applied to a flexible substrate according to the present invention;

FIG. 5B is a schematic diagram of the pixel structure of the fourth embodiment of the present invention in which the pattern position alignment shifts left and right during the manufacturing process;

FIG. 5C is a schematic diagram of the pixel structure of the fourth embodiment of the present invention when the pattern position alignment shifts up and down during the manufacturing process;

FIG. 5D is a schematic diagram of oblique offset of pattern position alignment during the manufacturing process of the pixel structure according to the fourth embodiment of the present invention;

6A is a schematic diagram of a fifth embodiment of the pixel layout structure applied to a flexible substrate according to the present invention;

FIG. 6B is a schematic diagram of the pixel structure of the fifth embodiment of the present invention in which the pattern position alignment shifts left and right during the manufacturing process;

FIG. 6C is a schematic diagram of the pixel structure of the fifth embodiment of the present invention when the pattern position alignment shifts up and down during the manufacturing process;

FIG. 6D is a schematic diagram illustrating oblique deviation of the pattern position alignment during the manufacturing process of the pixel structure according to the fifth embodiment of the present invention.

Among them, reference signs:

100～array substrate

110～data line

120～scanning lines

132～electrodes

134～oxide

136～silicon material

200, 300, 400, 500, 600～flexible substrate

210, 310, 410, 510, 610～data line

220, 320, 420, 520, 620～scanning lines

230, 330, 430, 530, 630～thin film transistor

232, 332, 432, 532, 632～electrode

236, 336, 436, 536, 636～silicon material

240, 340, 440, 540, 640～thin film transistor

242, 342, 542, 642～electrode

246, 346, 446, 546, 646～silicon material

450, 650～thin film transistor

456, 656～silicon material

652～electrodes

660～thin film transistor

666～silicon material

Detailed ways

In order to have a further cognition and understanding of the features, purposes and functions of the present invention, the detailed description is as follows in conjunction with the accompanying drawings:

FIG. 2A shows the first embodiment of the pixel layout structure of the present invention. The pixel structure is suitable for being arranged on a flexible substrate 200 and driven by a data line 210 and a scanning line 220. The pixel layout structure includes Two thin film transistors 230 and 240, the two thin film transistors are simply represented by the silicon material 236 and 246 in the active region, and the electrodes 232 and 242 are used to provide electrical connection, wherein the layout of the two thin film transistors 230 and 240 is arranged on the data line Both sides of 210 and the channels of the two thin film transistors are parallel to the data line 210 . With this layout method, even if the pattern alignment is slightly shifted left and right during the process, as shown in Figure 2B, at least one transistor can work normally within a certain range of shift; even if the pattern alignment is slightly shifted up and down during the process, as shown in Figure 2B As shown in 2C, at least one transistor can work normally within a certain offset range. Since the driving current of each transistor is enough to drive the resistance and capacitance loaded by the pixel, as long as one transistor can work normally, it can ensure that the pixel can display normally. To achieve the effect of normal display.

Wherein the flexible substrate 200 can be a plastic substrate or a metal foil substrate, the silicon material in these transistors can be amorphous silicon material or polycrystalline silicon material, and the flexible display to which the present invention can be applied includes TFTLCD or AMOLED, such The thin film transistor can be selected as a PMOS transistor or an NMOS transistor depending on requirements.

FIG. 3A shows the second embodiment of the pixel layout structure of the present invention. The pixel structure is suitable for being arranged on a flexible substrate 300 and driven by a data line 310 and a scanning line 320. The pixel layout structure includes Two thin film transistors 330 and 340, the two thin film transistors are simply represented by silicon materials 336 and 346 in the active region, and the electrodes 332 and 342 are used to provide electrical connection, wherein the layout of the two thin film transistors 330 and 340 is arranged on the data line One side of 310 and the channels of the two thin film transistors are parallel to the data line 310 . With this layout method, even if the pattern alignment is slightly shifted to the left during the process, as shown in Figure 3B, at least one transistor can work normally within a certain range of shift; or the pattern alignment is slightly shifted to the right during the process , as shown in FIG. 3C , at least one transistor can work normally within a certain offset range. Since the driving current of each transistor is enough to drive the resistance and capacitance loaded by the pixel, as long as one transistor can work normally, it can ensure that the pixel can display normally. To achieve the effect of normal display.

FIG. 4A shows the third embodiment of the pixel layout structure of the present invention. The pixel structure is suitable for being arranged on a flexible substrate 400 and driven by a data line 410 and a scanning line 420. The pixel layout structure includes A plurality of thin film transistors 430, 440 and 450, these thin film transistors are simply represented by the silicon material 436, 446 and 456 in the active area, and the electrode 432 is used to provide electrical connection, wherein the layout of the plurality of thin film transistors is set in the data One side of the line 410 and channels of the plurality of thin film transistors are parallel to the scan line 420 . With this layout method, even if there is a slight upward shift in the pattern alignment during the manufacturing process, as shown in Figure 4B, at least one transistor can work normally within a certain shift range; or a slight downward shift in the pattern alignment during the manufacturing process, As shown in FIG. 4C , at least one transistor can work normally within a certain offset range. Since the driving current of each transistor is enough to drive the resistance and capacitance loaded by the pixel, as long as one transistor can work normally, it can ensure that the pixel can display normally. To achieve the effect of normal display.

FIG. 5A shows the fourth embodiment of the pixel layout structure of the present invention. The pixel structure is suitable for being arranged on a flexible substrate 500 and driven by a data line 510 and a scanning line 520. The pixel layout structure includes Two thin film transistors 530 and 540, the two thin film transistors are simply represented by silicon materials 536 and 546 in the active region, and the electrodes 532 and 542 are used to provide electrical connection, wherein the layout of the two thin film transistors is set on the data line 510 The sides are perpendicular to each other to form an L shape, and the channels of the two thin film transistors 530 and 540 are parallel to the data line 510 and the scan line 520 respectively. With this layout method, even if there is a slight left-right shift in the pattern alignment during the manufacturing process, as shown in Figure 5B, at least one transistor can work normally within a certain shift range; or a slight up-down shift in the pattern alignment during the manufacturing process, such as As shown in Figure 5C, at least one transistor can work normally within a certain offset range; even a slight oblique offset occurs in the pattern alignment during the process, as shown in Figure 5D, at least one transistor can work normally within a certain offset range Work. Since the driving current of each transistor is enough to drive the resistance and capacitance loaded by the pixel, as long as one transistor can work normally, it can ensure that the pixel can display normally. To achieve the effect of normal display.

FIG. 6A shows the fifth embodiment of the pixel layout structure of the present invention. The pixel structure is suitable for being arranged on a flexible substrate 600 and driven by a data line 610 and a scanning line 620. The pixel layout structure includes Four thin film transistors 630, 640, 650 and 660, the four thin film transistors are simply represented by the silicon material 636, 646, 656 and 666 in the active region, and the electrodes 632, 642 and 652 are used to provide electrical connections, wherein the four thin film transistors The layout is that there are two thin film transistors arranged on both sides of the data line 610, which are perpendicular to each other and parallel to the data line 610 and the scanning line 620, and are connected in a ㄇ shape. Line 610 and the scan line 620 are parallel. With this layout method, even if the pattern alignment is slightly shifted left and right during the manufacturing process, as shown in Figure 6B, at least one transistor can work normally within a certain shift range; or the pattern alignment is slightly shifted up and down during the manufacturing process, as As shown in Figure 6C, at least one transistor can work normally within a certain offset range; even a slight oblique offset occurs in the pattern alignment during the process, as shown in Figure 6D, at least one transistor can work normally within a certain offset range Work. Since the driving current of each transistor is enough to drive the resistance and capacitance loaded by the pixel, as long as one transistor can work normally, it can ensure that the pixel can display normally. To achieve the effect of normal display.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (9)

1. pixel arrangement structure that is applied to flexible display, be suitable for being disposed on the bendable substrate, and drive by a data line and one scan line, it is characterized in that, described pixel arrangement structure comprises a plurality of thin film transistor (TFT)s, each thin film transistor (TFT) comprises a gate, a passage and one source pole/drain, link these a plurality of thin film transistor (TFT)s with a layout type in the wherein said pixel arrangement structure, even make that by described layout type pattern is aligned in the certain deviation scope, also have a described thin film transistor (TFT) operate as normal at least;

Wherein, two thin film transistor (TFT)s are arranged at the channel of the both sides of described data line and described two thin film transistor (TFT)s that each is parallel with described data line for described layout type; Perhaps

Described layout type is arranged at the channel of a side of described data line and described two thin film transistor (TFT)s with two thin film transistor (TFT)s, and each is parallel with described data line; Perhaps

Described layout type will at least three thin film transistor (TFT)s be arranged at the channel of side of described data line and described thin film transistor (TFT) each is parallel with described sweep trace; Perhaps

Described layout type is arranged at side of described data line and orthogonal one-tenths L type with two thin film transistor (TFT)s, and the channel of described two thin film transistor (TFT)s is respectively parallel with described data line and described sweep trace; Perhaps

Described layout type is arranged at four thin film transistor (TFT)s the both sides of described data line, each side of described data line respectively has the channel of described two thin film transistor (TFT)s of orthogonal and each side of two thin film transistor (TFT)s, and each is parallel with described data line and described sweep trace, and described four thin film transistor (TFT)s connect to the ㄇ type.

2. pixel arrangement structure according to claim 1 is characterized in that, described bendable substrate is a plastic base.

3. pixel arrangement structure according to claim 1 is characterized in that, described bendable substrate is a metal forming substrate.

4. pixel arrangement structure according to claim 1 is characterized in that, the silicon materials in the described thin film transistor (TFT) are amorphous silicon material.

5. pixel arrangement structure according to claim 1 is characterized in that, the silicon materials in the described thin film transistor (TFT) are polycrystalline silicon material.

6. pixel arrangement structure according to claim 1 is characterized in that, described flexible display is TFT LCD.

7. pixel arrangement structure according to claim 1 is characterized in that, described flexible display is AMOLED.

8. pixel arrangement structure according to claim 1 is characterized in that, described thin film transistor (TFT) is the PMOS transistor.

9. pixel arrangement structure according to claim 1 is characterized in that, described thin film transistor (TFT) is a nmos pass transistor.

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