CN1920771A - Processing method for special register supporting regular record variables access - Google Patents

Abstract

The invention discloses a processing method supporting special register group access by rule record variable. The method includes: 1) designing a new type attribute to identify the type of the rule record variable that needs to be put into a special register group; 2) designing the syntax tree structure of the rule record variable, and using a recursive algorithm to realize the calculation of the relative position of each member of the rule record variable; 3) Design the intermediate representation of the rule record variable; 4) Generate the code for using the rule record variable to access the special register group. Advantages of the present invention: 1) retain the advantages of high-level language development, overcome the shortcoming that high-level language is difficult to directly control special hardware, improve programming efficiency, and shorten development cycle; 2) shield the details of underlying hardware from programmers, and can Flexible handling of usage specifications of various special-purpose register groups; 3) exposing more optimization opportunities to the compiler to improve system performance.

Description

A Processing Method Supporting Using Rules to Record Variables to Access Special Register Banks

technical field

The invention relates to the development of embedded software with special-purpose register groups in processors, in particular to a processing method for supporting access to special-purpose register groups by using rules to record variables.

Background technique

The purpose of high-level language design is to make programs written in accordance with human thinking and language habits, and it is oriented to programmers. The high-level language widely used in the embedded field is C language. What a computer can directly recognize and execute is not a high-level language, but a collection of machine instructions expressed in binary code, that is, machine language. Assembly language replaces binary machine instructions with mnemonics, but it is still control information for hardware operations, so it is a machine-oriented low-level language like machine language.

The source program written in high-level language needs to be transformed into machine language object code to run on the computer. This transformation usually includes two stages: the first stage is to transform the source program into assembly language representation, and the latter stage is to transform the assembly representation into machine language object code. The latter stage is completed by assembler and linker, which has nothing to do with the present invention. The previous stage is completed by the compiler, and the work of the present invention also all concentrates on this stage. The compilation in the following, if not specified, refers to the process of transforming the source program of the high-level language into the assembly language representation.

The work of a compiler can be divided into several stages, usually divided into lexical analysis, syntax analysis, semantic analysis, intermediate code generation, code optimization and code generation stages, see Document 1: "Compiler Principles and Technologies (Second Edition)", Chen Yiyun ,1997. These phases of the compiler are often further divided into front-end and back-end. The front end only depends on the source language and usually includes the first three stages, namely lexical analysis, syntactic analysis and semantic analysis. The front end performs different analyzes on the source program to interpret the structure and basic data of the source program and determine their meaning. Among them, the semantic analysis stage checks the semantic correctness of the program and collects type information for the subsequent code generation stage. It uses the syntax tree determined in the syntax analysis stage to represent the operators and operands of expressions and statements. The compiler generates an intermediate representation of the source program during the intermediate code generation phase. The intermediate representation is a program of an abstract machine, which is easy to generate and translate into an object program. The backend of the compiler refers to the part of the compiler that depends on the target machine. It is generally independent of the source language and related to the intermediate language, including code optimization and code generation. The code optimization phase attempts to improve the code and produce object code that executes faster. The code generation stage translates the intermediate code into an equivalent sequence of machine instructions.

With the mass application of embedded processors, the development of embedded software becomes more and more important. For an embedded processor, being able to have a large number of application program support is the premise of pushing it to the market. Therefore, shortening the software development cycle and improving the quality of software development play a vital role in the entire development process. Some embedded processors have very high requirements on performance, for example, the routers of the backbone network are required to be able to support the packet forwarding rate of the upper G. Special techniques are used in this class of embedded processors to increase processing speed, one of which is the special purpose register set. These special-purpose register groups are used to store key data to overcome memory access bottlenecks and speed up data access, and cannot be used for compiler register allocation. How to make full use of these special-purpose register groups in embedded software is one of the keys to improve performance.

In the current embedded software development, there are two main ways to access the special register group: assembly language programming and mixed programming using high-level language and assembly language.

The advantages of assembly language programming are high operating efficiency and flexible control of special register groups, but the disadvantages are that programmers are required to directly operate hardware, programming efficiency is not high, and it is difficult to debug and transplant.

Hybrid programming is an option of last resort. High-level language overcomes the shortcomings of assembly language, but due to the limitation of high-level language syntax, it is difficult to directly use high-level language to operate the special register set provided by embedded processor, only by means of assembly statement embedded in high-level language source program to operate the hardware. As shown in the following C language source program fragment:

int a asm(%r18");//put the global variable a into the register %r18

void function()

{

int b asm("%r22");//The local variable b is specified to be placed in the register %r22

...

}

One disadvantage of mixed programming is that it is also difficult to transplant. If you change the number of a specific register from %r18 to %r17, you need to modify all occurrences of %r18 in the source program. Another disadvantage is that the functions are limited: 1) Embedded assembly can only use scalars to access dedicated registers, but cannot use rules such as structures and arrays to record variables, so the number of registers that can be accessed is limited by the maximum width of scalars, usually not More than 64 bits (that is, two 32-bit special registers); 2) the scalar can only be used as a whole, when the programmer needs to perform bit field operations on one or several bits of the special register, he needs to handle it himself Details increase the chance of error and reduce programming efficiency.

Therefore, it is desirable to support the handling of variable access special-purpose register banks with rules in high-level languages.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, provide a kind of processing method that supports to visit special-purpose register bank with rule record variable in high-level language, can directly use rule record variable such as structure, union etc. in embedded software development Access the processor's special register set.

In order to achieve the above object, the technical scheme that the present invention takes is as follows:

Supports the processing method of using rules to record variables to access special registers. By extending the functions of the compiler, for the special registers commonly found in embedded processors, the special registers can be defined in the high-level language source program as having certain attributes. Rules record variables for access, and the specific content includes the following four points:

1) Design a new type attribute to identify the type of the rule record variable that needs to be placed in the special register bank.

2) Design the grammatical tree structure of the rule record variable, and use a recursive algorithm to realize the calculation of the relative position of each member of the rule record variable; wherein the name, type, member field, and size of the variable are similar to the general variable grammatical tree structure. The feature bits of the above-mentioned type attributes, and ignore the alignment requirement information of the rule record variable and its field; Variables will be stored in special-purpose register groups, so there is no need to calculate alignment; the member fields of rule record variables are represented by linked lists in the syntax tree structure, and the members are syntax tree structures of general variables except joint variables; the recursive The algorithm traverses the member chain in the rule record variable syntax structure after the compiler analyzes the type attribute information, calculates the offset of the member in the rule record variable regardless of the type and alignment requirements of the member, and resets the compiler when building the member syntax tree structure The location information calculated at the time.

3) Design the intermediate representation of the rule record variable; the structure includes the rule record variable and its special register number, size, start bit and end bit corresponding to each member field; the algorithm for generating the intermediate representation of the rule record variable includes: traversal rule Record the member chain of the variable syntax tree structure, calculate the occupied special register number, start bit and end bit according to the relative position and size of the member, and instruct the compiler that the special register does not participate in register allocation.

4) Generate the code that uses the rule record variable to access the special register group; the algorithm used is divided into two modules: the data extraction module that extracts the member data of the rule record variable from the special register group and the data storage module that stores the member data of the rule record variable to the special register group ; Among them, the data extraction module is divided into three processes: data alignment, data-independent bit masking and special register reading and writing; the process of the data storage module is the reverse process of the above three processes; each process selects the appropriate processing according to the data size and position The code is generated by register instruction or instruction combination; the shift instruction is usually selected for general data alignment, the bitwise AND or instruction is selected for data-independent bit masking, and the data movement instruction is selected for special register reading and writing; for the case where a single member data occupies multiple special registers , the algorithm divides the data into multiple parts according to the register boundaries, each part is located in a single special-purpose register, after extracting or storing code generation, and finally generating the code to combine the data of each part.

Compared with the prior art, the processing method proposed by the present invention has the following advantages:

1) It retains the advantages of high-level language development, and overcomes the disadvantage that high-level language is difficult to directly control special hardware. Programmers use the special register set provided by the processor like using ordinary rules to record variables, without resorting to assembly statements , it can not only access the special register group as a whole, but also access one bit, several bits of a single register or access across register boundaries, which improves programming efficiency and shortens the development cycle;

2) The details of the underlying hardware are shielded from the programmer, and the use specifications of various special register sets can be flexibly handled. When the use specifications of special register sets change, only the mapping process of generating intermediate code in the compiler needs to be modified, and no Make any modification to the source program;

3) More optimization opportunities are exposed to the compiler, improving system performance.

Detailed ways

Below in conjunction with specific embodiment the present invention is described in further detail:

Supports the processing method of using rules to record variables to access special register groups, and the processing flow is as follows:

1) Add support for the type attribute of a high-level language such as C language in the compiler, and check the rule record variable in the source program. If it has this type attribute, the compiler will recognize it as needing to be placed in a special register group; if there is no attribute of this type, the compiler will process it according to a known method; this step includes the following sub-steps:

Step 1.1: Increase the length of the attribute array inside the compiler so that it can accommodate the newly added attribute;

Step 1.2: Modify the initialization function of the attribute array, so that the newly added attribute parameters can be correctly initialized, and the compiler can recognize this attribute when performing lexical analysis and syntax analysis;

2) The front-end of the compiler recognizes the rule record variable that needs to be put into the special register group according to the type attribute, and builds a syntax tree structure for it, sets the feature bit corresponding to the attribute in the syntax tree structure to 1, and according to the name of the variable , type, member field, size, alignment requirements, etc. to set the corresponding fields of the syntax tree structure. In addition, the calculation of the syntax tree structure and field information is also determined by the hardware designer. ) decision; this step includes the following sub-steps:

Step 2.1: Modify the definition of the syntax tree structure inside the compiler, and add the feature bit corresponding to this attribute;

Step 2.2: When the compiler performs grammatical analysis, it will establish a corresponding grammatical tree structure for the variable definition, and set the flag bit corresponding to this attribute to 1;

Step 2.3: The compiler analyzes the variable type, fills the syntax tree structure according to the variable name, type, and field, and records the size, alignment requirements, and starting position of each member of the variable according to the recursive calculation rules of the special register group usage specification.

3) In the intermediate code generation stage of the compiler, for the syntax tree structure whose feature bit is 0, it is processed as an ordinary variable, and for the syntax tree structure generated in step 2, a corresponding intermediate representation will be established for the variable and each of its subfields, Including its corresponding special register number, size, start bit and end bit. This step includes the following sub-steps:

Step 3.1: If the feature bit of the syntax tree structure is 0, then process it as a common variable, and perform step 4);

Step 3.2: For the syntax tree structure with a feature bit of 1 established in step 2.2, establish a corresponding intermediate representation for the variable and each of its subfields, and initialize basic information such as the name and type of the variable in the intermediate representation;

Step 3.3: According to the size, starting position and alignment information of each bit field calculated in step 2.3, the compiler maps each bit field to a special register group, and sets its corresponding intermediate code, including its corresponding special register Label, size, start bit and end bit.

4) The backend of the compiler utilizes the intermediate representation generated in step 3) for code generation. This step includes the following sub-steps:

Step 4.1: The compiler generates the intermediate code of the instruction; when the operand of the instruction is stored in the special register group, or when the instruction is used to perform operations on the data in the special register group, this patent supports that the data can cross the boundary of the special register. For such data occupying multiple physical registers, data extraction code and data merging code should be generated;

Step 4.2: The compiler transforms and optimizes the intermediate code of the instruction according to the methods provided by the prior art, including deleting redundant codes for extracting and merging data, and finally outputs the assembly representation.

Claims (7)

1, a kind of processing method that supports to record variables to visit special-purpose register group with the rule, by expanding the function of compiler, for the special-purpose register group commonly existing in the embedded processor, in high-level language source program, special-purpose register group is defined as having Certain attribute rules record variables for access, including the following four points: 1) Define a type attribute to identify the rule record variable type that needs to be put into the special register group; 2) Design the syntax tree structure of the rule record variable, and use a recursive algorithm to realize the calculation of the relative position of each member of the rule record variable; wherein the name, type, member field, and size of the variable are the same as the general variable syntax tree structure, and the increase indicates that step 1) The characteristic bit of the above-mentioned type attribute, and ignore the alignment requirement information of the rule record variable and its member field; the member field of the rule record variable is represented by a linked list in the syntax tree structure, and the members are the syntax tree structure of the general variable; 3) Design the intermediate representation of the rule record variable; the structure includes the rule record variable and its special register number, size, start bit and end bit corresponding to each member field; the algorithm for generating the intermediate representation of the rule record variable includes: traversal rule Record the member chain of the variable syntax tree structure, calculate the occupied special register number, start bit and end bit according to the relative position and size of the member, and instruct the compiler that the special register does not participate in register allocation; 4) Generate the code that uses the rule record variable to access the special register group; the algorithm used is divided into two modules: the data extraction module that extracts the member data of the rule record variable from the special register group and the data storage module that stores the member data of the rule record variable to the special register group ; Wherein, the data extraction module is divided into three processes: data alignment, data-independent bit masking and special register read and write; the process of the data storage module is the inverse process of the above three processes; each process is based on data size and position Select the appropriate processor instruction or combination of instructions to generate code. 2. The method according to claim 1, characterized in that, the recursive algorithm in step 2) traverses the grammatical structure of the rule record variable after the compiler analyzes the type attribute information In the member chain in , the offset of the member in the rule record variable is calculated regardless of the type and alignment requirements of the member, and the position information calculated by the compiler when building the member syntax tree structure is reset. 3. A processing method that supports using rule record variables to access special register groups, the processing flow is as follows: 1) Add support for the type attribute of a high-level language in the compiler, and check the rule record variable in the source program. If it has the type attribute, the compiler will recognize it as needing to be placed in the special register group; If there is no such type attribute, the compiler will handle it according to the known method; 2) The front-end of the compiler recognizes the rule record variable that needs to be put into the special register group according to the type attribute, and will establish a syntax tree structure for it, set the feature bit corresponding to the attribute in the syntax tree structure to 1, and set it according to the variable information The corresponding domain of the syntax tree structure; 3) In the intermediate code generation stage of the compiler, for the syntax tree structure with a feature bit of 0, it is processed as an ordinary variable, and for the syntax tree structure generated in step 2), a corresponding intermediate representation will be established for the variable and each of its subfields , including its corresponding special register number, size, start bit and end bit; 4) The backend of the compiler utilizes the intermediate representation generated in step 3) for code generation. 4. The method according to claim 3, characterized in that said step 1) includes the following sub-steps: Step 1.1: Increase the length of the attribute array inside the compiler so that it can accommodate the newly added attribute; Step 1.2: Modify the initialization function of the attribute array, so that the newly added attribute parameter can be correctly initialized, and at the same time, the compiler can recognize this attribute when performing lexical analysis and syntax analysis. 5. The method according to claim 3, characterized in that said step 2) includes the following sub-steps: Step 2.1: Modify the definition of the syntax tree structure inside the compiler, and add the feature bit corresponding to this attribute; Step 2.2: When the compiler performs grammatical analysis, it will establish a corresponding grammatical tree structure for the variable definition, and set the flag bit corresponding to this attribute to 1; Step 2.3: The compiler analyzes the variable type, fills the syntax tree structure according to the name, type, and domain of the variable, and records the size, alignment requirements, and starting position of each member of the variable according to the recursive calculation rules of the special register group usage specification; Described step 3) comprises following sub-step: Step 3.1: If the feature bit of the syntax tree structure is 0, then process it as a common variable, and perform step 4); Step 3.2: For the syntax tree structure with a feature bit of 1 established in step 2.2, establish a corresponding intermediate representation for the variable and each of its subfields, and initialize the basic information about the variable in the intermediate representation; Step 3.3: According to the size, starting position and alignment information of each bit field calculated in step 2.3, the compiler maps each bit field to a special register group, and sets its corresponding intermediate representation, including its corresponding special register Label, size, start bit and end bit. 6. The method according to claim 3, characterized in that said step 4) includes the following sub-steps: Step 4.1: The compiler generates the intermediate code of the instruction; when the operand of the instruction is stored in the special register group, or when the instruction is used to perform operations on the data in the special register group, the data can cross the boundary of the special register; For the data of physical registers, data extraction code and data merging code should be generated; Step 4.2: The compiler transforms and optimizes the intermediate code of the instruction, including deleting redundant codes for extracting and merging data, and finally outputs the assembly representation. 7. A processing method that supports using rule record variables to access special register groups, the processing flow is as follows: 1) Add support for the type attribute of a high-level language in the compiler, and check the rule record variable in the source program. If it has the type attribute, the compiler will recognize it as needing to be placed in the special register group; If there is no such type attribute, the compiler proceeds according to a known method; this step includes the following sub-steps: Step 1.1: Increase the length of the attribute array inside the compiler so that it can accommodate the newly added attribute; Step 1.2: Modify the initialization function of the attribute array, so that the newly added attribute parameters can be correctly initialized, and the compiler can recognize this attribute when performing lexical analysis and syntax analysis; 2) The front-end of the compiler recognizes the rule record variable that needs to be put into the special register group according to the type attribute, and will establish a syntax tree structure for it, set the feature bit corresponding to the attribute in the syntax tree structure to 1, and set it according to the variable information The corresponding domain of the syntax tree structure; this step includes the following sub-steps: Step 2.1: Modify the definition of the syntax tree structure inside the compiler, and add the feature bit corresponding to this attribute; Step 2.2: When the compiler performs grammatical analysis, it will establish a corresponding grammatical tree structure for the variable definition, and set the flag bit corresponding to this attribute to 1; Step 2.3: The compiler analyzes the variable type, fills the syntax tree structure according to the name, type, and domain of the variable, and records the size, alignment requirements, and starting position of each member of the variable according to the recursive calculation rules of the special register group usage specification; 3) In the intermediate code generation stage of the compiler, for the syntax tree structure whose feature bit is 0, it is processed as an ordinary variable, and for the syntax tree structure generated in step 2, a corresponding intermediate representation will be established for the variable and each of its subfields, Including its corresponding special register number, size, start bit and end bit; this step includes the following sub-steps: Step 3.1: If the feature bit of the syntax tree structure is 0, then process it as a common variable, and perform step 4); Step 3.2: For the syntax tree structure with a feature bit of 1 established in step 2.2, create a corresponding intermediate code for the variable and each of its subfields, and initialize the basic information about the variable in the intermediate representation; Step 3.3: According to the size, starting position and alignment information of each bit field calculated in step 2.3, the compiler maps each bit field to a special register group, and sets its corresponding intermediate code, including its corresponding special register label, size, start bit and end bit; 4) The backend of the compiler uses the intermediate representation generated in step 3) to generate code; this step includes the following sub-steps: Step 4.1: The compiler generates the intermediate code of the instruction; when the operand of the instruction is stored in the special register group, or when the instruction is used to perform operations on the data in the special register group, the data can cross the boundary of the special register; For the data of physical registers, data extraction code and data merging code should be generated; Step 4.2: The compiler transforms and optimizes the intermediate code of the instruction according to the methods provided by the prior art, including deleting redundant codes for extracting and merging data, and finally outputs the assembly representation.