CN1909430B - A Method for Delaying Payload Data of Optical Synchronous Digital Transport Network Channel - Google Patents

Abstract

The invention relates to a method for delaying the load data of light synchronous digit transmission network channel, wherein it comprises: de-multiplexing the STM-1, STM-4, STM-16, or STM-64, to store the separated load and load instruction of said delay channel into FIFO to store the channel; when the write address of FIFO is equal to the delay byte, reading the load and load instruct of delay channel from FIFO, to be multiplexed with other non-delay channel to form new STM-1, STM-4, STM-16, or STM-64. The invention provides needed channel delay data for the transmission chip design, based on the property of delay data to adjust the chip design.

Description

A Method for Delaying Payload Data of Optical Synchronous Digital Transport Network Channel

technical field

The invention relates to a method for delaying optical synchronous digital transport network (SDH) channel payload data, in particular to technologies such as virtual concatenation delay compensation processing and channel delay processing in SDH transmission systems in the communication field.

Background technique

In the prior art, delay refers to the group delay of digital signal transmission, that is, it always takes a certain time for a signal to be transmitted from one place to another. There are three main reasons for the delay, including the delay caused by the transmission system, the delay caused by the network digital equipment, and the delay caused by the introduction of SDH equipment. Since the delay of the photoelectric signal in the medium propagation is related to the refractive index of the transmission medium, the existence of the refractive index of the medium will cause a certain delay in the transmission signal, which is the delay caused by the transmission system. When network node equipment is introduced into the transmission system, equipment such as buffers and time slot switching units that the network equipment may have will generate signal delays. When some special transmission equipment is introduced into the transmission network, the delay may be reduced or increased. In the SDH system, using pointer adjustment technology for phase alignment and frequency correction can reduce the total delay of the equipment, but Pointer processing, fixed stuffing processing, mapping and unmapping processing, etc. all add latency to the overall system.

Delay has different effects on different services. For voice services, if the delay is too large, the voice clarity will be reduced and voice delay will occur; for data services, the transmission efficiency will be reduced. The SDH system can carry voice services and data services, so the existence of delay will have a certain impact on the services of the SDH transmission system. When carrying voice and data services, the channel payloads of AU4, AU3, TU3, TU2, TU12 or TU11 in the SDH system may have different degrees of delay in the process of mapping and demapping, which will reduce the performance of transmission equipment . In the SDH transmission system, virtual concatenation is generally adopted for the transmission of service information with a capacity greater than the standard AU4, AU3, TU3, TU2, TU12 or TU11 channels. Virtual concatenation is a combination of multiple virtual containers. , so that these combined virtual containers can be used as a virtual container with a relatively large capacity or a relatively suitable capacity, and the use of virtual concatenation technology can better transmit data services and effectively utilize bandwidth. Since the transmission paths of the channels constituting the virtual concatenation group may be different, different channels may have different delays. In addition, the order of the increase or decrease of the channels constituting the virtual concatenation group may cause the data to be sent not necessarily in accordance with Channel time slots are numbered sequentially, but in the transmission system, data is transmitted in the order of channel time slots, so the virtual concatenation processing chip and equipment must adjust the channel time slot order of the virtual concatenation group accordingly, according to the original Regularly align and rearrange the order to avoid the impact of delay.

Due to the impact of delay on the performance of transmission equipment, the possible impact of different delays on corresponding chip functions must be considered when developing SDH transmission chips with functions such as mapping and demapping, and virtual concatenation. In the SDH mapping and demapping, virtual concatenation related chip design process, it is necessary to generate various delay delay generation devices for different channel payloads, so that designers can use this delay device to change and modify the design of the chip at any time , in order to meet the conditions of different delays, the mapping and demapping of the chip, and the virtual concatenation function are all normal, and the design performance of the chip is improved.

In the prior art, no relevant technical content about the method for generating the transmission delay has been found.

Contents of the invention

The purpose of the present invention is to provide a method for delaying optical synchronous digital transmission network channel payload data, provide a method for delaying channel payload data for SDH transmission system chip design, and provide various channel delays for transmission chip design The method, using this patented method can generate different delays of the channel payloads of STM-1, STM-4, STM-16 and STM-64, such as AU4, AU3, TU3, TU2, TU12 and TU11, in solving mapping, De-mapping and virtual concatenation functions are essential, and the design of the transmission chip in terms of virtual concatenation and mapping functions is corrected to improve chip design performance.

Technical scheme of the present invention is as follows:

A method for delaying optical synchronous digital transmission network channel payload data, it comprises the following steps:

After channel demultiplexing of STM-1, STM-4, STM-16 or STM-64, the payload and payload indication of the separated delay channel are stored in the FIFO for channel storage, when the write of the FIFO When the address is equal to the delayed byte, read the payload and payload indication of the corresponding delayed channel from the FIFO, and perform channel multiplexing with other undelayed channels to form new STM-1, STM-4, STM- 16 or STM-64;

Specifically include the following steps:

a: The payload, payload indication and frame header multiplexing indication obtained from the channel demultiplexing are delayed by one beat and then the high-order channel overhead byte indication is located;

b: perform channel demultiplexing according to the high-order path overhead byte indication, and use the high-order path overhead byte indication, delay configuration information and SDH frame structure multiplexing mapping principle to obtain the payload and the delay path Payload indication, and the undelayed part includes the overhead pointer of the delayed channel, the section overhead and the payload and payload indication of the undelayed channel;

c: write the payload and payload indication of the delayed channel into the FIFO, and simultaneously delay the payload and payload indication of the undelayed part by two beats;

d: when the write address of the FIFO is equal to the delay byte of the delay channel, read the payload and the payload indication of the delay channel;

e: The undelayed part and the delayed channel are multiplexed according to the SDH frame structure multiplexing mapping principle to generate a new STM-1, STM-4, STM-16 or STM-64 frame with a delayed channel, where the delayed The payload of the time channel is the payload read from the FIFO, and the payload indication of the delay channel is the payload indication read from the FIFO.

The method, wherein, the step c also includes:

d1: The delay time is represented by the number of delayed bytes;

d2: The unit of the delay byte is a single byte, the total number of payload bytes of various channels, the total number of single frame bytes and the total number of multiframe bytes;

d3: When the payload indication of the delay channel is valid, the FIFO starts to write the payload and payload indication of the delay channel, and the writing does not stop;

Said step d also includes:

d4: When the write address of the FIFO is less than the delay byte of the delay channel, the payload sent to the delay channel of the step e is 0, and the payload indicator is low; when the delay time value corresponds to When the number of bytes is equal to the write address of the FIFO, the FIFO reads out the payload and the payload indication of the delay channel, and the reading does not stop.

The method described above, wherein, the specific relationship between the delay time and the number of delayed bytes is that a delay of 125 microseconds is equal to a delay of 2430 bytes.

A method for delaying the channel payload data of the optical synchronous digital transmission network provided by the present invention provides the required channel delay data for the design of the transmission chip, so that the chip design can be continuously adjusted according to the performance of the channel delay data processing, and the The design performance of the transmission chip in terms of processing channel delay and virtual concatenation delay compensation and other functions.

Description of drawings

Fig. 1 is the flow chart of realizing the channel delay of AU4, AU3, TU3, TU2, TU12 or TU11 channel of SDH system of the present invention suitable for STM-1, STM-4, STM-16 or STM-64 frame.

Detailed ways

Various preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

The method for delaying optical synchronous digital transmission network channel payload data of the present invention, its core idea is: after channel demultiplexing is carried out to STM-1, STM-4, STM-16 and STM-64 etc., will separate The payload and payload indication of the desired delay channel are stored in the FIFO for channel storage. When the write address of the FIFO is equal to the delay byte, that is, the delay time, read the payload and payload indication of the delay channel from the FIFO , and then perform channel multiplexing with other undelayed channels to form new STM-1 data.

The method for delaying optical synchronous digital transmission network channel payload data of the present invention, as shown in Figure 1, it comprises the following steps:

Step 1: Delay the payload ID, payload indication IPL, and frame header multiplexing indication IC1J1 of STM-1 (STM-4, STM-16, and STM-64, etc.) by one beat to locate the high-order path overhead word Section J1;

Step 2: Perform channel demultiplexing according to the J1 indication, and use the J1 indication, delay configuration information and SDH frame structure multiplexing mapping principle to obtain the payload and payload indication of the delayed channel, and the undelayed part including the delay Channel overhead pointers, segment overhead, and undelayed channel payloads and payload indications;

Step 3: Write the payload and payload indication of the channel to be delayed into the synchronous FIFO of the FIFO, and simultaneously delay the payload and payload indication of the undelayed part by two beats;

Step 4: When the write address of the FIFO is equal to the delay byte of the delay channel, the FIFO starts to read the payload and payload indication of the delay channel;

Step 5: The undelayed part and the delayed channel are multiplexed according to the SDH frame structure multiplexing mapping principle to generate a new STM-1 (STM-4, STM-16 and STM-64, etc.) with a delayed channel frame, in the new STM-1 (STM-4, STM-16 and STM-64 etc.) Read payload indication.

The method for reading and writing FIFO in the fourth step above specifically includes:

First: The delay time is represented by the number of delayed bytes. The specific relationship is that a delay of 125 microseconds is equivalent to a delay of 2430 bytes;

Second: The delay unit is single byte, the total number of payload bytes of various channels, the total number of single frame bytes and the total number of multiframe bytes, etc.;

Third: When the payload indication of the delay channel is valid, FIFO starts to write the payload and payload indication of the delay channel, and the FIFO writing will not stop;

Fourth: When the write address of the FIFO is less than the delay byte of the delay channel, the payload sent to the delay channel in the fifth step is 0, and the payload indicator is low; when the word corresponding to the delay time value When the section number is equal to the write address of the FIFO, the FIFO starts to read the payload and payload indication of the delay channel, and the FIFO read will not stop.

The above-mentioned technical scheme of the present invention is applicable to the generation process of the delay channels of STM-1 frame and TU11, TU12, TU2, TU3, AU3 and AU4 etc. of STM-4, STM-16 and STM-64 etc. channels.

Below in conjunction with accompanying drawing 1, take the TU12 channel delay of STM-1 as an example to further describe in detail the implementation of the technical solution of the present invention, as shown in Figure 1:

Step 1: Delay STM-1 related signals such as payload (ID), payload indication (IPL) and frame header multiplexing indication (IC1J1) by one beat at the same time, and determine the J1 indication according to IPL and IC1J1;

Step 2: Obtain the first pointer byte V1 indication and the first overhead word of the TU12 delay channel according to the delay configuration information such as delay time unit and delay time setting, J1 indication and STM-1 multiplexing mapping principle Section V5 indicates that other pointer byte indications are determined according to V1 byte indications, and other overhead byte indications are obtained according to V5 byte indications, and finally this TU12 channel payload indication is obtained; segment overhead indications are determined according to J1, and other undelayed byte indications are obtained. When the channel byte indication and the stuffing and pointer indication filled by multiplexing at all levels, these three indications are combined into one indication, that is, there is no delay part indication;

Step 3: Write the TU12 channel payload indication and channel payload to be delayed obtained in the second step into the FIFO synchronous FIFO, and the number of bytes written into the FIFO is the channel delay value, which is expressed in multiframe bytes The total is the unit; at the same time, the indication and data flow without delay will be delayed by two beats;

Step 4: When the write address of FIFO is equal to the delay byte value of the delay channel, FIFO starts to read the payload and payload indication of the delay channel; when the write address of FIFO is less than the delay byte value of the delay channel , the payload sent to the delay channel in the fifth step below is 0, and the payload indication is low;

Step 5: Multiplex the undelayed part and delayed channel obtained in the third and fourth steps according to the SDH frame structure multiplexing mapping principle to generate a new STM-1 frame with a TU12 delayed channel. In the new STM-1 frame, the payload of the delayed channel is the payload read from the FIFO, and the payload indicator of the delayed channel is the payload indicator read from the FIFO.

The above process specifically describes the channel delay implementation of one TU12 channel of the STM-1 frame, and the TU11, TU2, TU3, AU3 and AU4 of the STM-1 frame, STM-4 frame, STM-16 frame and STM-64 frame, etc. The generation of the delay channel is similar to the above process, and will not be repeated here.

The method for delaying optical synchronous digital transport network channel payload data of the present invention realizes AU4, AU3, TU3, TU2, TU12 of frames such as SDH system STM-1, STM-4, STM-16 or STM-64 Or the various time delays of the TU11 channel payload, so that in the design of the transmission chip, the data with different delay channels can be used to continuously improve and correct the specific design of the chip, thereby improving the transmission mapping and virtual concatenation processing, etc. Chip design performance.

It should be understood that the above descriptions of the present invention for specific embodiments are relatively specific, and should not therefore be construed as limiting the scope of patent protection of the present invention, and the scope of patent protection of the present invention should be based on the appended claims.

Claims (3)

1. the method for a delaying phototiming digital transmission net channel payload data, it may further comprise the steps:

After STM-1, STM-4, STM-16 or STM-64 carried out the passage demultiplexing, store into and carry out the passage storage among the FIFO isolating the indication of time-delay payload of passage and payload, when the write address of described FIFO equals to delay time byte, reading the payload of corresponding time-delay passage and payload indication and other passages of not delaying time from described FIFO carries out channel multiplexing and forms new STM-1, STM-4, STM-16 or STM-64;

Specifically may further comprise the steps:

A: orient the indication of Higher Order Path Overhead byte after the multiplexing indication time-delay one of the payload that described passage demultiplexing goes out, payload indication and frame head is clapped;

B: carry out the passage demultiplexing according to described Higher Order Path Overhead byte indication, utilize described Higher Order Path Overhead byte indication, time-delay configuration information and the multiplexing mapping principle of SDH frame structure, obtain the delay time payload and the payload indication of passage, and the payload and the payload indication of delaying time and partly comprising expense pointer, the section overhead of the passage of delaying time and the passage of not delaying time;

C: the payload and the payload indication of described time-delay passage are written among the FIFO payload of the part of will not delaying time simultaneously and payload indication time-delay two bats;

D: when the write address of described FIFO equals to delay time the time-delay byte of passage, the payload and the payload indication of reading described time-delay passage;

E: not time-delay part and time-delay passage carry out multiplexing according to the multiplexing mapping principle of SDH frame structure, generation has new STM-1, STM-4, STM-16 or the STM-64 frame of a time-delay passage, wherein the delay time payload of payload for reading from described FIFO of passage, the payload of time-delay passage is designated as the payload indication of reading from described FIFO.

2. method according to claim 1 is characterized in that, described step c also comprises:

D1: described time-delay is to represent delay time with the time-delay byte number;

D2: the unit of described time-delay byte is byte, various passage bytes of payload sum, single frames total amount of byte and multi-frame total amount of byte;

D3: when the payload of described time-delay passage is indicated when effective, described FIFO begins to write the payload and the payload indication of time-delay passage, and it writes and does not stop;

Described steps d also comprises:

D4: when the write address of described FIFO during less than the time-delay byte of time-delay passage, the payload that is sent to the time-delay passage of described step e is 0, and payload is designated as low; When the pairing byte number of delay time value equaled the write address of described FIFO, described FIFO read the payload of described time-delay passage and payload indication, and read and do not stop.

3. method according to claim 2 is characterized in that, the physical relationship of described delay time and described time-delay byte number is to equal to delay time 2430 bytes when delaying time 125 microseconds.