CN1909240A - InGaP Enhancement/Depletion Mode Strained High Electron Mobility Transistor Material Structure - Google Patents

Abstract

The utility model provides an indium gallium phosphorus strengthens/depletion type strain high electron mobility transistor material structure, it adopts indium gallium phosphorus/indium aluminium arsenic/indium gallium arsenic material structure, on semi-insulating gallium arsenide substrate material, uses the gradual growth technique to grow linear gradual indium aluminium gallium arsenic epitaxial layer as the buffer layer, then grows in proper order on the buffer layer: the indium-aluminum-arsenic layer, the indium-gallium-arsenic layer, the indium-aluminum-arsenic layer, the plane doping layer, the indium-aluminum-arsenic layer, the strained indium-gallium-phosphorus layer and the indium-gallium-arsenic layer; the ninth indium gallium arsenic epitaxial layer is used as a cap layer, the eighth strained indium gallium phosphorus epitaxial layer is used as a depletion type barrier layer, the seventh indium aluminum arsenic epitaxial layer is used as an enhancement type barrier layer, the fifth indium aluminum arsenic epitaxial layer is used as an isolation layer, and the fourth indium gallium arsenic layer is used as a channel layer.

Description

InGaP Enhancement/Depletion Mode Strained High Electron Mobility Transistor Material Structure

technical field

The invention belongs to the technical field of compound semiconductors, in particular to a gallium arsenide (GaAs)-based monolithic integrated indium gallium phosphide/indium aluminum arsenic/indium gallium arsenic (InGaP/InAlAs/InGaAs) enhanced/depleted strain high electron migration High-frequency transistor (MHEMT) material structure.

Background technique

High Electron Mobility Transistor devices (HEMTs) have by far the highest unity current gain cutoff frequency and lowest noise figure. However, so far, only depletion-type HEMT devices have been widely used in the circuit design of HEMT devices, such as traditional buffered FET logic circuits (BFL) or source-coupled FET logic circuits (SCFL). In actual circuit design, due to the use of depletion-type HEMT devices in these circuits, the consequences and shortcomings are complex circuit structures and high power consumption.

In order to overcome the above shortcomings, the direct coupled field effect transistor logic circuit (DCFL) structure has received more and more attention and attention. The DCFL circuit is composed of enhancement/depletion (E/D) HEMT devices. So far, it has been used in It is one of the best logic circuit technologies in the design of large-scale integrated circuits, and is widely used in the design of frequency dividers, ring oscillators, microwave switches and other circuits. Compared with other logic circuit structures, the DCFL logic circuit structure has very significant advantages and characteristics, which are manifested in its low power consumption, high speed, simple design (such as no level drift) and single power supply operation. However, its disadvantages are low noise tolerance and its sensitivity to threshold voltage variation. Therefore, a DCFL circuit with superior performance must be able to precisely control the device's threshold voltage. The difficulty in the successful manufacture of integrated enhancement/depletion HEMT devices lies in how to design the transistor material structure and how to accurately control the fabrication of enhancement devices in the process, which has always been the bottleneck restricting the wide application of DCFL circuit structures. At present, the typical structure of enhancement/depletion devices widely used at home and abroad is a low-strain AlGaAs/InGaAs pseudo-high electron mobility transistor structure (for representative literature, see M.Tong, K.Nummila, J. - W. Seo. A. Ketterson and I. Adesida, "Process for enhancement/depletion-mode GaAs/InGaAs/AlGaAs pseudomorphic MODFETs using selective wet gaterecessing", Electronics Letters 13 ^th August 1992 Vol. 28 No. 17). Compared with GaAs-based low-strain channel In _x Ga _1-x As (indium composition x<=0.22) HEMT devices, GaAs-based high-strain channel MHEMT devices (indium composition x>0.22) can significantly improve the device performance, such as DC performance (leakage saturation current and transconductance), microwave performance (f _T and f _max ), low frequency noise (Hooge parameters) and high frequency noise (minimum noise figure and noise gain), and more attention and Pay attention to. Table 1 shows the typical material structures of monolithically integrated enhanced/depleted low-strain channel pseudomorphic high-electron transistor (PHEMT) devices that are widely used at present.

Table 1: Schematic diagram of the existing typical GaAs-based monolithic integrated enhancement/depletion low-strain channel PHEMT material structure. serial number Material The molar ratio of% thickness doping concentration 12 Heavily doped GaAs 300 Angstroms Doping source (Si) 5.0E+18cm-3 11 Undoped AlAs 15 Angstroms 10 Undoped Al _x Ga _1-x As 0.17 150 Angstroms 9 Undoped AlAs 15 Angstroms 8 Undoped Al _x Ga _1-x As 0.17 200 Angstroms 7 planar doping Si3.0E+12cm-2 6 Undoped Al _x Ga _1-x As 0.17 20 Angstroms 5 Undoped In _x Ga _1-x As 0.20 170 Angstroms 4 Undoped GaAs 500 Angstroms 3 Undoped Al _x Ga _1-x As 0.45 50 Angstroms 2 The buffer layer 1 Semi-insulating substrate GaAs(100)

This transistor material structure mainly has the following characteristics:

1. Utilize the conduction band difference between Al _x Ga _1-x As/In _y Ga _1-y As two materials to form a two-dimensional InGaAs channel epitaxial layer with low band gap and high electron mobility Electron gas (2DEG), Al composition X in the Al _x Ga _1-x As epitaxial layer = 0.17, In _y Ga _1-y As channel epitaxial layer In composition Y = 0.2, which belongs to the low-strain channel, Their conduction band difference is about 0.27eV, and the barrier layers of the enhancement and depletion PHEMT devices are both Al _x Ga _1-x As epitaxial layers.

2. Since one of the most critical and difficult points in the fabrication of enhancement and depletion PHEMT devices is to maintain the consistency of the enhancement/depletion threshold voltage, in the typical material structure of enhancement and depletion PHEMT devices, by growing two thin layers An aluminum arsenic (AlAs) epitaxial layer acts as an enhancement/depletion etch stop layer to maintain threshold voltage consistency.

Contents of the invention

The purpose of the present invention is to design a gallium arsenide-based monolithic integrated high indium composition indium gallium phosphide/indium aluminum arsenic/indium gallium arsenic enhancement/depletion strained high electron mobility transistor (MHEMT) material structure to overcome the existing There are some deficiencies in the material structure.

In order to achieve the above object, the technical solution of the present invention is to provide an InGaP enhancement/depletion type strained high electron mobility transistor material structure, which adopts the InGaP/InAlAs/InGaAs material structure, in half On the insulating gallium arsenide substrate material, the linear slow-change InAlGaAs epitaxial layer is grown by the slow-change growth technology as a buffer layer, and then sequentially grown on the buffer layer: InAlAs layer, InGaAs layer, InAlAs layer , planar doped layer, indium aluminum arsenic layer, strained indium gallium phosphide layer, indium gallium arsenic layer; wherein, the ninth layer of indium gallium arsenic epitaxial layer is used as a cap layer, and the eighth layer of strained indium gallium phosphide epitaxial layer is used as a depletion type The barrier layer, the seventh layer of InAlAs epitaxial layer is used as an enhanced barrier layer, the fifth layer of InAlAs epitaxial layer is used as an isolation layer, and the fourth layer of InGaAs is used as a channel layer.

In the transistor material structure, the layers sequentially grown on the linear slowly changing InAlGaAs epitaxial layer are non-doped InAlAs layer, non-doped InGaAs layer, and non-doped InAlAs layer, planar doped layer, undoped InAlAs layer, undoped strained InGaP layer, heavily doped InGaAs layer.

In the transistor material structure, the ninth layer of InGaAs epitaxial layer is highly n-type doped, wherein the indium composition X=0.53±0.05, the aluminum composition Y=0.47±0.05, X+Y=1, The thickness is 100±10 angstroms, the doping is silicon doping, and the concentration is (1.0±0.1)×10 ¹⁹ cm ^-3 ; the barrier layer of the depletion-mode MHEMT is the eighth undoped strained InGaP epitaxial layer, Among them, the indium composition X=0.8±0.05, the aluminum composition Y=0.2±0.05, X+Y=1, and the thickness is 100±10 angstroms; the barrier layer of the enhanced MHEMT is the seventh layer of undoped AlGaAs epitaxy layer, wherein the indium composition X=0.52±0.05, the aluminum composition Y=0.48±0.05, X+Y=1, and the thickness is 100±10 angstroms; the planar doped layer is silicon-doped, and the doping concentration is designed to be (1.5 ±0.1)×10 ¹² cm ^-2 ; the channel layer is the fourth undoped InGaAs epitaxial layer, in which the indium composition X=0.53±0.05, the aluminum composition Y=0.47±0.05, X+Y=1 , with a thickness of 200±10 angstroms.

Compared with the existing typical single-chip integrated enhanced/depleted PHEMT material structure, the present invention has very obvious advantages, which are mainly reflected in the following four aspects:

1) High indium composition In _y Al _1-y -As (indium composition Y=0.52) has a larger bandgap width than Al _x Ga _1-x As (indium composition X=0.17), while high indium composition In _x Ga _1-x As (indium composition Y=0.53) has a smaller band gap than low indium composition In _y Ga _1-y As (indium composition X=0.2), so In _y Al _1- The conduction band difference between _y As/In _x Ga _1-x As heterojunction is larger. The conduction band difference between In _y Al _1-y As/In _x Ga _1-x As is about 0.47eV, which is worse than that of typical PHEMT material structure Aly _{Ga 1-y} As/In _x Ga _1-x As 0.27eV is much larger. In this way, a higher potential barrier is formed between In _y Al _1-y As/In _x Ga _1-x As, so that the 2DEG is better bound in the In _x Ga _1-x As channel layer.

2) The high indium composition strained In _0.8 Ga _0.2 P epitaxial layer instead of the AlGaAs epitaxial layer is used as the depletion barrier layer. InGaP has two advantages as the barrier layer of depletion-type MHEMT: a) InGaP/InAlAs has a high corrosion selectivity ratio for certain etching solutions, and it can be used as both a depletion-type barrier layer and an etch stop layer, which has a dual role; b) it has no deep energy level generation (such as DX center) and has a low surface potential;

3) Compared with the material structure of typical PHEMT devices, since the InGaP epitaxial layer has dual functions, there is no need to design an etching stop layer, which reduces the difficulty of material growth and is conducive to improving the quality of material growth.

4) Since the In _0.3 Ga _0.47 As epitaxial layer is used as the cap layer, its low forbidden band and high doping rate characteristics enable the device to form a good ohmic contact.

Description of drawings

Figure 1: Schematic diagram of the structure of the enhancement/depletion MHEMT device of the present invention;

Fig. 2: the curve diagram of the simulated DC transconductance characteristic of the enhanced MHEMT device of the present invention;

Fig. 3: A graph showing the simulated DC transconductance characteristic curve of the depletion-type MHEMT device of the present invention.

Detailed ways

An indium gallium phosphide enhancement/depletion type strained high electron mobility transistor material structure, as shown in Table 2, which adopts the material structure of indium gallium arsenic/indium gallium phosphide/indium aluminum arsenic/indium gallium arsenic On the gallium substrate material, the second layer of linearly-graded InAlGaAs epitaxial layer is grown by the slow-change growth technology as a buffer layer with a thickness of 1.5 μm, and then sequentially grown on the buffer layer: the third layer is not doped with InAlGaAs layer, the thickness is 200 angstroms; the fourth layer is not doped indium gallium arsenic layer, wherein the indium composition X=0.53±0.05, the aluminum composition Y=0.47±0.05, X+Y=1, and the thickness is 200±10 angstroms; The fifth layer is not doped with indium aluminum arsenic layer, with a thickness of 40 angstroms; the sixth layer is doped with silicon, and the concentration is designed to be (1.5±0.1)×10 ¹² cm ^-2 ; the seventh layer is not doped The indium aluminum arsenic layer, wherein the indium composition X=0.52±0.05, the aluminum composition Y=0.48±0.05, X+Y=1, and the thickness is 100±10 angstroms; the eighth layer is not doped with a strained indium gallium phosphide layer, wherein Indium composition X=0.8±0.05, gallium composition Y=0.2±0.05, X+Y=1, the thickness selection of the strained indium gallium phosphide epitaxial layer considers the In _0.86 Ga _0.2 As and the ninth layer In _0.53 Ga _0.47 As epitaxy There is about 1.4% lattice mismatch between the layer and the seventh layer of In _0.52 Al _0.48 As epitaxial layer, and the design thickness is 100±10 angstroms, which is less than its strained thickness; the ninth layer is heavily doped indium gallium arsenic layer, which is n Type high doping, wherein the indium composition X=0.53±0.05, the aluminum composition Y=0.47±0.05, X+Y=1, the thickness is 100±10 angstroms, the doping is silicon doping, and the concentration is (1.0±0.1 )×10 ¹⁹ cm ^-3 ; wherein, the ninth layer of InGaAs epitaxial layer is used as a cap layer, the eighth layer of strained InGaP epitaxial layer is used as a depletion barrier layer, and the seventh layer of InGaAs epitaxial layer is used as an enhancement type barrier layer, the fifth layer of InAlAs epitaxial layer is used as the isolation layer, and the fourth layer of InGaAs is used as the channel layer.

Table 2: Schematic diagram of the GaAs-based monolithic integrated enhancement/depletion mode MHEMT material structure of the present invention. serial number Material The molar ratio of% Thickness (angstroms) doping concentration 9 Heavily doped In _x Ga _1-x As 0.53 100 Angstroms Doping source (Si) 1.0E+19cm-3 8 Undoped In _x Ga _1-x P 0.8 100 Angstroms 7 Undoped In _x Al _1-x As 0.52 100 Angstroms 6 planar doping Si 1.5E+12cm-2 5 Undoped In _x Al _1-x As 0.52 40 Angstroms 4 Undoped In _x Ga _1-x As 0.53 200 Angstroms 3 Undoped In _x Al _1-x As 0.52 500 Angstroms 2 Linear Gradient Growth of i-InAlGaAs 1.5μm 1 Semi-insulating substrate GaAs(100)

According to the transistor material structure of the present invention, theoretical calculation and analysis are carried out on the relationship between the epitaxial layer thickness, doping concentration, Schottky barrier height of the material structure and the threshold voltage of the transistor, and the DC characteristics of the material structure are simulated. The theoretical calculation of the device threshold voltage is as follows: $V_T=\mathrm{\&phi;B}-\mathrm{\&Delta;Ec}-\frac{\mathrm{wxya}}{\mathrm{\&epsiv;}},$ V _T is the threshold voltage of the device, φB is the Schottky barrier height, ΔEc is the conduction band difference of the heterojunction, q is the electron charge, d is the thickness from the barrier layer to the plane doped layer, Ns is the plane doping concentration, ε is the dielectric constant. The parameters related to the material structure and the theoretically calculated threshold voltage are shown in Table 3.

Table 3: Schematic table for calculation of relevant parameters and threshold voltage of the material structure of the present invention. Material structure related parameters Enhanced Depletion type Plane doping concentration Ns Si 1.5E+12cm-2 Si 1.5E+12cm-2 barrier layer epitaxial layer InAlAs InGaP Schottky barrier height φB 0.75～0.8eV 0.6～0.65eV Thickness d 100 Angstroms 200 Angstroms Dielectric constant ε 12.2 11.9 Threshold voltage _VT 0.05～0.1V -0.45～-0.6V

In order to further verify the feasibility of the material structure of the present invention, the heterojunction device material structure simulation software was used to simulate the energy band relationship of the heterojunction, combined with the device geometry parameters (gate length, gate width, distance from the bottom of the gate to the 2DEG layer) and The setting of process parameters (contact resistance, metal-semiconductor junction barrier height) simulates the DC transconductance characteristics of the device. Fig. 1 is a schematic diagram of a material structure enhancement/depletion MHEMT device of the present invention. In the device characteristic simulation, set the enhancement/depletion type MHEMT device gate length L=1.0μm, gate width W=100μm, source-drain spacing is 5.0μm, metal-semiconductor structure barrier height is 0.65eV, contact resistance is 2.5Ω .mm, the simulated enhanced/depleted DC transconductance characteristic curves are shown in Figure 2 and Figure 3. The simulation results show that the enhanced threshold voltage is 0V, and its maximum transconductance is 300mS/mm; the depletion threshold voltage is -0.5V, and its maximum transconductance is 250mS/mm.

Claims (3)

1. An indium gallium phosphide enhancement/depletion type strained high electron mobility transistor material structure, characterized in that the material structure of indium gallium phosphide/indium aluminum arsenic/indium gallium arsenide is used on a semi-insulating gallium arsenide substrate material , using the slow-change growth technology to grow a linear slow-change InAlGaAs epitaxial layer as a buffer layer, and then sequentially grow on the buffer layer: InAlAs layer, InGaAs layer, InAlAs layer, planar doped layer, InAlAs Arsenic layer, strained InGaP layer, and InGaAs layer; wherein, the ninth layer of InGaAs epitaxial layer is used as a cap layer, the eighth layer of strained InGaP layer is used as a depletion barrier layer, and the seventh layer The indium aluminum arsenic epitaxial layer is used as an enhanced barrier layer, the fifth indium aluminum arsenic epitaxial layer is used as an isolation layer, and the fourth indium gallium arsenic layer is used as a channel layer. 2. The transistor material structure according to claim 1, characterized in that the layers sequentially grown on the linear graded InAlGaAs epitaxial layer are undoped InAlAs layers, undoped InGaAs Arsenic layer, undoped InAlAs layer, planar doped layer, undoped InAlAs layer, undoped strained InGaP layer, heavily doped InGaAs layer. 3. The transistor material structure according to claim 1 or 2, characterized in that the ninth layer of InGaAs epitaxial layer is highly n-type doped, wherein the indium composition X=0.53±0.05, the aluminum composition Y =0.47±0.05, X+Y=1, the thickness is 100±10 Angstroms, the doping is silicon-doped, and the concentration is (1.0±0.1)×10 ¹⁹ cm ^-3 ; the barrier layer of the depletion-type MHEMT is the eighth Layer undoped strained InGaP epitaxial layer, wherein the indium composition X=0.8±0.05, the aluminum composition Y=0.2±0.05, X+Y=1, and the thickness is 100±10 angstroms; the barrier layer of the enhanced MHEMT It is the seventh undoped AlGaAs epitaxial layer, wherein the indium composition X=0.52±0.05, the aluminum composition Y=0.48±0.05, X+Y=1, and the thickness is 100±10 angstroms; the planar doped layer is Silicon doping, the doping concentration is designed to be (1.5±0.1)×10 ¹² cm ^-2 ; the channel layer is the fourth undoped InGaAs epitaxial layer, where the indium composition X=0.53±0.05, the aluminum composition Y=0.47±0.05, X+Y=1, and the thickness is 200±10 angstroms.

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