CN1901615A - Means for generating a pixel clock locked to an input frame rate - Google Patents
Means for generating a pixel clock locked to an input frame rate Download PDFInfo
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Abstract
一种用于产生一被锁定到一视频信号的输入帧速率的像素时钟的装置，其包括一锁相环、一∑－Δ调制器(sigma－delta modulator)和一帧速率/像素比率产生器。所述帧速率/像素比率产生器经耦接以产生一参考时钟信号、一帧速率信号和一像素分辨率信号。使用这些输入信号，所述帧速率/像素比率产生器产生一表示显示像素时钟与参考时钟的比率的信号。将所述帧速率/像素比率产生器的输出耦接到所述∑－Δ调制器和所述锁相环，并对所述∑－Δ调制器和所述锁相环进行控制。相应地，所述锁相环产生并输出一稳定的并被锁定到所述帧速率的时钟信号。
A device for generating a pixel clock locked to an input frame rate of a video signal includes a phase-locked loop, a sigma-delta modulator, and a frame rate/pixel ratio generator. The frame rate/pixel ratio generator is coupled to generate a reference clock signal, a frame rate signal, and a pixel resolution signal. Using these input signals, the frame rate/pixel ratio generator generates a signal representing the ratio of the display pixel clock to the reference clock. The output of the frame rate/pixel ratio generator is coupled to the sigma-delta modulator and the phase-locked loop, and the sigma-delta modulator and the phase-locked loop are controlled. Accordingly, the phase-locked loop generates and outputs a stable clock signal that is locked to the frame rate.
Description
The cross reference of related application
The application's case is advocated the U.S. Provisional Patent Application case the 60/588th that is entitled as " SYSTEM AND METHOD FOR USEIN VIDEO PROCESSING INCLUDING A PROGRAMMABLE INPUT DEVICE; A PIXELCLOCK GENERATOR AND A DUAL SCALER ARCHITECTURE " of application on July 16th, 2004, No. 647 priority under 35 U.S.C. § 119 (e), described application case all is incorporated herein by reference.
Technical field
The present invention relates to the processing of video data.More particularly, the present invention relates to the Generation of Clock Signal in video data is handled, used by other assembly.More particularly, the present invention relates to one with the generation of the synchronous pixel clock of described input frame speed.
Background technology
In field of video processing, some signals are used to deal with data.For example, described frame rate is the frame of per second institute's projection or demonstration or the number of image.No matter frame rate is the isochronous audio and the picture of film, TV or video if being used for.The frame rate of 24,25 and 30 frames of per second is comparatively common.In computer video stream, described frame rate is described the playback rate of AVI and QuickTime film.The described video playback speed of one AVI and QuickTime film is directly relevant with the fluency of being felt of its broadcast.The actual frame rate of a plurality of factor affecting one computers, and modern PC is not having under the situation of acceleration per second only can play 10-15 frame.
In graphic process unit, also there are the various clock signals that are used for processing video data.Described signal comprises that one is used for department of computer science unify system clock, a reference clock and a pixel clock as the reference of other video clock signal and operation of graphic process unit, its horizontal line with video is divided into pixel makes that the frequency of described pixel clock is high more, and the pixel that will occur on display is many more.
One of major function of graphics process is for to convert an incoming video signal with a special frames speed and resolution to an outputting video signal with different frame rates and video resolution.When being the integral multiple of described input frame speed, described frame rate of display will can not go wrong.Yet this generally the time when not being in, frame inserts or frame deletion causes motion artifacts with the mismatch of compensation along with the time.
Prior art has attempted to solve this problem by described frame rate is locked onto described input clock.If described demonstration has the resolution identical with input, can finish frame lock by using described input clock or a plurality of input clock so.Yet, if described input clock instability uses described input clock problematic so.Particularly, any shake will propagate into display.Equally, when described display resolution was different from described input resolution, using clock was not unique selection.
Therefore, needed is a kind of method and system of pixel clock that is locked into the input frame speed of a vision signal that is used to produce.
Summary of the invention
The invention provides one and be used to produce one or more embodiment of device of pixel clock that are locked into the input frame speed of a vision signal.In one embodiment, the present invention includes a phase-locked loop, a sigma-delta modulator and one frame rate/pixel rate generator.Described frame rate/pixel rate generator is through coupling to produce a reference clock signal, a frame rate signal and a pixel resolution signal.Use these input signals, described frame rate/pixel rate generator produces the signal of the ratio of an expression display pixel clock and reference clock.The output of described frame rate/pixel rate generator is couple to the input of described sigma-delta modulator.Another input of described sigma-delta modulator is couple to the output of described phase-locked loop.Couple described phase-locked loop to receive the output of a reference clock and described sigma-delta modulator.Correspondingly, described phase-locked loop produces and exports a clock signal stable and that be locked into described frame rate.Such as in the following detailed description announcement, the present invention also comprises a kind of method of pixel clock that is locked into the input frame speed of a vision signal that is used to produce.
The present invention also comprises a kind of method of pixel clock that is locked into the input frame speed of a vision signal that is used to produce.Described method preferably comprises following steps: 1) use a reference clock to measure an input perpendicular separation (vertical interval); 2) ratio of calculating display pixel clock and reference clock; 3) ask the mean value of a plurality of perpendicular separations to quantize caused error by shake and sampling with cancellation; 4) use described mean value to control a sigma-delta oscillator and a phase-locked loop.
Description of drawings
Fig. 1 is that one first embodiment according to the present invention illustrates that one is used to produce a simplified block diagram of device that is locked into the pixel clock of input frame speed.
Fig. 2 is the block diagram that first embodiment according to the present invention illustrates described frame rate/pixel rate generator.
Fig. 3 is that one second embodiment according to the present invention is used to produce a block diagram of device that is locked into the pixel clock of described input frame speed.
Embodiment
The present invention is directed to a kind of method and system of pixel clock that is locked into the input frame speed of a vision signal that is used to produce.The present invention is especially favourable, because it utilizes a high stable reference clock that produces a clock and a sigma-delta phase-locked loop such as crystal to think that the input frame speed coupling produces display pixel clock.As shown in Figure 1, one first embodiment of device 100 comprises a phase-locked loop 102, a sigma-delta modulator 104 and one frame rate/pixel rate generator 106.
Described phase-locked loop 102 has one first input, one second input and an output.Described phase-locked loop 102 is a general type, and is one to have one and constantly regulated with the electronic circuit with the oscillator of (and the therefore locked) frequency input signal that is complementary.Described phase-locked loop 102 produces one and has more low noise and the more signal of high stability.Described phase-locked loop 102 is preferably an analog PLL.In an alternate embodiment, described phase-locked loop 102 is the part of an integrated circuit.First input of described phase-locked loop 102 preferably is couple to holding wire 110 to receive a reference clock signal.For example, described reference clock signal can be a high stable reference clock, as the known crystal clocking of those skilled in the art.Second input of described phase-locked loop 102 is couple to the output of sigma-delta modulator 104 with the feedback signal on the received signal line 118.Described phase-locked loop 102 also has one and is couple to the output of described sigma-delta modulator 104 by holding wire 116.The output of described phase-locked loop 102 is couple to holding wire 120 so that the described pixel clock that is locked into described input frame speed to be provided.
Described sigma-delta modulator 104 has one first input, one second input and an output.Described sigma-delta modulator 104 is operating as an oscillator.The output of described sigma-delta modulator 104 is provided on the holding wire 118 as an input to described phase-locked loop 102.First input of described sigma-delta modulator 104 is couple to holding wire 112 to receive the output of described frame rate/pixel rate generator 106.Another input of described sigma-delta modulator 104 is couple to holding wire 116 to receive a load divider signal.
Described frame rate/pixel rate generator 106 is couple to line 110 to receive a reference clock signal, is couple to line 124 receiving a frame rate signal, and is couple to line 122 to receive a pixel resolution signal.Use these input signals, described frame rate/pixel rate generator 106 produces the signal of the ratio of an expression display pixel clock and reference clock.The output of described frame rate/pixel rate generator 106 is couple to holding wire 112 and it is provided to described sigma-delta modulator 104 as input.
Referring now to Fig. 2,, shows frame rate/pixel rate generator 106 in greater detail.In first embodiment, described frame rate/pixel rate generator 106 further comprises a counter 202 and a multiplier 204.The clock that preferably will be input to described counter 202 is couple to holding wire 110 to receive described reference clock signal.Therefore, described counter 202 every experience its reference clock signals of one-period increase progressively.The input that resets of described counter 202 is couple to holding wire 124 to receive described frame rate signal.For example, described frame rate signal is conventional VSYNC signal, and it is provided to a vision signal is divided into frame.Whenever described frame rate signal is determined, counter 202 resets and begins up to next frame.This has guaranteed that the arbitrary signal by 106 outputs of frame rate/pixel rate generator will be many times of reference clock signal, and with the beginning of described frame or finish synchronously.The output of described counter 202 is couple to the input of described multiplier 204.Another input of described multiplier 204 is couple to line 122 to receive a pixel resolution signal.Pixel resolution signal among embodiment preferably includes the indication of the pixel wide and the pixels tall of described video data.Described multiplier 204 is preferably determined described ratio by the number of reference clock in use indication one frame and with its output divided by the counter 202 of display width and demonstration height.Then, described value or ratio are exported on holding wire 112 by multiplier 204 and in order to control described sigma-delta modulator 104 and described phase-locked loop 102.
Referring now to Fig. 3,, shown to be used to produce one second embodiment of device 300 of pixel clock that is locked into the input frame speed of a vision signal.For understand easily and convenient for the purpose of, for assembly like the above component class of having described, use similar terms and reference number among Fig. 3.As shown in Figure 3, second embodiment of described device 300 preferably comprises: a phase-locked loop 102, a sigma-delta modulator 104, a counter 302, clock multiplication calculator (clock multiplier calculator) 304, one average filter 306 and a frequency limitation controller 308.
More than describe a phase-locked loop 102 and a sigma-delta modulator 104 in detail referring to Fig. 1.For second embodiment of Fig. 3, it has similar coupling and function, so no longer be repeated in this description at this.
Described counter 302 is a general type, and in order to produce a reference clock count signal.The number of the reference clock cycle in this signal indication one frame.The clock input of described counter 302 is couple to holding wire 110 to receive described reference clock signal.Therefore, described counter 302 every experience its reference clock signals of one-period increase progressively once.The input that resets of described counter 302 is couple to a holding wire 310 to receive described frame rate signal.For example, described frame rate signal is conventional VSYNC signal, and it is provided to a vision signal is divided into frame.Whenever described VSYNC signal is determined, counter 302 resets and begins up to next frame.Described counter 302 is output as described reference clock count signal.
Described multiplied clock calculator 304 has a plurality of inputs and an output.The clock input of described multiplied clock calculator 304 is couple to holding wire 110 to receive described reference clock signal.First data input of described multiplied clock calculator 304 is couple to the output of counter 302 to receive the reference clock count signal.Two residue inputs of described multiplied clock calculator 304 are coupled to receive a demonstration altitude signal and a display width signal.In an one exemplary embodiment, described demonstration height and display width signal are produced by the configuration register (not shown).The described known parameters that shows that height and display width are user-programmable in the configuration register of described device.The described multiplied clock calculator 304 preferred clock multiplication signals (clock multiplication signal) that produce.The ratio of described multiplied clock signal indication display pixel clock and reference clock.In an one exemplary embodiment, described multiplied clock signal equals described reference clock count signal divided by described display pixel width and described display pixel height.The load input of described multiplied clock calculator 304 is couple to holding wire 310 to receive described VSYNC signal, makes the value of described counter 302 be written into described multiplied clock calculator 304 at each frame end place.At each reference clock signal place, described multiplied clock calculator 304 output reference clock count signals are divided by the value of the display pixel width and the display pixel height of present load.Multiplied clock calculator 304 is output as described multiplied clock signal.
Average filter 306 has one and is couple to the output of described multiplied clock calculator 304 to receive the input of described multiplied clock signal.The value of described average filter 306 n past frames of storage (past frame), and it is averaged together to produce the multiplied clock signal once filtering.In one embodiment, described average filter 306 comprises the circular buffer of n multiplied clock signal value of a storage, and one in the described value is used for each past frame.In one embodiment, the value of last four frames is averaged.In another embodiment, the value of 40 past frames is averaged.The present invention advantageously asks the mean value of the value of the multiplied clock signal on a plurality of frames to quantize caused error to guarantee its stability and cancellation by shake and sampling.The clock input of described average filter 306 is couple to reference clock signal, makes to produce the described mean value of signal in the past according to each reference clock signal.The load coupled that is input to average filter 306 is arrived line 310 to receive VSYNC.This is at described frame end place's load one clock multiplication signal.In an one exemplary embodiment, described average filter 306 can comprise that a circular buffer loads to the next position in the described circular buffer with the new value with the multiplied clock signal at described frame end place.The output of average filter 306 provides the multiplied clock signal through filtering.
Frequency limitation controller 308 has a plurality of inputs and an output.Described frequency limitation controller 308 is in order to the value through the multiplied clock signal of filtering output on the limiting signal line 112 and that send to sigma-delta modulator 104.The present invention uses the minimum and the maximum multiplication value that are input to described frequency limitation controller 308 advantageously to limit described read clock variation under the situation that does not have stabilization signal.Described frequency limitation controller 308 have one be couple to average filter 306 output first the input.The second and the 3rd input of described frequency limitation controller 308 is coupled to receive a maximum multiplication signal and a minimum multiplication signal respectively.These similar signals of height and width that show can be stored in the configuration register (not shown).Value in the described minimum and maximum doubling register is limited in the described digital dock multiplier signal that outputs to sigma-delta modulator 104 on the holding wire 112.The clock input of described frequency limitation controller 308 is couple to holding wire 110 to receive described reference clock signal.
The present invention also comprises a kind of method of pixel clock that is locked into the input frame speed of a vision signal that is used to produce.Described method preferably comprises following steps:
1) use described reference clock to measure described input perpendicular separation to produce a reference clock counting as the some reference clock vibrations between the frame.
2) use following formula to calculate the ratio of display pixel clock and reference clock: multiplied clock=reference clock counting ÷ display width+demonstration height.Described height and the display width of showing is the known parameters that is programmed in the configuration register of described device.
3) ask the mean value of the ratio of a plurality of perpendicular separations to quantize caused error by shake and sampling to guarantee its stability and cancellation.
4) under the situation that does not have stabilization signal, ratio that described warp is average or read clock change the value that is restricted to from minimum and maximum register, thereby limit described digital dock multiplier.
5) with described average ratio (it is the high-precision numeral of an expression obatained score) through restriction with accomplishing the input of a sigma-delta oscillator and simulaed phase locked loop, to produce a pixel clock that is locked into the described input frame speed of a vision signal.
Although described the present invention with reference to some preferred embodiment, those skilled in the art will realize that to provide various modifications.For example, principle of the present invention is extensible and be applied to other clock system.The invention provides variation and modification to described preferred embodiment.
Claims (20)
1. one kind is used to produce a device of pixel clock signal that is locked into the input frame speed of a vision signal, and described device comprises:
One has the ratio generator of one first input, one second input and an output, described ratio generator is used to produce the rate signal of the ratio of expression one display pixel clock and a reference clock, described first input is through coupling to receive a reference clock signal, and described second input of described ratio generator is through coupling to receive a pixel resolution signal;
One has one first input, one second input and is used to produce the phase-locked loop of the output of described pixel clock signal, and described first input of described phase-locked loop is through coupling to receive described reference clock signal; With
One has the modulator of one first input, one second input and an output, described first input of described modulator is couple to the described output of described ratio generator, described second input of described modulator is couple to phase-locked loop, and the described output of described modulator is couple to described second input of described phase-locked loop.
2. device according to claim 1, wherein said phase-locked loop are an analog circuit.
3. device according to claim 1, wherein said modulator are a sigma-delta modulator (sigma-delta modulator).
4. device according to claim 1, wherein said modulator operation are an oscillator.
5. device according to claim 1, wherein said ratio generator has one the 3rd input, described the 3rd input of described ratio generator is through coupling receiving a frame rate signal, and wherein said frame rate signal, described reference clock signal and described pixel resolution signal are in order to the rate signal of the described ratio that produces described display pixel clock of described expression and described reference clock.
6. device according to claim 1, wherein said ratio generator further comprises a counter of signal that is used for producing some reference clocks of an expression one frame, and described counter is through coupling to receive described reference clock signal and described frame rate signal.
7. device according to claim 6, wherein said frame rate signal are a VSYNC signal.
8. device according to claim 6, wherein said ratio generator further comprises a multiplier that is used to produce described rate signal, and described multiplier has one and is couple to first input of described counter and once coupling to receive second input of described pixel resolution signal.
9. device according to claim 6, wherein said pixel resolution signal comprise that a display width signal and shows altitude signal, and the described reference count of described rate signal for being removed by described display width and demonstration altitude signal.
10. device according to claim 1, it further comprises one and has an input and an average filter of exporting that is used to store a plurality of rate signal values, the described input of described average filter is couple to the described output of described ratio generator, and the described output of described average filter is couple to the described input of described modulator.
11. device according to claim 10, wherein said average filter are stored the rate signal value of four previous frames and are asked the mean value of described rate signal value.
12. device according to claim 10, wherein said average filter comprises a circular buffer.
13. device according to claim 1, it further comprises one and has the frequency limitation controller that one first input, one second input and are used to limit the output of described rate signal value, described first input of described frequency limitation controller is couple to the described output of described ratio generator, described second input of described frequency limitation controller is through coupling to receive a maximum and minimum multiplication value, and the described output of described frequency limitation controller is couple to the described input of described modulator.
14. one kind is used to produce a method of pixel clock that is locked into the described input frame speed of a vision signal, described method comprises:
Use a reference clock to measure an input perpendicular separation to produce reference clock counting;
Use the ratio of described reference clock counting and a display resolution calculated signals display pixel clock and reference clock; With
With described ratio as an input to control a modulator and a loop mutually, to produce a pixel clock.
15. method according to claim 14, wherein said reference clock counting are some reference clock vibrations of an image duration.
16. method according to claim 14 wherein shows highly divided by one by described reference clock counting and a display width is carried out the described ratio of calculating.
17. method according to claim 14, wherein said ratio are the high accuracy number of an expression one obatained score.
18. method according to claim 14, wherein said modulator are one ∑-Δ oscillator, and described phase-locked loop is an analog circuit.
19. method according to claim 14, it further is included under the situation that does not have a stabilization signal, and described ratio is restricted to a scope between a maximum and a minimum value.
20. method according to claim 14, it further comprises the mean value of asking two or more perpendicular separations, quantizes caused error to guarantee its stability and cancellation by shake and sampling.
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| CN 200510085441 CN1901615A (en) | 2005-07-18 | 2005-07-18 | Means for generating a pixel clock locked to an input frame rate |
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| CN 200510085441 CN1901615A (en) | 2005-07-18 | 2005-07-18 | Means for generating a pixel clock locked to an input frame rate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113132553A (en) * | 2020-01-16 | 2021-07-16 | 京东方科技集团股份有限公司 | Novel source end synchronous display method and device |
| CN113825003A (en) * | 2020-06-18 | 2021-12-21 | 杜尔利塔斯有限公司 | Frame rate synchronization |
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2005
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113132553A (en) * | 2020-01-16 | 2021-07-16 | 京东方科技集团股份有限公司 | Novel source end synchronous display method and device |
| CN113132553B (en) * | 2020-01-16 | 2022-07-29 | 京东方科技集团股份有限公司 | Novel source end synchronous display method and device |
| US11758097B2 (en) | 2020-01-16 | 2023-09-12 | Boe Technology Group Co., Ltd. | Method and apparatus for transmitting video signals, and display device |
| US12069414B2 (en) | 2020-01-16 | 2024-08-20 | Boe Technology Group Co., Ltd. | Method and apparatus for transmitting video signals, and display device |
| CN113825003A (en) * | 2020-06-18 | 2021-12-21 | 杜尔利塔斯有限公司 | Frame rate synchronization |
| CN113825003B (en) * | 2020-06-18 | 2024-02-13 | 杜尔利塔斯有限公司 | Frame rate synchronized display system, display and method of displaying video stream receiving frames |
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