CN1900781B - Liquid crystal display - Google Patents

Abstract

The present invention provides a liquid crystal display, comprising: a substrate; a pixel electrode arranged on the substrate and including a first sub-pixel electrode and a second sub-pixel electrode; and a common electrode facing the pixel electrode, wherein the first sub-pixel electrode has a For curved edges that are substantially parallel to each other, the second subpixel electrode has a pair of curved edges that are substantially parallel to each other, and the height of the second subpixel electrode is greater than the height of the first subpixel electrode, and the first and second subpixels The convexity and concavity of the curved edges of the electrodes are alternately reversed relative to each other in the height direction.

Description

LCD Monitor

technical field

The present disclosure relates to a liquid crystal display.

Background technique

A liquid crystal display (LCD) is one of the most widely used flat panel display devices. The LCD includes a pair of panels including field generating electrodes such as pixel electrodes and a common electrode and a liquid crystal (LC) layer interposed between the pair of panels. The LCD generates an electric field in the LC layer by applying a voltage to the electrodes, and determines the orientation of the LC molecules and the polarization of the light incident on the LC layer by controlling the intensity of the electric field, so as to change the transmittance of the light incident on the LC layer, thereby obtaining the desired desired image.

The LCD also includes switching elements connected to the pixel electrodes, and signal lines, such as gate lines and data lines, to apply signals to the switching elements and thus voltages to the pixel electrodes.

Among these LCDs, a vertical alignment (VA) mode LCD is attracting attention because of its high contrast ratio and wide reference viewing angle. The VA mode LCD positions LC molecules so that the long axis of the LC molecules is perpendicular to the panel when there is no electric field. The reference viewing angle refers to the viewing angle at which the contrast ratio is 1:10 or the brightness order of the grayscale starts to reverse.

A wide viewing angle of the VA mode LCD can be realized by cutouts in the field generating electrodes and protrusions on or under the field generating electrodes. Since the notches and protrusions can determine the tilt directions of the LC molecules, the tilt directions can be spread into several directions by using the notches and protrusions, thereby widening the reference viewing angle.

However, the protrusions and cutouts block the transmission of incident light, and thus, the transmittance of light decreases as the number of protrusions or cutouts increases. In order to increase the transmittance of light, it is proposed to increase the area of the pixel electrode. However, the proposed structure brings adjacent pixel electrodes close together, and brings the pixel electrode and its adjacent data line close together, so that a strong lateral electric field is generated near the edge of the pixel electrode. The transverse electric field disturbs the orientation of the LC molecules, creating visible texture and light leakage within the image.

In addition, the VA mode LCD has weak side visibility compared to front visibility. For example, in a conventional LCD equipped with a cutout, the image becomes brighter toward the sides of the LCD, and in severe cases, the difference in brightness between high grayscales disappears, thereby making the entire image dark.

To improve side visibility, a pixel is split into two sub-pixels that are capacitively coupled to each other. One of the two subpixels is supplied with a voltage directly, while the other is subjected to a voltage drop through capacitive coupling, so that the two subpixels have different voltages, resulting in different light transmittances.

Contents of the invention

A liquid crystal display according to an embodiment of the present invention includes: a first substrate; a second substrate; a plurality of first signal lines formed on the first substrate; a plurality of second signal lines formed on the first substrate; A first subpixel electrode on the substrate and having a curved edge; a second subpixel electrode formed on the first substrate, the second subpixel electrode has a curved edge, and is arranged adjacent to the first subpixel electrode in a first direction; formed The third sub-pixel electrode on the first substrate, the third sub-pixel electrode has a curved edge, and is arranged adjacent to the second sub-pixel electrode in the second direction; the fourth sub-pixel electrode formed on the first substrate, the fourth The sub-pixel electrode has curved edges and is arranged adjacent to the third sub-pixel electrode in the first direction and adjacent to the first sub-pixel electrode in the second direction; a common electrode formed on the second substrate facing the first to fourth a sub-pixel electrode; and a plurality of switching elements, each of which is coupled to one of the first signal lines, one of the second signal lines, and one of the first to fourth sub-pixel electrodes, wherein the second sub-pixel electrode The curved edge is longer than the curved edge of the first sub-pixel electrode, the curved edge of the fourth sub-pixel electrode is longer than the curved edge of the third sub-pixel electrode, and the fourth sub-pixel electrode has an edge adjacent to the edge of the second sub-pixel electrode. edge.

The lengths in the first direction of the first to fourth subpixel electrodes may be substantially equal to each other, and the length of the curved edge of each of the second and fourth subpixel electrodes may be approximately the same as that of the curved edge of each of the first and third subpixel electrodes. twice the length.

The liquid crystal display may further include a tilt direction determining part formed on the common electrode. The tilt direction determining part may include a cutout having a curved portion passing through one of the first to fourth subpixel electrodes and extending substantially parallel to a curved edge of the one of the first to fourth subpixel electrodes. A distance between a curved portion of the cutout and a curved edge of one of the first to fourth subpixel electrodes may be approximately equal to 20-35 μm.

Different voltages obtained from a single image information may be supplied to the first sub-pixel electrode and the second or fourth sub-pixel electrode.

The switch element may include a first thin film transistor coupled to the first sub-pixel electrode and a second thin film transistor coupled to the second or fourth sub-pixel electrode, and the first and second thin film transistors may be connected to two different first signal line and a single second signal line.

The first and second thin film transistors may be turned on in response to signals from two different first signal lines to transmit a signal from a single second signal line, or may be turned on in response to a signal from a single second signal line In order to transmit signals from two different first signal lines.

A liquid crystal display according to an embodiment of the present invention includes: a substrate; a pixel electrode arranged on the substrate and including a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of Curved edges substantially parallel to each other, the second sub-pixel electrode has a pair of curved edges substantially parallel to each other, and the height of the second sub-pixel electrode is greater than that of the first sub-pixel electrode.

The first subpixel electrode and the second subpixel electrode may be adjacent in a length direction or a height direction. In the latter case, the convexity and concavity of the curved edges of the first and second subpixel electrodes may be reversed relative to each other.

The length of the first subpixel electrode may be substantially equal to the length of the second subpixel electrode, and the height of the second subpixel electrode may be about twice the height of the first subpixel electrode.

Each curved edge may have a curved point, and each of the first and second subpixel electrodes may be symmetrical about a straight line connecting the curved point.

Each pair of curved edges may include a concave edge and a convex edge.

A convex edge of the first subpixel electrode may be adjacent to a concave edge of the second subpixel electrode, or a concave edge of the first subpixel electrode may be adjacent to a convex edge of the second subpixel electrode. In addition, the end of the concave edge of the first subpixel electrode may be opposite to the end of the convex edge of the second subpixel electrode, and the end of the convex edge of the first subpixel electrode may be opposite to the end of the concave edge of the second subpixel electrode. .

The liquid crystal display may further include a tilt direction determining part formed on the common electrode. The tilt direction determining part may include a cutout having a bent portion passing through the first or second sub-pixel electrode and extending substantially parallel to a bent edge of the first or second sub-pixel electrode. A distance between the curved portion of the cutout and one of the curved edges of the first or second sub-pixel electrode adjacent to the curved portion may be approximately equal to 20-35 μm.

The first subpixel electrode and the second subpixel electrode may have different voltages, and the first subpixel electrode and the second subpixel electrode may be supplied with different voltages obtained from a single image information.

The liquid crystal display may further include: a first thin film transistor coupled to the first sub-pixel electrode; a second thin film transistor coupled to the second sub-pixel electrode; a first signal line coupled to the first thin film transistor; a second signal line of the thin film transistor; and a third signal line coupled to the first and second thin film transistors, and intersecting the first and second signal line.

In response to a signal from the first signal line, the first thin film transistor may be turned on to transmit a signal from the third signal line, and in response to a signal from the second signal line, the second thin film transistor may be turned on to transmit a signal from the third signal line. signal of. At this time, the first thin film transistor and the second thin film transistor may be arranged to face each other with respect to the third signal line.

In addition, in response to a signal from the third signal line, the first thin film transistor may be turned on to transmit a signal from the first signal line, and in response to a signal from the third signal line, the second thin film transistor may be turned on to transmit a signal from the second signal line. signal on the signal line.

The liquid crystal display may further include a fourth signal line extending along a straight line connecting bending points of curved edges of the first and second sub-pixel electrodes. Each of the first and second thin film transistors may include a drain electrode overlapping the fourth signal line.

The first subpixel electrode and the second subpixel electrode may be capacitively coupled to each other. The liquid crystal display may further include: a thin film transistor coupled to the first sub-pixel electrode; a first signal line coupled to the thin film transistor; and a second signal line coupled to the thin film transistor and crossing the first signal line.

Description of drawings

Embodiments of the present invention can be understood in more detail according to the following description in conjunction with the accompanying drawings, wherein:

1 is a block diagram of an LCD according to an exemplary embodiment of the present invention;

2 is an equivalent circuit diagram of a pixel of an LCD according to an exemplary embodiment of the present invention;

3-5 are layout views of pixel electrodes, common electrodes and color filters in an LC panel assembly according to an exemplary embodiment of the present invention;

Figure 6 is a plan view of a sub-pixel electrode showing the sub-pixel electrodes shown in Figures 3-5;

7 is an equivalent circuit diagram of signal lines and pixels according to an exemplary embodiment of the present invention;

8 is a layout view of a lower panel of an LC panel assembly according to an exemplary embodiment of the present invention;

9 is a layout view of an upper panel of an LC panel assembly according to an exemplary embodiment of the present invention;

10 is a layout view of an LC panel assembly including the lower panel shown in FIG. 8 and the upper panel shown in FIG. 9;

11 is a schematic cross-sectional view of the LC panel assembly shown in FIG. 10 along line XI-XI;

12 is another schematic cross-sectional view of the LC panel assembly shown in FIG. 10 along line XI-XI;

13 is a layout view of a lower panel of an LC panel assembly according to an exemplary embodiment of the present invention;

14 is a layout view of an upper panel of an LC panel assembly according to an exemplary embodiment of the present invention;

15 is a layout view of an LC panel assembly including the lower panel shown in FIG. 13 and the upper panel shown in FIG. 14;

Figure 16 is a cross-sectional view of the LC panel assembly shown in Figure 15 along the line XVI-XVI'-XVI";

17 is an equivalent circuit diagram of signal lines and pixels according to an exemplary embodiment of the present invention;

18 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention;

19 is an equivalent circuit diagram of signal lines and pixels according to an exemplary embodiment of the present invention;

20 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention;

Figure 21 is a cross-sectional view of the LC panel assembly shown in Figure 20 along line XXI-XXI;

22 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention;

FIG. 23 is a cross-sectional view of the LC panel assembly shown in FIG. 22 along line XXIII-XXIII.

Detailed ways

Embodiments of the invention will now be described more fully hereinafter with reference to the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

An LCD according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 .

FIG. 1 is a block diagram of an LCD according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the LCD according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an LCD according to an exemplary embodiment of the present invention includes an LC panel assembly 300, a gate driver 400 and a data driver 500 connected to the panel assembly 300, a grayscale voltage generator 800 connected to the data driver 500, and controlling the above-mentioned The signal controller 600 of the component.

Referring to FIG. 1, the panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected to the signal lines and arranged substantially in a matrix. In the structural diagram shown in FIG. 2, the panel assembly 300 includes a lower panel 100, an upper panel 200, and an LC layer 3 interposed therebetween.

The signal lines provided on the lower panel 100 include a plurality of gate lines (not shown) and a plurality of data lines (not shown). The gate lines transmit gate signals, also referred to as "scanning signals", and the data lines transmit data signals. The gate lines extend substantially in a row direction and are substantially parallel to each other, and the data lines extend substantially in a column direction and are substantially parallel to each other.

Referring to FIG. 2, each pixel PX includes a pair of sub-pixels, and each sub-pixel includes liquid crystal (LC) capacitors Clc1/Clc2. At least one of the two sub-pixels further includes a switching element (not shown) connected to the gate line, the data line and the LC capacitors Clc1/Clc2.

The LC capacitor Clc1/Clc2 includes sub-pixel electrodes PE1/PE2 provided on the lower panel 100 and a common electrode CE provided on the upper panel 200 as two terminals. The LC layer 3 arranged between the electrodes PE1/PE2 and CE serves as a dielectric of the LC capacitors Clc1/Clc2. A pair of subpixel electrodes PE1 and PE2 are separated from each other and form a pixel electrode PE. The common electrode CE is supplied with a common voltage Vcom, and covers the entire surface of the upper panel 200 . The LC layer 3 has negative dielectric anisotropy, and LC molecules within the LC layer 3 may be oriented such that long axes of the LC molecules are perpendicular to the surfaces of the panels 100 and 200 in the absence of an electric field.

For a color display, each pixel PX uniquely represents a primary color, that is, space division, or each pixel PX sequentially represents the primary colors, that is, time division, so that the space or time sum of the three primary colors is regarded as the desired color . An example of a set of primary colors includes red, green and blue. FIG. 2 shows an example of space division in which each pixel PX includes a color filter CF representing one of primary colors in a region of the upper panel 200 facing the pixel electrode PE. Alternatively, a color filter CF is provided on or under the sub-pixel electrode PE1 or PE2 on the lower panel 100 .

A pair of polarizers (not shown) are attached to the outer surfaces of the panels 100 and 200 . The polarization axes of the two polarizers may be crossed so that the crossed polarizers prevent light from being incident on the LC layer 3 . One polarizer can be omitted.

Detailed structures of pixel electrodes, common electrodes and color filters within the LC panel assembly will be described in detail with reference to FIGS. 3 , 4 , 5 and 6 .

3-5 are layout views of pixel electrodes, common electrodes and color filters in an LC panel assembly according to an exemplary embodiment of the present invention, and FIG. 6 is a sub-pixel representing the sub-pixel electrodes shown in FIGS. 3-5. The plan view of the electrode.

Referring to FIGS. 3-5, each pixel electrode 191 of the LC panel assembly according to an exemplary embodiment of the present invention includes a first sub-pixel electrode 191a and a second sub-pixel electrode 191b separated from each other, and the pixel electrodes are illustrated by dot-dash lines. surrounded. The subpixel electrodes 191a and 191b have cutouts 92a and 92b, respectively, and the common electrode CE (illustrated in FIG. 2) has a plurality of cutouts 71a and 71b facing the subpixel electrodes 191a and 191b, respectively. The red color filter 230R, the green color filter 230G, and the blue color filter 230B extend along the pixel electrodes 191 adjacent to each other in the column direction.

Both the first and second subpixel electrodes 191a and 191b forming the pixel electrode 191 may be coupled to respective switching elements (not shown). On the other hand, the first subpixel electrode 191a is coupled to a switching element (not shown), and the second subpixel electrode 191b is capacitively coupled to the first subpixel electrode 191a.

The subpixel electrodes 191a and 191b substantially have the same or similar shape, and the cutouts 71a and 71b of the common electrode CE also substantially have the same or similar shape. Figure 6 illustrates subpixel electrode 193 representing subpixel electrodes 191a and 191b shown in Figures 3-5 and cutouts 70 representing cutouts 71a and 71b shown in Figures 3-5.

As shown in FIG. 6, the subpixel electrode 193 has a pair of curved edges 193o1 and 193o2 and a pair of lateral edges 193t, and has a herringbone shape. Curved edges 193o1 and 193o2 include a convex edge 193o1 that intersects lateral edge 193t at an obtuse angle, such as about 135 degrees, and a concave edge 193o2 that meets lateral edge 193t at an acute angle, such as about 45 degrees. The curved edges 193o1 and 193o2 are bent at approximately right angles, and they are formed by a pair of inclined edges intersecting at 90 degrees. Each subpixel electrode 193 has a cutout 90 extending from the concave vertex CV on the concave edge 193o2 to the convex vertex VV on the convex edge 193o1, and reaching near the center of the subpixel electrode 193 .

The cutout 70 in the common electrode includes a curved portion 70o having a curved point CP, a central lateral portion 70t1 connected to the curved point CP of the curved portion 70o, and a pair of end lateral portions 70t2 connected to ends of the curved portion 70o. The curved portion 70o of the cutout 70 includes a pair of inclined portions intersecting at approximately right angles, extending substantially parallel to the curved edges 193o1 and 193o2 of the sub-pixel electrode 193, and bisects the sub-pixel electrode 193 into left and right halves. A central lateral portion 70t1 of the cutout 70 forms an obtuse angle with the bent portion 70o, for example, about 135 degrees, and extends toward the convex vertex VV of the sub-pixel electrode 193 . The end lateral portion 70t2 is aligned with the lateral edge 193t of the sub-pixel electrode 193 and forms an obtuse angle with the bent portion 70o, eg, about 135 degrees.

The subpixel electrode 193 is divided into four subregions S1, S2, S3 and S4 by the cutouts 70 and 90. Each sub-region S1-S4 has two main edges defined by the curved portion 70o of the cutout 70 and the curved edge 193o of the sub-pixel electrode 193. The distance between the main edges, ie the width of each sub-region S1-S4, may be equal to about 20-35 microns.

The subpixel electrode 193 and the cutout 70 have inversion symmetry with respect to an imaginary straight line called a center horizontal line, which connects the convex vertex VV and the concave vertex CV of the subpixel electrode 193 .

Referring to FIG. 6 , the length L of the lateral edge 193t of the subpixel electrode 193 is referred to as the length of the subpixel electrode 193 , and the distance H between the two lateral edges 193t of the subpixel electrode 193 is referred to as the height of the subpixel electrode 193 . In FIGS. 3-5, the length of the first subpixel electrode 191a is substantially equal to the length of the second subpixel electrode 191b, and the height of the second subpixel electrode 191b is about twice the height of the first subpixel electrode 191a. Therefore, the area of the second subpixel electrode 191b is about twice that of the first subpixel electrode 191a.

As shown in FIGS. 3-5, the first sub-pixel electrodes 191a and the second sub-pixel electrodes 191b are alternately arranged in the row direction and the column direction. However, the convexity and concavity of the subpixel electrodes 191a and 191b are fixed in the row direction, while the convexity and concavity of the subpixel electrodes 191a and 191b are alternately reversed in the column direction. For example, the upper row of the two rows shown in FIGS. 3-5 includes subpixel electrodes 191a and 191b with left convex edges and right concave edges, while the lower row of the two rows includes subpixel electrodes with left concave edges and right convex edges. Electrodes 191a and 191b. It is to be noted that the second subpixel electrodes 191b located in adjacent rows have contact edges or portions.

Regarding the arrangement of the sub-pixel electrodes 191a and 191b in the row direction, the central horizontal line of the first sub-pixel electrode 191a coincides with the central horizontal line of the second sub-pixel electrode 191b. In addition, the convex edge of the first subpixel electrode 191a is adjacent to the concave edge of the second subpixel electrode 191b, and the concave edge of the first subpixel electrode 191a is adjacent to the convex edge of the second subpixel electrode 191b. Regarding the arrangement in the column direction, the convex edge of the first subpixel electrode 191a is connected to the concave edge of the second subpixel electrode 191b, and the concave edge of the first subpixel electrode 191a is connected to the convex edge of the second subpixel electrode 191b.

The first and second subpixel electrodes 191a and 191b of each pixel electrode 191 shown in FIGS. 3 and 4 are adjacent to each other in the row direction, while the first and second subpixel electrodes 191 of each pixel electrode 191 shown in FIG. The subpixel electrodes 191a and 191b are adjacent to each other in the column direction.

Referring to FIG. 3, the relative positions of the first subpixel electrode 191a and the second subpixel electrode 191b within each pixel electrode 191 are reversed between two adjacent rows. For example, the first subpixel electrode 191a of each pixel electrode 191 in the upper row of the two rows shown in FIG. 3 is arranged to the right side of the second subpixel electrode 191b, while the The first subpixel electrode 191a of each pixel electrode 191 in the lower row is arranged to the left of the second subpixel electrode 191b.

In contrast, the relative positions of the first subpixel electrode 191a and the second subpixel electrode 191b within each pixel electrode 191 shown in FIG. 4 are the same in all rows. For example, the first subpixel electrode 191a of each pixel electrode 191 in all rows shown in FIG. 4 is arranged to the right side of the second subpixel electrode 191b. However, the first subpixel electrode 191a may be arranged to the left side of the second subpixel electrode 191b. In this arrangement, pixel electrodes 191 adjacent in the column direction form a straighter line than that shown in FIG. 3 .

In the arrangement shown in FIG. 5 , the relative (column direction) positions of the first subpixel electrode 191a and the second subpixel electrode 191b in each pixel electrode 191 are reversed in two adjacent rows. For example, among the pixel electrodes 191 in the leftmost column among the four columns shown in FIG. The first subpixel electrode 191a is disposed on top of the second subpixel electrode 191b. The widths of the color filters 230R, 230G, and 230B shown in FIG. 5 are half of those shown in FIGS. 3 and 4 .

In the above arrangement, the first and second subpixel electrodes 191a and 191b with an area ratio of about 1:2 are well organized without wasting space. The arrangements shown in Figures 3 and 4 may be suitable for large pixel size display devices, eg, large display devices greater than about 32", especially television sets of about 40". Conversely, the arrangement shown in FIG. 5 may be suitable for small pixel size display devices, eg, 17" or 19" monitors and the like.

Meanwhile, since the color filters 230R, 230G, and 230B extend almost straight in the column direction, monochrome lines may be easily displayed. Specifically, the pixel electrodes 191 in each column shown in FIG. 4 form straighter lines so as to be more conducive to displaying vertical lines.

In addition, the color filters 230R, 230G, and 230B have equal areas in order to facilitate color balance.

Also, each pixel electrode 191 is bent only once, providing an increased aperture ratio compared to a pixel electrode bent two or more times.

Referring again to FIG. 1, the gray voltage generator 800 generates a plurality of gray voltages related to the light transmittance of the pixel PX. However, the gray voltage generator 800 may generate only a prescribed number of gray voltages, called reference gray voltages, instead of generating all the gray voltages.

The gate driver 400 is connected to the gate lines of the panel assembly 300, and synthesizes a gate-on voltage Von and a gate-off voltage Voff from an external device to generate a gate signal Vg applied to the gate lines.

The data driver 500 is connected to the data lines of the panel assembly 300 and applies a data voltage Vd selected from gray voltages provided by the gray voltage generator 800 to the data lines. However, when the gray voltage generator 800 generates the reference gray voltages, the data driver 500 may generate gray voltages for all gray voltages by dividing the reference gray voltages and selecting the data voltage Vd from the generated gray voltages.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each drive and processing unit 400, 500, 600, and 800 may include at least one integrated circuit (IC) chip mounted on the LC panel assembly 300 or a flexible printed circuit (FPC) in a tape carrier package (TCP) device. These driving and processing units are connected to the panel assembly 300 on the membrane. Alternatively, at least one of the driving and processing units 400, 500, 600, and 800 may be integrated in the panel assembly 300 together with signal lines and switching elements. Alternatively, all driving and processing units 400, 500, 600 and 800 may be integrated in a single IC chip, but at least one driving and processing unit 400, 500, 600 and 800 or at least one driving and processing unit 400, 500, 600 and At least one circuit element within 800 may be arranged on a single IC chip.

Now, the operation of the above-mentioned LCD will be described in detail.

The signal controller 600 is supplied with input image signals R, G, and B and input control signals to control image display from an external graphics controller (not shown). The input image signals R, G and B contain luminance information of each pixel PX with a predetermined number of gradations such as 1024 (=2 ¹⁰ ), 256 (=2 ⁸ ) or 64 (=2 ⁶ ). The input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK and a data enable signal DE, and the like.

After generating the gate control signal CONT1 and the data control signal CONT2, and processing the input image signals R, G, and B suitable for the operation of the panel assembly 300 and the data driver 500 according to the input control signal and the input image signals R, G, and B, the signal control The driver 600 transmits the gate control signal CONT1 to the gate driver 400 , and transmits the processed image signal DAT and the data control signal CONT2 to the data driver 500 . The output image signal DAT is a digital signal having a predetermined number of values or grayscales.

The gate control signal CONT1 includes a scan start signal STV for indicating scan start and at least one clock signal for controlling an output timing of the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE for determining the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal sync start signal STH for notifying the start of data transmission of a group of sub-pixels, a load signal LOAD for instructing application of a data voltage to the panel assembly 300 , and a data clock signal HCLK. The data control signal CONT2 may further include an inversion signal RVS for inverting the polarity of the data voltage with respect to the common voltage Vcom.

The data driver 500 receives packets of the image signal DAT for the group of sub-pixels from the signal controller 600 in response to the data control signal CONT2 from the signal controller 600 . The data driver 500 converts the image signal DAT into an analog data signal selected from gray voltages provided by the gray voltage generator 800, and applies the data signal to the data line.

In response to the gate control signal CONT1 from the signal controller 600, the gate driver 400 applies the gate-on voltage Von to the gate lines, thereby turning on the switching elements connected to the gate lines. The data voltage applied to the data line is supplied to the sub-pixel through the activated switching element.

Referring to FIGS. 3-5, when the first subpixel electrode 191a and the second subpixel electrode 191b forming the pixel electrode 191 are coupled to respective switching elements, that is, when each subpixel includes its own switching element, at different times through The two sub-pixels may be provided with respective data voltages by the same data line or by different data lines at the same time. However, when the first sub-pixel electrode 191a is coupled to a switching element (not shown) and the second sub-pixel electrode 191b is capacitively coupled to the first sub-pixel electrode 191a, the switching element can be used to directly provide One subpixel electrode 191a supplies a data voltage, and another subpixel including the second subpixel electrode 191b may have a voltage varying according to the voltage of the first subpixel electrode 191a. At this time, the voltage of the first subpixel electrode 191a having a relatively small area is preferably greater than that of the second subpixel electrode 191b having a relatively large area with respect to the common voltage.

On the other hand, after charging the two subpixel electrodes 191a and 191b with the same voltage, the voltages of the subpixel electrodes 191a and 191b can be distinguished from each other by using a storage capacitor (not shown) or the like.

When a voltage difference is generated between the two terminals of the LC capacitor Clc1/Clc2, a main electric field substantially perpendicular to the surfaces of the panels 100 and 200 is generated within the LC layer 3, and the pixel electrodes 191, PE and the common electrode CE are generally referred to as field generate electrodes. The LC molecules within the LC capacitor Clc1/Clc2 tend to change their orientation in response to the electric field so that their long axis can be perpendicular to the direction of the electric field. Molecular orientation determines the polarization of light passing through the LC layer 3 . The polarizer converts light polarization into light transmittance so that the pixel PX displays the luminance indicated by the image signal DAT.

The tilt angle of LC molecules depends on the electric field strength. Since the voltages of the LC capacitors Clc1 and Clc2 are different from each other, the inclination angles of the LC molecules in the sub-pixels are different from each other, so the brightness of the two sub-pixels is different. Thus, the voltages of the two sub-pixels can be adjusted so that the image viewed from the side is closest to the image viewed from the front, ie, the side gamma curve is closest to the front gamma curve, thereby improving side visibility.

In addition, relative to the common voltage Vcom, the area of the first subpixel electrode 191a whose voltage is higher than that of the second subpixel electrode 191b may be smaller than the area of the second subpixel electrode 191b, so that the side gamma curve is closer to the front gamma curve. Specifically, when the area ratio of the first sub-pixel electrode 191a and the second sub-pixel electrode 191b is approximately equal to 1:2, the side gamma curve is further close to the front gamma curve to further improve side visibility.

First, the tilt direction of the LC molecules is determined by the horizontal electric field component. The horizontal electric field components are generated by the cutouts 71a, 71b, 92a and 92b of the field generating electrodes 191 and 270CE and the edges of the subpixel electrodes 191a and 191b, which distort the main electric field. The horizontal electric field component is substantially perpendicular to the edges of the cutouts 71a, 71b, 92a, 92b and the edges of the first and second subpixel electrodes 191a and 191b.

Referring to Figures 3-5, since the LC molecules on each sub-region divided by a set of cutouts 71a, 71b, 92a, 92b are inclined to be perpendicular to the main edge of the sub-region, the azimuth distribution of the inclined direction is positioned in four directions, thereby increasing The base viewing angle of the LCD.

As mentioned above, the width of the sub-region, i.e. the distance between the curved portion of the cutout of the common electrode CE and the curved edge of the sub-pixel electrodes 191a, 191b, is preferably equal to about 20-35 microns, so that the level of the main electric field can be properly used The component sum can reduce the decrease in aperture ratio caused by the cutouts 71a, 71b, 92a, 92b.

The direction of the sub-electric field generated by the voltage difference between the adjacent sub-pixel electrodes 191a and 191b is perpendicular to the main edge of the sub-region. Therefore, the electric field direction of the secondary electric field coincides with the direction of the horizontal component of the main electric field. Therefore, the sub-electric field between the adjacent subpixel electrodes 191a and 191b enhances the determination of the tilt direction of the LC molecules.

All the pixels PX are supplied with data voltages by repeating this procedure in units of a horizontal period, which is denoted by "1H" and equal to one period of the horizontal synchronization signal Hsync or the data enable signal DE.

When the next frame starts after one frame is completed, the inversion control signal RVS applied to the data driver 500 is controlled so as to invert the polarity of the data voltage, which is called 'frame inversion'. The inversion control signal RVS can also be controlled so that the polarity of the data signal flowing in the data line is periodically inverted during one frame, for example, row inversion and dot inversion, or the polarity of the data signal in one packet Polarity inversion, for example, column inversion and dot inversion.

The voltage on the LC capacitor Clc1 or Clc2 forces the LC molecules in the LC layer 3 to reorient to a stable state corresponding to the voltage, and the reorientation of the LC molecules takes time due to the slow response time of the LC molecules. With the voltage application on the LC capacitor Clc1 or Clc2 also maintained, the LC molecules continue to reorient themselves to change light transmission or brightness until they reach a steady state. When the LC molecules reach a steady state and stop reorienting, the light transmittance becomes fixed.

When the pixel voltage in this stable state is called the target pixel voltage and the light transmittance in this stable state is called the target light transmittance, the target pixel voltage and the target light transmittance have a one-to-one correspondence.

Since the time for turning on the switching element of each pixel PX to apply the data voltage to the pixel is limited, it is difficult for the LC molecules in the pixel PX to reach a stable state during the application of the data voltage. However, even though the switching element is turned off, the voltage on the LC capacitor Clc1 or Clc2 is still present, so the LC molecules continue to reorient so that the capacitance of the LC capacitor Clc1 or Clc2 changes. Neglecting leakage current, when the switching element is turned off, since one terminal of the LC capacitor Clc1 or Clc2 is floating, the total amount of charges stored in the LC capacitor Clc1 or Clc2 remains constant. Therefore, the capacitance variation of the LC capacitor Clc1 or Clc2 causes the voltage of the LC capacitor Clc1 or Clc2, that is, the pixel voltage to vary.

Therefore, when a data voltage equivalent to the target pixel voltage is supplied to the pixel PX, the target pixel voltage determined in a steady state is hereinafter referred to as a "target data voltage", the actual pixel voltage of the pixel PX may be different from the target pixel voltage, Therefore, the pixel PX may not achieve the corresponding target light transmittance. The more the target transmittance differs from the light transmittance the subpixel originally had, the more the actual pixel voltage differs from the target pixel voltage.

Therefore, it is required that the data voltage applied to the pixel PX be higher or lower than the target data voltage, which can be realized by DCC (Dynamic Capacitance Compensation), for example.

The DCC, which may be performed by the signal controller 600 or a separate image signal modifier, modifies the image signal of a frame of sub-pixels, hereinafter referred to as "current image signal", so as to correspond to the image signal of the immediately previous frame of the sub-pixel, hereinafter Referred to as the "previous image signal", a modified current image signal is generated, hereinafter referred to as the "modified (current) image signal". The corrected image signal is basically obtained through experiments, and the difference between the corrected current image signal and the previous image signal is usually greater than the difference between the current and previous image signal before correction. However, when the current image signal and the previous image signal are equal to each other or their difference is small, the corrected image signal may be equal to the current image signal, that is, the current image signal may not be corrected.

As such, the data voltage applied to the sub-pixel by the data driver 500 is higher or lower than the target data voltage.

However, the target transmittance cannot be obtained by the above method. In this case, a predetermined voltage, hereinafter referred to as a pre-tilt voltage, is previously applied to the sub-pixels to pre-tilt the LC molecules, and then a main voltage is applied to the sub-pixels.

To this end, the signal controller 600 or the image signal modifier modifies the current image signal in consideration of the next frame image signal, hereinafter referred to as 'next image signal', and the previous image signal. For example, if the next image signal is very different from the current image signal, even if the current image signal is equal to the previous image signal, the current image signal is corrected to prepare the next frame.

For the highest grayscale or the lowest grayscale, correction of image signals and data voltages may or may not be performed. In order to correct the highest grayscale or the lowest grayscale, the grayscale voltage range generated by the grayscale voltage generator 800 can be widened compared with the target data voltage range required to obtain the target brightness or the target transmittance range, the target brightness or the target transmittance range. The transmittance is represented by the gray scale of the image signal.

Now, a structure of an LC panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 and FIGS. 1-4.

FIG. 7 is an equivalent circuit diagram of signal lines and pixels according to an exemplary embodiment of the present invention.

The LC panel assembly shown in FIG. 7 includes a plurality of signal lines and a plurality of pixels PX connected to the signal lines. The signal lines include a plurality of pairs of gate lines GLa and GLb, a plurality of data lines DL, and a plurality of storage electrode lines SL extending substantially parallel to the gate lines GLa and GLb.

Each pixel PX includes a pair of subpixels PXa and PXb. Each sub-pixel PXa/PXb includes a switching element Qa/Qb, an LC capacitor Clca/Clcb, and a storage capacitor Csta/Cstb, the switching element Qa/Qb is connected to one of the gate lines GLa, GLb and one of the data lines DL, and the LC capacitor Clca /Clcb is coupled to the switching element Qa/Qb, and the storage capacitor Csta/Cstb is connected between the switching element Qa/Qb and the storage electrode line SL.

Switching elements Qa/Qb, such as thin film transistors (TFTs), are provided on the lower panel 100 and have three terminals: a control terminal connected to the gate line GLa/GLb; an input terminal connected to the data line DL; and an LC capacitor Clca connected to /Clcb and the output of the storage capacitor Csta/Cstb.

The storage capacitors Csta/Cstb are auxiliary capacitors for the LC capacitors Clca/Clcb. The storage capacitor Csta/Cstb includes a subpixel electrode and an independent signal line, which is provided on the lower panel 100, overlaps the subpixel electrode via an insulator, and is supplied with a predetermined voltage such as a common voltage Vcom. Alternatively, the storage capacitor Csta/Cstb includes a sub-pixel electrode and an adjacent gate line, called a previous gate line, which overlaps the sub-pixel electrode via an insulator.

Since the LC capacitors Clca/Clcb and the like are described above with reference to FIG. 2 , their detailed description will be omitted.

In the LCD shown in FIG. 7, the signal controller 600 receives input image signals R, G, and B, and converts the input image signals R, G, and B for each pixel PX into A pair of output image signals DAT to be supplied to the data driver 500 . In addition, the gray voltage generator 800 generates a pair of gray voltage sets for the respective sub-pixels PXa and PXb. Two groups of gray voltages are alternately supplied to the data driver 500 by the gray voltage generator 800 or alternately selected by the data driver 500, thereby providing different voltages to the two sub-pixels PXa and PXb.

At this time, it is preferable to determine the converted output image signal value and the grayscale voltage value within each group so that the composition of the gamma curves of the two sub-pixels PXa and PXb viewed from the front is close to the reference gamma curve. For example, the composite gamma curve viewed from the front is consistent with the most appropriate reference gamma curve viewed from the front, while the composite gamma curve viewed from the side is most similar to the reference gamma curve viewed from the front.

An example of the LC panel assembly shown in FIG. 8 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8-11.

8 is a layout diagram of a lower panel of an LC panel assembly according to an exemplary embodiment of the present invention, FIG. 9 is a layout diagram of an upper panel of an LC panel assembly according to an exemplary embodiment of the present invention, and FIG. 9, and FIG. 11 is an exemplary cross-sectional view of the LC panel assembly shown in FIG. 10 along line XI-XI.

Referring to FIGS. 8-11 , an LC panel assembly according to an exemplary embodiment of the present invention includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , and a liquid crystal layer 3 interposed between the panels 100 and 200 .

First, the lower panel 100 will be described with reference to FIGS. 8 , 10 and 11 .

A plurality of gate conductors including pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110, such as transparent glass or plastic.

The gate lines 121a and 121b transmit gate signals, extend substantially in a lateral direction, and are arranged at opposite upper and lower positions, respectively.

Each first gate line 121a includes a plurality of first gate electrodes 124a protruding downward and an end portion 129a having a large area for contacting another layer or connecting with an external driving circuit. Each second gate line 121b includes a plurality of second gate electrodes 124b protruding upward and an end portion 129b having a large area for contacting another layer or connecting with an external driving circuit. The first and second gate lines 121 a and 121 b may extend to be connected to the gate driver 400 , and the gate driver 400 may be integrated on the substrate 110 .

The storage electrode line 131 is supplied with a predetermined voltage, such as a common voltage Vcom, and extends substantially parallel to the first and second gate lines 121a and 121b. Each storage electrode line 131 is disposed between the first and second gate lines 121a and 121b at an almost equidistant distance from the first gate line 121a and the second gate line 121b. The storage electrode lines 131 may have various shapes and arrangements. For example, each storage electrode line 131 may include a plurality of extensions extending upward and downward.

The first and second gate lines 121a, 121b and the storage electrode lines 131 can be made of metals containing aluminum, such as aluminum and aluminum alloys, metals containing silver, such as silver and silver alloys, metals containing copper, such as copper and copper alloys, metals containing molybdenum. , such as molybdenum and molybdenum alloys, chromium, tantalum or titanium. However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the two films may be made of low resistivity metals, including aluminum-containing metals, silver-containing metals and copper-containing metals, in order to reduce signal delay or voltage drop. Another film can be made of a material such as molybdenum-containing metals, chromium, tantalum or titanium, which has good physical properties with other materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), Chemical and electrical contact properties. Examples of two-layer film combinations are a lower chromium film and an upper aluminum (alloy) film and a lower aluminum (alloy) film and an upper molybdenum (alloy) film. However, the first and second gate lines 121a, 121b and the storage electrode line 131 may be made of various metals or conductors.

The sides of the first and second gate lines 121a, 121b and the storage electrode lines 131 are inclined relative to the surface of the substrate, and their inclination angles range from about 30-80 degrees.

A gate insulating layer 140 , which may be made of silicon nitride (SiNx) or silicon oxide (SiOx), is formed on the first and second gate lines 121 a , 121 b and the storage electrode line 131 .

A plurality of first and second semiconductor islands 154 a and 154 b , which may be made of hydrogenated amorphous silicon (abbreviated as “a-Si”) or polysilicon, are formed on the gate insulating layer 140 . The first/second semiconductor islands 154a/154b are disposed on the first/second gate electrodes 124a/124b.

Pairs of ohmic contact islands 163b and 165b are formed on semiconductor island 154b, and multiple pairs of ohmic contact islands (not shown) are formed on semiconductor island 154a. Ohmic contact islands 163b and 165b may be made of n+ hydrogenated a-Si heavily doped with n-type impurities such as phosphorus, or they may be made of silicide.

The sides of the semiconductor islands 154a and 154b and the ohmic contact islands 163b and 165b are inclined relative to the surface of the substrate 110, and their inclination angles may be in the range of about 30-80 degrees.

A plurality of data conductors including a plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175 a and 175 b are formed on the ohmic contacts 163 b, 165 b and the gate insulating layer 140 .

The data lines 171 transmit data signals, and extend substantially in a longitudinal direction to cross the first and second gate lines 121 a , 121 b and the storage electrode lines 131 . Near the intersection with the storage electrode line 131, each data line 171 includes a plurality of bent portions protruding leftward or rightward. Each curved portion includes a pair of inclined portions connected to each other to form a herringbone shape and form an angle of about 45 degrees with the grid line 121 .

Each data line 171 includes a plurality of first and second source electrodes 173a and 173b and end portions 179, the first and second source electrodes 173a and 173b protrude toward the first and second gate electrodes 124a and 124b, respectively, and the end portions 179 The portion 179 has a large area to be in contact with another layer or to be connected with an external driving circuit. The data line 171 may extend to be connected to the data driver 500 , and the data driver 500 may be integrated on the substrate 110 .

The first and second drain electrodes 175 a and 175 b are separated from each other and from the data line 171 . The first/second drain electrodes 175a/175b are arranged opposite to the first/second source electrodes 173a/173b with respect to the first/second gate electrodes 124a/124b. Each first/second drain electrode 175a/175b includes a wide end portion 177a/177b and a narrow end portion. The wide end portion 177a/177b overlaps the storage electrode line 131, and the narrow end portion is partially surrounded by the first/second source electrode 173a/173b.

The first/second gate electrode 124a/124b, the first/second source electrode 173a/173b and the first/second drain electrode 175a/175b together with the first/second semiconductor island 154a/154b form a first/second TFT Qa/Qb, the first/second TFT Qa/Qb has a channel formed in the first/second semiconductor island 154a/154b, and the first/second semiconductor island 154a/154b is arranged on the first/second source electrode 173a/173b and the first/second drain electrodes 175a/175b.

The data conductors 171, 175a and 175b may be made of refractory metals such as chromium, molybdenum, tantalum, titanium and alloys thereof. However, they may have a multilayer structure including a refractory metal film (not shown) and a low-resistivity film (not shown). A good example of the multilayer structure is a double layer structure comprising a lower chromium/molybdenum (alloy) film and an upper aluminum (alloy) film, and a lower molybdenum (alloy) film, a middle aluminum (alloy) film and an upper molybdenum (alloy) film Three-tier structure. However, the data conductors 171, 175a, and 175b may be made of various metals or conductors.

The data conductors 171, 175a and 175b have sloped edge profiles, and their slope angles range from about 30-80 degrees.

The ohmic contacts 163b and 165b are sandwiched only between the underlying semiconductor islands 154a, 154b and the data conductors 171, 175a, 175b located above, and reduce the contact resistance therebetween. The semiconductor islands 154a and 154b include some exposed parts which are not covered by the data conductors 171, 175a and 175b, such as the parts located between the source electrode 173 and the drain electrodes 175a, 175b.

A passivation layer 180 is formed on the data conductors 171, 175a and 175b and exposed portions of the semiconductor islands 154a and 154b. The passivation layer 180 may be made of an inorganic or organic insulator, and it may have a flat top surface. Examples of inorganic insulators include silicon nitride and silicon oxide. The organic insulator can have photosensitivity and a dielectric constant of less than about 4.0. The passivation layer 180 may include a lower film of an inorganic insulator and an upper film of an organic insulator so that it provides excellent insulating properties of the organic insulator while preventing exposed portions of the semiconductor islands 154a and 154b from being damaged by the organic insulator.

The passivation layer 180 has a plurality of contact holes 182, 185a and 185b exposing the end portion 179 of the data line 171, and the first drain electrode 175a and the second drain electrode 175b, respectively. The passivation layer 180 and the gate insulating layer 140 have a plurality of contact holes 181a and 181b exposing end portions 129a and 129b of the gate lines 121a and 121b.

A plurality of pixel electrodes 191 and a plurality of contact assistants 81 a , 81 b and 82 are formed on the passivation layer 180 . They can be made of transparent conductors such as ITO or IZO or reflective conductors such as silver, aluminum, chromium or alloys thereof.

The pixel electrodes 191 have the structure shown in FIG. 3, and each pixel electrode 191 includes a pair of sub-pixel electrodes 191a and 191b. The subpixel electrodes 191a and 191b include cutouts 92a and 92b.

The data line 171 , specifically, the curved portion of the data line 171 extends along some curved edges of the pixel electrode 191 . Therefore, the electric field generated between the data line 171 and the subpixel electrodes 191a, 191b has a horizontal component substantially parallel to the main electric field horizontal component, so that the tilt direction determination of the LC molecules is enhanced. In addition, the aperture ratio is increased.

The storage electrode line 131, the extensions 177a and 177b of the drain electrodes 175a and 175b, and the contact holes 185a and 185b are located on a straight line connecting the bent portions of the subpixel electrodes 191a and 191b. The straight line connecting the bent portions of the sub-pixel electrodes 191a and 191b forms the boundary of the above-mentioned sub-region, so this configuration can cover the texture that may be generated by the disorder of LC molecules near the sub-region boundary, thereby increasing the aperture ratio.

Since other features of the pixel 191 are described above with reference to FIG. 3 , their detailed description will be omitted.

The first/second subpixel electrode 191a/191b is physically and electrically connected to the first/second drain electrode 175a/175b through the contact hole 185a/185b, so that the first/second subpixel electrode 191a/191b The two drain electrodes 175a/175b receive the data voltage. The first/second subpixel electrodes 191a/191b and the common electrode 270 form first/second LC capacitors Clca/Clcb, which store an applied voltage after the TFT is turned off.

By overlapping the extension 177a/177b of the first/second drain electrode 175a/175b connected to the first/second subpixel electrode 191a/191b with the storage electrode line 131, the first/second subpixel for enhancing the charge storage capacity is formed. The second storage capacitor Csta/Cstb.

The contact assistants 81a, 81b and 82 are connected to the end portions 129a and 129b of the gate lines 121a and 121b and the end portion 179 of the data line 171 through the contact holes 181a, 181b and 182, respectively. The contact assistants 81a, 81b, and 82 protect the end portions 129a, 129b, and 179, and enhance adhesion between the end portions 129a, 129b, and 179 and external devices.

The upper panel 200 is described below with reference to FIGS. 9-11.

A light blocking member 220 called a black matrix is formed on an insulating substrate 210 such as transparent glass or plastic. The light blocking member 220 includes a plurality of linear portions facing the border of the pixel electrodes 191 on the lower panel 100 and widening portions facing the TFTs Qa and Qb on the lower panel 100 . The light blocking member 220 blocks light leakage near the pixel electrode 191 and the TFTs Qa, Qb, and may have various shapes.

A plurality of color filters 230 are also formed on the substrate 210 and the light blocking member 220 . The color filter 230 is substantially disposed in a region surrounded by the light blocking member 220 , and the color filter 230 may extend substantially longitudinally along the pixel electrode 191 . Each color filter 230R represents one of three primary colors, such as red, green and blue.

The overcoat 250 is formed on the color filter 230 and the light blocking member 220 . The cover layer 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The cover layer 250 may be omitted.

The common electrode 270 is formed on the capping layer 250 . The common electrode 270 may be made of a transparent conductive material, such as ITO or IZO, and has multiple sets of cutouts 71a and 71b as described above with reference to FIG. 3 .

The number of cutouts 71a and 71b may vary according to design factors, and the light blocking member 220 may also overlap the cutouts 71a and 71b to prevent light from leaking through the cutouts 71a and 71b.

Alignment layers 11 and 21 , which may be of the same type, are coated on inner surfaces of panels 100 and 200 .

Polarizers 12 and 22 are provided on the outer surfaces of the panels 100 and 200 so that their polarization axes can cross, and the polarization axes can form an angle of about 45 degrees with the curved edges of the subpixel electrodes 191a and 191b for increasing light efficiency. When the LCD is a reflective LCD, one of the polarizers 12 and 22 may be omitted.

The LCD may further include at least one retardation film (not shown) for compensating the retardation of the LC layer 3 . The LCD may further include a backlight unit (not shown) to provide light to the LC layer 3 through polarizers 12 and 22 , retardation films, and panels 100 and 200 .

Preferably, the LC layer 3 has negative dielectric anisotropy and is vertically aligned.

The shape and arrangement of the cutouts 71a, 71b, 92a and 92b can be modified.

At least one of the cutouts 71a, 71b, 92a and 92b can be replaced by a protrusion (not shown) or a recess (not shown). The protrusions may be made of organic or inorganic materials and disposed above or below the field generating electrode 191 or 270 .

Another example of the LC panel assembly shown in FIG. 10 will be described in detail with reference to FIG. 12 .

FIG. 12 is another exemplary cross-sectional view of the LC panel assembly shown in FIG. 10 along line XI-XI.

Referring to FIG. 12 , the LC panel assembly according to the present embodiment includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , an LC layer 3 , and a pair of polarizers 12 and 22 .

The layered structure of the LC panel assembly according to this embodiment is similar to the structure shown in FIG. 11 .

Regarding the lower panel 100 , a gate conductor including a plurality of first and second gate lines 121 a and 121 b and a plurality of storage electrode lines 131 is formed on the substrate 110 . The first and second gate lines 121a and 121b include first and second gate electrodes 124a and 124b and end portions 129a and 129b, respectively. A gate insulating layer 140, a plurality of semiconductor islands 154a and 154b, and a plurality of ohmic contacts 163b and 165b are sequentially formed on the first and second gate lines 121a, 121b and the storage electrode line 131. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175 a and 175 b is formed on the ohmic contacts 163 b, 165 b and the gate insulating layer 140 . The data line 171 includes first and second source electrodes 173a and 173b and an end portion 179, and the drain electrodes 175a and 175b include wide end portions 177a and 177b. A passivation layer 180 is formed on the data conductors 171, 175a and 175b, the gate insulating layer 140, and exposed portions of the semiconductor islands 154a and 154b. A plurality of contact holes 181 a , 181 b , 182 , 185 a and 185 b are provided on the passivation layer 180 and the gate insulating layer 140 . A plurality of pixel electrodes 191 including subpixel electrodes 191a and 191b and having cutouts 92a and 92b and a plurality of contact assistants 81a, 81b and 82 are formed on the passivation layer 180, and the alignment layer 11 is coated thereon.

Regarding the upper panel 200 , a light blocking member 220 , a cover layer 250 , a common electrode 270 having a plurality of cutouts 71 a and 71 b , and an alignment layer 21 are formed on an insulating substrate 210 .

Unlike the LC panel assembly shown in FIG. 11, the lower panel 100 shown in FIG. 12 includes a plurality of color filters 230 disposed under the passivation layer 180, while the upper panel 200 has no color filters.

The color filter 230 extends in the longitudinal direction while being periodically bent, and is not provided in a peripheral area in which the end portions 129a and 129b of the first and second gate lines 121a and 121b and the end portion 179 of the data line 171 are arranged on the periphery. within the area. The color filter 230 has a through hole 235 larger than the contact hole 185a so that the contact hole 185a can pass through the through hole 235 .

Adjacent color filters 230 may overlap each other near the boundary of the pixel electrode 191 to prevent any light leakage therebetween, which functions as the light blocking member 220 . In this case, the light blocking member 220 disposed on the upper panel 200 may be omitted to simplify the manufacturing process.

Another passivation layer (not shown) may be formed under the color filter 230 .

The cover layer 250 on the upper panel 200 may be omitted.

Many of the above-described features of the LC panel assembly shown in FIG. 11 can be applied to the LC panel assembly shown in FIG. 12 .

Another example of the LC panel assembly shown in FIG. 7 will be described in detail with reference to FIGS. 13 , 14 , 15 and 16 .

13 is a layout diagram of a lower panel of an LC panel assembly according to an exemplary embodiment of the present invention, FIG. 14 is a layout diagram of an upper panel of an LC panel assembly according to another embodiment of the present invention, and FIG. 14, and FIG. 16 is a cross-sectional view of the LC panel assembly shown in FIG. 15 along the line XVI-XVI'-XVI".

Referring to FIGS. 13-16 , the LC panel assembly according to the present exemplary embodiment includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , an LC layer 3 , and a pair of polarizers 12 and 22 .

The layered structure of the LC panel assembly according to this embodiment is similar to the structure shown in FIGS. 8-11.

Regarding the lower panel 100 , a gate conductor including a plurality of first and second gate lines 121 a and 121 b and a plurality of storage electrode lines 131 is formed on the substrate 110 . The first and second gate lines 121a and 121b include first and second gate electrodes 124a and 124b and end portions 129a and 129b, respectively. A gate insulating layer 140, a plurality of semiconductor elements 154a and 154b, and a plurality of ohmic contacts 163b and 165b are sequentially formed on the first and second gate lines 121a, 121b and the storage electrode line 131. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175a and 175b is formed on the ohmic contacts 163b and 165b. The data line 171 includes first and second source electrodes 173a and 173b and an end portion 179, and the drain electrodes 175a and 175b include wide end portions 177a and 177b. A passivation layer 180 is formed on the data conductors 171, 175a and 175b, the gate insulating layer 140, and exposed portions of the semiconductor elements 154a and 154b. A plurality of contact holes 181 a , 181 b , 182 , 185 a and 185 b are provided on the passivation layer 180 and the gate insulating layer 140 . A plurality of pixel electrodes 191 including subpixel electrodes 191a and 191b and having cutouts 92a and 92b and a plurality of contact assistants 81a, 81b and 82 are formed on the passivation layer 180, and the alignment layer 11 is formed thereon.

Regarding the upper panel 200 , a light blocking member 220 , a plurality of color filters 230 , an overcoat layer 250 , a common electrode 270 having a plurality of cutouts 71 a and 71 b , and an alignment layer 21 are formed on the insulating substrate 210 .

Unlike the LC panel assembly shown in FIGS. 8-11 , the arrangement of the pixel electrode 191 and the subpixel electrodes 191 a and 191 b is substantially the same as that shown in FIG. 4 . As mentioned above, the adjacent pixel electrodes 191 in the column direction shown in FIG. 3 form straighter lines than the lines shown in FIG. The configuration shown in 16 is more conducive to displaying lengthwise lines.

The data line passes through approximately the center of the first or second subpixel electrode 191a or 191b. Specifically, the curved portion of the data line 171 overlaps the cutouts 71a and 71b of the common electrode 270 instead of extending along the boundary of the pixel electrode 191, and this configuration is also compared with the case where the data line 171 extends along the boundary of the pixel electrode 191. gives essentially the same advantages.

The first/second TFTs Qa/Qb are arranged on the right/left side of the data line 171. Compared with the configuration shown in FIGS. 8-12, this configuration shortens the length of the second drain electrode 175b in order to further increase the aperture ratio.

In addition, the semiconductor elements 154 a and 154 b extend along the data line 171 and the drain electrodes 175 a , 175 b to form the semiconductor strip 151 , and the ohmic contact 163 b extends along the data line 171 to form the ohmic contact strip 161 . The semiconductor strip 151 has almost the same planar shape as the data conductors 171, 175a and 175b and the underlying ohmic contacts 161 and 165b.

The method of manufacturing the lower panel according to an exemplary embodiment of the present invention simultaneously forms the data conductors 171, 175a and 175b, the semiconductor element 151, and the ohmic contacts 161a and 165b using one photolithography process.

A photoresist pattern used in a photolithography process has a thickness that varies with position, specifically, it has first and second portions of reduced thickness. The first part is located on the wiring area to be occupied by the data conductors 171, 175a and 175b, and the second part is located on the channel area of the TFT Qa/Qb.

The location-dependent thickness of the photoresist is obtained by several techniques, for example, by providing translucent areas on the exposure mask along with light-transmissive transparent areas and light-blocking opaque areas. The translucent area can have a slit pattern, a grid pattern, or a film with a medium transmittance or medium thickness. When using a slit pattern, preferably, the slit width or slit pitch is smaller than the resolution of a light exposer used in photolithography. Another example is the use of reflowable photoresist. In detail, once a photoresist pattern made of reflowable material is formed by using a common exposure mask with transparent and opaque areas, it is subjected to a reflow process to flow over the photoresist-free areas , thus forming thin sections.

As a result, the manufacturing process is simplified by omitting photolithography steps.

Many of the above-described features of the LC panel assembly shown in Figures 8-11 can be applied to the LC panel assembly shown in Figures 13-16.

The structure of an LC panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 17 and 18 and FIGS. 1, 2 and 4. Referring to FIG.

FIG. 17 is an equivalent circuit diagram of signal lines and pixels according to an exemplary embodiment of the present invention.

The LC panel assembly shown in FIG. 17 includes a plurality of signal lines and a plurality of pixels PX connected to the signal lines. The signal lines include a plurality of gate lines GL, a plurality of pairs of data lines DLa and DLb, and a plurality of storage electrode lines SL.

Each pixel PX includes a pair of subpixels PXc and PXd. Each sub-pixel PXc/PXd includes a switching element Qc/Qd, an LC capacitor Clcc/Clcd and a storage capacitor Cstc/Cstd, the switching element Qc/Qd is connected to one of the gate line GL and one of the data lines DLa and DLb, and the LC capacitor Clcc/ Clcd is coupled to the switching element Qc/Qd, and the storage capacitor Cstc/Cstd is connected between the switching element Qc/Qd and the storage electrode line SL.

Switching elements Qc/Qd, such as thin film transistors (TFTs), are provided on the lower panel 100 and have three terminals: a control terminal connected to the gate line GL; an input terminal connected to the data line DLa/DLb; and connected to the LC capacitor Clcc /Clcd output.

Since the operations of the LC capacitors Clcc/Clcd, the storage capacitors Cstc and Cstd, and the LCD including the panel assembly shown in FIG. 17 etc. are basically the same as above, their detailed description will be omitted.

Note, however, that unlike that shown in FIG. 7 , the data voltages are simultaneously supplied to the two subpixels PXc and PXd forming the pixel PX shown in FIG. 17 .

An example of the LC panel assembly shown in FIG. 17 according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 18. Referring to FIG.

FIG. 18 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 18, an LC panel assembly according to an exemplary embodiment of the present invention includes a lower panel (not shown), an upper panel (not shown) facing the lower panel, and an LC layer (not shown).

The layered structure of the LC panel assembly according to this embodiment is almost the same as that shown in FIGS. 13-16.

Regarding the lower panel, a gate conductor including a plurality of gate lines 121 and a plurality of storage electrode lines 131 is formed on a substrate (not shown). Each gate line 121 includes first and second gate electrodes 124c and 124d and an end portion 129 . A gate insulating layer (not shown) is formed on the gate conductor 121 and the storage electrode line 131, and pairs of semiconductor islands 154c and 154d are formed on the gate insulating layer. A plurality of ohmic contacts (not shown) are formed on the semiconductor islands 154c and 154d. Data conductors including pairs of first and second data lines 171a and 171b and pairs of first and second drain electrodes 175c and 175d are formed on the ohmic contacts and the gate insulating layer. Each first/second data line 171a/171b includes a plurality of first/second source electrodes 173c/173d and an end portion 179a/179b. Each first/second drain electrode 175c/175d includes a wide end portion 177c/177d. A passivation layer (not shown) is formed on the data conductors 171a, 171b, 175c and 175d, the gate insulating layer, and exposed portions of the semiconductor islands 154c and 154d. A plurality of contact holes 181, 182a, 182b, 185c and 185d are provided on the passivation layer and the gate insulating layer. A pixel electrode 191 including first and second subpixel electrodes 191c and 191d and a plurality of contact assistants 81, 82a and 82b are formed on the passivation layer. The first subpixel electrode 191c has a cutout 92c, and the second subpixel electrode 191d has a cutout 92d. An alignment layer (not shown) is formed on the pixel electrode 191 and the passivation layer.

Regarding the upper panel, a light blocking member (not shown), a color filter (not shown), a cover layer (not shown), a common electrode (not shown) having a plurality of cutouts 71c and 71d, and an alignment layer (not shown) is formed on an insulating substrate (not shown).

However, the number of grid lines 121 in the LC panel assembly shown in FIG. 18 is half of the number of grid lines in the LC panel assembly shown in FIGS. The number of and 171b is twice the number of data lines in the LC panel assembly shown in FIGS. 13-16. Also, the first and second TFTs Qc and Qd coupled to the first and second subpixel electrodes 191c and 191d forming the pixel electrode 191 are connected to the same gate line 121 and different data lines 171a, 171b.

The bent portions of the data lines 171a and 171b are disposed near a boundary between the first subpixel electrode 191c and the second subpixel electrode 191d. The first and second TFTs Qc and Qd are disposed on left sides of the first and second data lines 171a and 171b, respectively.

Many of the above-described features of the LC panel assembly shown in FIGS. 13-16 can be applied to the LC panel assembly shown in FIG. 18 .

The structure of an LC panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 19, 20, 21, 22 and 23 and FIGS. 1-3.

FIG. 19 is an equivalent circuit diagram of a signal line and a pixel PX according to an exemplary embodiment of the present invention.

The LC panel assembly shown in FIG. 19 includes a plurality of signal lines and a plurality of pixels PX connected to the signal lines. The signal lines include a plurality of gate lines GL and a plurality of data lines DL.

Each pixel PX includes a pair of first and second subpixels PXe and PXf and a coupling capacitor Ccp connected between the first subpixel PXe and the second subpixel PXf.

The first sub-pixel PXe includes a switching element Q, a first LC capacitor Clce, and a storage capacitor Cste, the switching element Q is connected to one of the gate lines GL and one of the data lines DL, the first LC capacitor Clce is coupled to the switching element Q, and the storage capacitor Cste The capacitor Cste is connected to the switching element Q. The second subpixel PXf includes a second LC capacitor Clcb coupled to a coupling capacitor Ccp.

A switching element Q, such as a thin film transistor (TFT), is provided on the lower panel 100 and has three terminals: a control terminal connected to the gate line GL; an input terminal connected to the data line DL; and connected to the LC capacitor Clce, the storage capacitor Cste , and the output terminal of the coupling capacitor Ccp.

The switching element Q transmits a data voltage from the data line DL in response to a gate signal from the gate line GL to the first LC capacitor Clce and the coupling capacitor Ccp, and the coupling capacitor Ccp converts the magnitude of the data voltage and supplies it to the second LC capacitor Clcf.

Assuming that a common voltage Vcom is applied to the storage capacitor Cste and the capacitors Clce, Cste, Clcf or Ccp, whose capacitances are denoted by the same numeral, the voltage Ve stored in the first LC capacitor Clce and the voltage stored in the second LC capacitor Clcf Vf satisfies:

Vf=Ve×[Ccp/(Ccp+Clcf)]

Since Ccp/(Ccp+Clcf) is less than 1, the voltage Vf stored in the second LC capacitor Clcf is smaller than the voltage Ve stored in the first LC capacitor Clce. This relationship is satisfied even if the voltage applied to the storage capacitor Cste is not the common voltage Vcom.

By adjusting the capacitance of the coupling capacitor Ccp, the desired ratio of voltages Ve and Vf can be obtained.

An example of the LC panel assembly shown in FIG. 19 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 20 and 21 .

20 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention, and FIG. 21 is a cross-sectional view of the LC panel assembly shown in FIG. 20 along line XXI-XXI.

The LC panel assembly includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , a liquid crystal layer 3 , and a pair of polarizers 12 and 22 .

The layered structure of the LC panel assembly according to these embodiments is almost the same as that shown in FIGS. 8-11.

Regarding the lower panel 100 , a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the substrate 110 . Each gate line 121 includes a plurality of gate electrodes 124 and an end portion 129 . A gate insulating layer 140 , a plurality of semiconductor islands 154 , and a plurality of pairs of ohmic contacts 163 and 165 are sequentially formed on the gate line 121 . A data conductor including a plurality of data lines 171 and a plurality of drain electrodes 175 is formed on the ohmic contacts 163 , 165 and the gate insulating layer 140 . Each data line 171 includes a plurality of source electrodes 173 and an end portion 179 , and each drain electrode 175 includes an extension 177 . A passivation layer 180 is formed on the data conductors 171 and 175 , the gate insulating layer 140 , and exposed portions of the semiconductor island 154 . A plurality of contact holes 181 , 182 and 185 are provided on the passivation layer 180 and the gate insulating layer 140 . A plurality of pixel electrodes 191 including subpixel electrodes 191e and 191f and having cutouts 92e and 92f are formed on the passivation layer 180 . The alignment layer 11 is formed on the pixel electrode 191 and the passivation layer 180 .

Regarding the upper panel 200 , a light blocking member 220 , a plurality of color filters 230 , an overcoat layer 250 , a common electrode 270 having a plurality of cutouts 71 e and 71 f , and an alignment layer 21 are formed on the insulating substrate 210 .

Unlike the LC panel assembly shown in FIGS. 8-11 , the second subpixel electrode 191f is electrically floating, while the first subpixel electrode 191e is connected to the drain electrode 175 .

Instead, each extension 177 of the drain electrode 175 extends along the storage electrode line 131 below the second subpixel electrode 191f to overlap the second subpixel electrode 191f. Accordingly, the first subpixel electrode 191e and the second subpixel electrode 191f are capacitively coupled to each other to form a coupling capacitor Ccp.

The passivation layer 180 includes a lower film 180p and an upper film 180q. The lower film 180p may be made of an inorganic insulator, such as silicon nitride or silicon oxide, and the upper film 180q may be made of an organic insulator. The organic insulator can have photosensitivity and a dielectric constant of less than about 4.0, and can provide a planar surface. The passivation layer 180 may have a single-layer structure, and the single-layer structure may be made of an inorganic or organic insulator.

The upper film 180q has a plurality of openings 187 exposing the lower film 180p, and the plurality of openings 187 are arranged on the extension 177 of the drain electrode 175 under the second subpixel electrode 191f. Therefore, the second sub-pixel electrode 191f overlaps the extension 177 in the opening 187, in which only the lower film 180p is inserted, and therefore, the capacitance of the coupling capacitor Ccp is large compared with a structure in which both the lower film 180p and the upper film 180q are inserted, thereby Increase the aperture ratio.

Many of the above-described features of the LC panel assembly shown in FIGS. 8-11 can be applied to the LC panel assembly shown in FIGS. 20 and 21 .

Another example of the LC panel assembly shown in FIG. 19 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 22 and 23 .

22 is a layout view of an LC panel assembly according to an exemplary embodiment of the present invention, and FIG. 23 is a cross-sectional view of the LC panel assembly shown in FIG. 22 along line XXIII-XXIII.

The LC panel assembly includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , a liquid crystal layer 3 , and a pair of polarizers 12 and 22 .

The layered structure of the LC panel assembly according to these embodiments is almost the same as that shown in FIGS. 20 and 22 .

Regarding the lower panel 100 , a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the substrate 110 . Each gate line 121 includes a plurality of gate electrodes 124 and an end portion 129 . A gate insulating layer 140 , a plurality of semiconductor islands 154 , and a plurality of pairs of ohmic contacts (not shown) are sequentially formed on the gate line 121 . A data conductor including a plurality of data lines 171 and a plurality of drain electrodes 175 is formed on the ohmic contacts and the gate insulating layer 140 . Each data line 171 includes a plurality of source electrodes 173 and an end portion 179 . A passivation layer 180 including a lower film 180 p and an upper film 180 q is formed on the data conductors 171 and 175 , the gate insulating layer 140 , and exposed portions of the semiconductor island 154 . A plurality of contact holes 181 , 182 , 185 and 186 are provided on the passivation layer 180 and the gate insulating layer 140 . A plurality of pixel electrodes 191 including subpixel electrodes 191e and 191f having cutouts 92e and 92f are formed on the passivation layer 180 . The alignment layer 11 is formed on the pixel electrode 191 and the passivation layer 180 .

Regarding the upper panel 200 , a light blocking member 220 , a plurality of color filters 230 , an overcoat layer 250 , a common electrode 270 having cutouts 71 e and 71 f , and an alignment layer 21 are formed on an insulating substrate 210 .

Unlike the LC panel assembly shown in FIGS. 20 and 21 , pairs of capacitive electrodes 136 are formed on the substrate 110 . Capacitance electrode 136 is composed of the same layer as gate line 121 and storage electrode line 131 , and is separated from gate line 121 and storage electrode line 131 . A pair of capacitive electrodes 136 is symmetrically arranged with respect to the storage electrode line 131 and extends along the cutout 71 f of the common electrode 270 . The capacitor electrode 136 is connected to the second subpixel electrode 191f through the contact hole 186 .

Each drain electrode 175 includes an extension 177 and a pair of branches 176 separated from the extension 177 . The extension 177 extends along the storage electrode line 131 to the bending point of the cutout 71f, and a branch extends from the end of the extension 177 along the pair of capacitor electrodes 136 so as to overlap the capacitor electrodes 136 . The branch 176 has a plurality of through holes 176H larger than the contact holes 186 so that the contact holes 186 can pass through the through holes 176H.

The branch 176 and the capacitive electrode 136 form a coupling capacitor Ccp, and the second subpixel electrode 191f and the part of the extension 177 disposed thereunder also contribute to the coupling capacitance.

Many of the above-described features of the LC panel assembly shown in FIGS. 20 and 21 can be applied to the LC panel assembly shown in FIGS. 22 and 23 .

As described above, the above-described exemplary embodiments of the present invention provide sub-region widths suitable for various LCD pixel sizes. These exemplary embodiments give a balanced color configuration and facilitate the display of vertical and oblique lines. In addition, these exemplary embodiments further improve aperture ratio, side visibility, and reference viewing angle.

Although the present invention has been described in detail with reference to the exemplary embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made to the present invention without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (32)

1. A liquid crystal display, comprising: first substrate; second substrate; a plurality of first signal lines formed on the first substrate; a plurality of second signal lines formed on the first substrate; a first subpixel electrode formed on the first substrate and having a curved edge; a second subpixel electrode formed on the first substrate, the second subpixel electrode has a curved edge, and is arranged adjacent to the first subpixel electrode in a row direction; a third subpixel electrode formed on the first substrate, the third subpixel electrode has a curved edge and is arranged adjacent to the second subpixel electrode in a column direction; a fourth subpixel electrode formed on the first substrate, the fourth subpixel electrode has a curved edge, and is arranged adjacent to the third subpixel electrode in a row direction and adjacent to the first subpixel electrode in a column direction; a common electrode formed on the second substrate facing the first to fourth subpixel electrodes on the first substrate; and a plurality of switching elements each coupled to one of the first signal lines, one of the second signal lines, and one of the first to fourth subpixel electrodes, Wherein, the curved edge of the second sub-pixel electrode is longer than the curved edge of the first sub-pixel electrode, The curved edge of the fourth subpixel electrode is longer than the curved edge of the third subpixel electrode, the fourth subpixel electrode has an edge adjacent to an edge of the second subpixel electrode, and The convexity and concavity of the sub-pixel electrodes are fixed in the row direction, while the convexity and concavity of the sub-pixel electrodes are alternately reversed in the column direction. 2. The liquid crystal display of claim 1, wherein row-direction lengths of the first to fourth subpixel electrodes are substantially equal to each other. 3. The liquid crystal display of claim 2, wherein each of the second and fourth sub-pixel electrodes has a bent edge length about twice that of each of the first and third sub-pixel electrodes. 4. The liquid crystal display of claim 1, further comprising a tilt direction determining part formed on the common electrode. 5. The liquid crystal display as claimed in claim 4 , wherein the tilt direction determining member comprises a cutout having a curved portion passing through one of the first to fourth subpixel electrodes and substantially parallel to the first to fourth subpixel electrodes. A curved edge of one of the subpixel electrodes extends. 6. The liquid crystal display of claim 5, wherein a distance between the curved portion of the cutout and the curved edge of one of the first to fourth sub-pixel electrodes is approximately equal to 20-35 micrometers. 7. The liquid crystal display of claim 1, wherein different voltages obtained from a single image information are supplied to the first subpixel electrode and the second subpixel electrode. 8. The liquid crystal display of claim 1, wherein different voltages obtained from a single image information are supplied to the first subpixel electrode and the fourth subpixel electrode. 9. The liquid crystal display of claim 1, wherein the switching element comprises a first thin film transistor coupled to the first sub-pixel electrode and a second thin film transistor coupled to the second or fourth sub-pixel electrode, and the first and the first The two thin film transistors are connected to two different first signal lines and a single second signal line. 10. The liquid crystal display of claim 9, wherein the first and second thin film transistors are turned on to transmit a signal from a single second signal line in response to two different signals of the first signal line. 11. The liquid crystal display of claim 9, wherein the first and second thin film transistors are turned on to transmit signals of two different signals from the first signal line in response to a signal from the single second signal line. 12. A liquid crystal display comprising: Substrate; a pixel electrode disposed on the substrate and including a first sub-pixel electrode and a second sub-pixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of curved edges substantially parallel to each other, The second subpixel electrode has a pair of curved edges substantially parallel to each other, and, the height of the second subpixel electrode is greater than the height of the first subpixel electrode, Wherein the convexity and concavity of the curved edges of the first and second sub-pixel electrodes are alternately reversed relative to each other in the height direction. 13. The liquid crystal display of claim 12, wherein the first sub-pixel electrode and the second sub-pixel electrode are adjacent to each other along a length direction. 14. The liquid crystal display of claim 12, wherein the first subpixel electrode and the second subpixel electrode are adjacent in a height direction. 15. The liquid crystal display of claim 12, wherein a length of the first subpixel electrode is substantially equal to a length of the second subpixel electrode. 16. The liquid crystal display of claim 15, wherein the height of the second subpixel electrode is about twice the height of the first subpixel electrode. 17. The liquid crystal display of claim 12, wherein each curved edge of the first and second subpixel electrodes has a bending point, and each of the first and second subpixel electrodes is symmetrical about a straight line connecting the bending point, respectively. 18. The liquid crystal display as claimed in claim 12, wherein each pair of curved edges comprises a concave edge and a convex edge, and the convex edge of the first subpixel electrode is adjacent to the concave edge of the second subpixel electrode, or the convex edge of the first subpixel electrode The concave edge is adjacent to the convex edge of the second sub-pixel electrode. 19. The liquid crystal display as claimed in claim 12 , wherein each pair of curved edges comprises a concave edge and a convex edge, an end of the concave edge of the first subpixel electrode is opposite to an end of the convex edge of the second subpixel electrode, and the first The end of the convex edge of the subpixel electrode is opposite to the end of the concave edge of the second subpixel electrode. 20. The liquid crystal display of claim 12, further comprising a tilt direction determining part formed on the common electrode. 21. The liquid crystal display as claimed in claim 20, wherein the tilt direction determining member comprises a cutout having a curved portion passing through the first or second subpixel electrode and substantially parallel to the first or second subpixel electrode. The curved edges of the electrodes are extended. 22. The liquid crystal display of claim 21, wherein a distance between the curved portion of the cutout and one of the curved edges of the first or second sub-pixel electrodes adjacent to the curved portion is approximately equal to 20-35 microns. 23. The liquid crystal display of claim 12, wherein the first subpixel electrode and the second subpixel electrode have respective different voltages. 24. The liquid crystal display of claim 23, wherein the first subpixel electrode and the second subpixel electrode are supplied with respective different voltages obtained from a single image information. 25. The liquid crystal display of claim 23, further comprising: a first thin film transistor coupled to the first subpixel electrode; a second thin film transistor coupled to the second subpixel electrode; a first signal line coupled to the first thin film transistor; a second signal line coupled to the second thin film transistor; and A third signal line is coupled to the first and second thin film transistors, and the third signal line crosses the first and second signal lines. 26. The liquid crystal display as claimed in claim 25, wherein in response to a signal from the first signal line, the first thin film transistor is turned on so as to transmit a signal from the third signal line, and in response to a signal from the second signal line, the third thin film transistor is turned on. Two thin film transistors are used to transmit signals from the third signal line. 27. The liquid crystal display of claim 25, wherein the first thin film transistor and the second thin film transistor are arranged to face each other with respect to the third signal line. 28. The liquid crystal display as claimed in claim 25, wherein in response to a signal from the third signal line, the first thin film transistor is turned on so as to transmit the signal from the first signal line, and in response to a signal from the third signal line, the first thin film transistor is turned on. Two thin film transistors are used to transmit signals from the second signal line. 29. The liquid crystal display of claim 25, further comprising a fourth signal line extending along a straight line connecting bending points of curved edges of the first and second sub-pixel electrodes. 30. The liquid crystal display of claim 29, wherein each of the first and second thin film transistors includes a drain electrode overlapping the fourth signal line. 31. The liquid crystal display of claim 12, wherein the first subpixel electrode and the second subpixel electrode are capacitively coupled to each other. 32. The liquid crystal display of claim 31 , further comprising: a thin film transistor coupled to the first subpixel electrode; a first signal line coupled to the thin film transistor; and A second signal line coupled to the thin film transistor and intersecting the first signal line.

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