CN1996275A - Bulk memory accessing method for I2C controller in 10-site addressing mode - Google Patents

Abstract

The present invention provides a method for an I2C controller using a 10-bit addressing mode to access a large-capacity storage, wherein the operation of the above-mentioned I2C controller to randomly read data from the large-capacity storage at least includes the following steps: the I2C controller sends a start Signal; send a write operation command, wait for the return ACK; send the upper 8 bits of the address of the above data, wait for the return ACK; send the lower 8 bits of the address of the above data, wait for the return ACK; send a start signal; send a read operation command, wait for ACK to be returned; read one byte of the above data, wait for ACK to be returned; if the size of the read data is one byte, go directly to the next step; if the read data is larger than one byte, repeat In this step, until the data of the specified length are all read; send a stop command. By adopting the method of the present invention, the access of the standard I2C controller to the I2C storage medium with a larger space can be realized simply and efficiently.

Description

Method of 10-bit addressing mode I2C controller accessing large-capacity memory

technical field

The invention relates to the communication field of telecommunication equipment, electronic equipment and computer equipment, in particular to a method for using an I2C controller to access a large-capacity memory.

Background technique

At present, in the fields of numerically controlled consumer appliances, telecommunication equipment, electronic equipment, and computer equipment, I2C buses and other equipment are widely used to realize mutual communication between equipment.

The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus consisting of a bidirectional data line SDA and a clock line SCL. Through these two lines, system components can communicate with each other. The I2C bus is divided from the transmission rate, there are standard mode (100Kbit/s), fast mode (400Kbit/s), high-speed mode (3.4Mbit/s); from the addressing range, there are 7-bit address mode and 10-bit address mode . The I2C bus connects the I2C master controller (bus master) and the I2C auxiliary device (bus slave). Generally speaking, the I2C master controller is usually a microprocessor, and the I2C auxiliary device includes many devices connected to the I2C bus, such as memory, The sensor waits. Usually, the I2C master controller can directly communicate with the I2C auxiliary device and provide a clock signal; the I2C auxiliary device can receive data from the I2C master controller or provide data to the main controller. Only one I2C master can be present at any one time, but multiple I2C slaves can be present at the same time.

Data can only be transmitted on the I2C bus in bytes, and the unit of data transmission is bytes. The transmission usually takes the most significant bit (MSB for short) as the first bit, followed by 8 bits of data. After each byte transmission is completed, an Acknowledge bit (Acknowledge bit, below) will be sent from the other party. ACK for short). Figure 1 shows the format of data transfer on the I2C bus.

When the I2C master controller sends a command to the I2C auxiliary device, the software needs to make the following settings: set the auxiliary device address (Slave Address), the operation attribute is read or write, command word (Command Code), data (Data), and then set The control register is turned on (start). If all the parameters are correct, the I2C master controller will generate an SMI# signal or generate an interrupt when the write operation completes the data transmission, or the read operation completes the data reception.

The I2C bus supports 7 operation modes: Quick Command, Send Byte, Receive Byte, Write Byte, Read Byte, Procedure Call and Data Block Read/Write. Some of the most commonly used modes of operation are listed below:

1) Read a byte (Byte)/word (Word) from the current address:

There is an address pointer counter inside the memory belonging to the I2C auxiliary device to record the pointer of the current access address. After each memory read/write operation, the pointer will be automatically moved and saved. Receiving bytes can simply obtain the data stored in the address bit pointed by the current pointer. The data flow of this operation on the bidirectional data line SDA is shown in FIG. 2 . The memory reads a data block operation from the current address, that is, the operation of reading a word is different from the operation of reading a byte. The difference is that the STOP command is not sent after transferring a byte of data, but continues Read the data of the next byte until all the data is read, and then send the STOP command. The operation data flow is shown in Figure 6.

2) Write a byte to the current address:

The protocol for writing a byte is very similar to reading a byte, the only difference is the direction of data transfer: reading a byte of data is transmitted from the I2C auxiliary device to the I2C master controller; writing a byte of data is from the The I2C master controller passes to the I2C slave device. The data flow of this operation on the bidirectional data line SDA is similar to that in Figure 2, except that the eighth bit of the first byte in Figure 2 is changed to "0".

3) Write a byte/word to the specified address of the memory:

The command format requires to first transmit the address of an I2C auxiliary device, and mark a write operation in the last bit of the command word, wait for the response of the I2C auxiliary device, and then transmit the data address (Word Address) with a length of one byte and the address to be written. Enter the value of the byte, and then send a STOP command later. The data flow of this operation on the bidirectional data line SDA is shown in FIG. 3 . The difference between the operation of writing a word (buffer write) and the operation of writing a byte (byte write) is that the STOP command is not sent after transferring a byte of data, but continues to write the next word Section data, until all the data is written, and then send the STOP command, the operation data flow is shown in Figure 4.

4) Read a byte/word from the specified address of the memory:

The read operation is not the same as the write operation. To read a specified address, you must first use the write command to tell the memory the address to be read, and then perform the read operation. After receiving the byte, send the STOP command. The data flow of the operation is as follows: Figure 5 shows. If you want to read a word of data from the specified address, the operation before the STOP command remains unchanged, but after receiving the first byte, the STOP command is not sent, but another byte is read until all bytes are received. data before sending the STOP command.

Currently, the I2C bus with 10-bit addressing mode provides 10-bit address lines for auxiliary devices, which can only access up to 1K bytes of physical space. With the increase of I2C bus applications, greater requirements are put forward for the memory space. At present, there are many memories with a storage space larger than 1K bytes on the market, and because the address bits of the data have exceeded 10 bits, so use The normal I2C bus operation process can no longer complete the random access of data normally.

Contents of the invention

In view of the above, the present invention will solve the technical problem that the I2C controller adopting the 10-bit addressing mode cannot address the storage device with a storage space larger than 1K bytes due to insufficient addressing space, so as to improve the storage space of the system and provide more storage space for the system. powerful functions.

In order to solve the above-mentioned technical problems, the present invention proposes a method for accessing a large-capacity memory by an I2C controller using a 10-bit addressing mode, wherein the above-mentioned I2C controller randomly reads data from the large-capacity memory at least including the following steps:

Step 1, the I2C controller sends a start (start) signal;

Step 2, the I2C controller sends a write operation command to the mass storage, and waits for an ACK to be returned;

Step 3, after receiving the ACK, the I2C controller sends the upper 8 bits of the address of the above data to the mass storage, and waits for the ACK to be returned;

Step 4, after receiving the ACK, the I2C controller sends the lower 8 bits of the address of the above data to the mass storage, and waits for the ACK to be returned;

Step 5, after receiving the ACK, the I2C controller sends another start signal;

Step 6, the I2C controller sends a read operation command to the mass storage, and waits for an ACK to be returned;

Step 7, after receiving the ACK, the I2C controller reads one byte of the above data from the mass storage, and waits for the ACK to be returned;

Step 7', if the size of the read data is one byte, go directly to step 8; if the read data is larger than one byte, repeat step 7 until all the data of the specified length is read, go to step 8 ;

Step 8, after receiving the ACK, send a stop (stop) command.

Among them, the write operation command in step 2 is a byte, and its 1-7 bits are used to determine the slave controller selected for this operation, that is, the address of the above-mentioned large-capacity storage, and its 8th bit is 0, indicating It is used to determine that this operation is a write operation; the read operation command in step 6 is a byte, and its 1-7 bits are used to determine the slave controller selected for this operation, that is, the address of the above-mentioned large-capacity storage, Its 8th bit is 1, indicating that it is used to determine that this operation is a read operation.

The operation of writing random read data to mass memory by using the I2C controller in 10-bit addressing mode includes at least the following steps:

Step 1, the I2C controller sends a start signal;

Step 2, the I2C controller sends a write operation command to the mass storage, and waits for an ACK to be returned;

Step 3, after receiving the ACK, the I2C controller sends the upper 8 bits of the address where the above data will be written to the mass storage, and waits for the ACK to be returned;

Step 4, after receiving the ACK, the I2C controller sends the lower 8 bits of the address where the above data will be written to the mass storage, and waits for the ACK to be returned;

Step 5, after receiving the ACK, the I2C controller sends a byte of data to be written to the mass storage, and waits for the ACK to be returned;

Step 5', if the size of the data to be written is one byte, then go directly to step 6; if the data to be written is larger than one byte, repeat step 5 until all the data of the specified length is written, go to Step 6;

Step 6, after receiving the ACK, send the stop command.

Among them, the write operation command in step 2 is a byte, and its 1-7 bits are used to determine the slave controller selected for this operation, that is, the address of the above-mentioned large-capacity storage, and its 8th bit is 0, indicating Used to determine that this operation is a write operation. The data that can be written above is up to 15 bytes.

The method of the invention can simply and efficiently realize the access of the standard I2C controller to a storage medium with a larger space, effectively expand the available address space of the I2C auxiliary equipment, and provide more powerful functions for the I2C auxiliary equipment. Its advantages are as follows: the existing I2C controller is not changed, the circuit is not changed in any way, it is completely realized by software, and the compatibility of hardware is guaranteed.

The specific implementation of the present invention will be further described in detail below in conjunction with the accompanying drawings. The above and other objects, features and advantages of the present invention will be apparent to those skilled in the art from the detailed description of the method of the present invention.

Description of drawings

Figure 1 shows the format of data transmission on the I2C bus.

Figure 2 shows the data flow for the operation of reading a byte from the current address.

Figure 3 is the data flow of the I2C controller to write a byte operation to the specified address.

Figure 4 is the data flow for the operation of the I2C controller to write a continuous data block to the specified address.

Figure 5 is the data flow of the operation of the I2C controller to read a byte from the specified address.

Figure 6 is the data flow for the operation of the I2C controller to read a continuous data block from the current address.

FIG. 7 is a data flow of a memory byte read operation for a storage space larger than 1K bytes.

FIG. 8 is a data flow of a memory byte write operation for a storage space larger than 1K bytes.

FIG. 9 is a data flow of an operation of reading a continuous data block from a memory with a storage space larger than 1K bytes.

Detailed ways

The method described in the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Some large-capacity memories, especially memories larger than 1K bytes of storage space, provide some operations compatible with the operation of the I2C controller using 10-bit addressing mode, including: write by byte, write by page, current address Read/write, random read, page-by-page read, etc. Several common modes of operation are discussed below.

(1) Read a byte from the current address: This operation mode is exactly the same as the operation mode of reading a byte from the current address mentioned in the background technology, and will not be discussed here.

(2) Write a byte to the current address: This operation mode is exactly the same as the operation mode of writing a byte to the current address mentioned in the background technology, and will not be discussed here.

(3) Read a byte from the specified address: The random read method allows the I2C controller with 10-bit addressing mode to randomly access any address in the entire space. Before reading data, a null write operation must be performed first, and the word to be read The address of the section is passed to the bidirectional data line SDA, and then a read operation of the current address is performed.

Figure 7 shows the process of randomly reading a byte from a memory larger than 1K bytes of storage space. This process is very different from the process of the I2C controller using 10-bit addressing mode, and no single process can be completed independently. this function. The method combines a plurality of standard operation processes to realize the function of randomly reading a byte from a large-capacity memory. The basic idea is to use the I2C controller using 10-bit addressing mode as shown in Figure 3 to combine the operation of writing a byte to the specified address and the operation of reading a byte from the current address as shown in Figure 2 to achieve this. Function. Specific steps include at least:

Step 1: The I2C controller sends a Start signal;

Step 2: The I2C controller sends a write operation command and waits for the memory to respond with ACK;

Step 3: After receiving the ACK, the I2C controller sends the upper 8 bits of the specified address to the memory, and waits for the memory to respond to the ACK;

Step 4: After receiving the ACK, the I2C controller sends the lower 8 bits of the specified address to the memory, and waits for the memory to respond with ACK;

Step 5: After receiving ACK, send a Start signal;

Step 6: The I2C controller sends a read operation command to the memory, and waits for the memory to respond with ACK;

Step 7: After receiving the ACK, the I2C controller reads a byte of data from the memory and waits for the memory to respond with an ACK;

Step 8: Send STOP command.

FIG. 9 shows the operation of randomly reading a continuous data block from a memory with a storage space larger than 1K bytes. The main difference between the flow of randomly reading a contiguous block of data from mass storage and the flow of randomly reading a byte from mass storage is that after the first word is successfully read by the I2C controller using 10-bit addressing mode After the section, do not end the read operation immediately, but continue to wait for the large-capacity storage to send data to the I2C controller using the 10-bit addressing mode, and end the read operation after reading the specified data length. The method combines a plurality of standard operating procedures to complete the function of randomly reading a continuous data block from a large-capacity storage. Specific steps include at least:

Step 1: The I2C controller sends a Start signal;

Step 2: The I2C controller sends a write operation command and waits for the memory to respond with ACK;

Step 3: After receiving the ACK, the I2C controller sends the upper 8 bits of the specified address to the memory, and waits for the memory to respond to the ACK;

Step 4: After receiving the ACK, the I2C controller sends the lower 8 bits of the specified address to the memory, and waits for the memory to respond with ACK;

Step 5: After receiving ACK, send a Start signal;

Step 6: Send a read operation command and wait for the memory to respond with ACK;

Step 7: After receiving the ACK, the I2C controller reads a byte of data from the memory and waits for the memory to respond with an ACK;

Step 8: Repeat step 7 until all required data is read, and each byte of data read operation must wait for the memory to respond to ACK;

Step 9: Send STOP command.

(4) Write a byte to the specified address: this operation is compared with the operation of writing a byte to the specified address of the memory mentioned in the background technology, and there is an address of one byte more, and other places are completely Same, as shown in Figure 8.

Comparing Figure 4 and Figure 8 carefully, it is not difficult to find that the processing flow in Figure 4 only sends a memory address of one byte after issuing the write command, and 1-16 bytes of data can be continuously written later; the processing flow in Figure 8 It is required to send two bytes of memory address after the write command, followed by one byte of data. For memory, both data and bytes are just byte streams, and it is impossible and unnecessary to distinguish. Therefore, this method takes advantage of these characteristics and uses the I2C controller using 10-bit addressing mode to write two bytes to the specified memory address with the processing flow shown in Figure 4, so as to realize the function of randomly writing one byte to the large-capacity memory . The steps of the write operation include at least:

Step 1: The I2C controller sends a Start signal;

Step 2: The I2C controller sends a write operation command and waits for the memory to respond with ACK;

Step 3: After receiving the ACK, the I2C controller sends the upper 8 bits of the memory address to which the above data will be written to the memory, and waits for the memory to respond with ACK;

Step 4: After receiving the ACK, the I2C controller sends the lower 8 bits of the memory address to which the above data will be written to the memory, and waits for the memory to respond with ACK;

Step 5: After receiving the ACK, the I2C controller sends the data to be written to the memory, and waits for the memory to respond with an ACK;

Step 6: After receiving the ACK, the I2C controller sends a STOP command.

The main difference between the I2C controller using 10-bit addressing mode to write a continuous data block (buffer write) and write a byte (byte write) to the random address of the mass storage is that the data of a byte is successfully sent After that, the write operation is not ended, but multiple bytes are sent continuously, and the write end command is sent only after success. Therefore, such an operation flow can be realized by using the buffer writing process of the I2C controller using the 10-bit addressing mode. After careful analysis of Figure 4, it can be found that the buffer writing function of the large-capacity memory can be realized by using the process of Figure 4 and making slight changes. Due to the limitation of the two devices, a single write operation of buffer writing implemented by this method can write up to 15 bytes. The specific steps are:

Step 1: The I2C controller sends a Start signal;

Step 2: The I2C controller sends a write operation command and waits for the memory to respond with ACK;

Step 3: After receiving the ACK, the I2C controller sends the upper 8 bits of the memory address to which the above data will be written to the memory, and waits for the memory to respond with ACK;

Step 4: After receiving the ACK, the I2C controller sends the lower 8 bits of the memory address to which the above data will be written to the memory, and waits for the memory to respond with ACK;

Step 5: After receiving the ACK, the I2C controller sends the first byte of the data to be written to the memory, and waits for the memory to respond with an ACK;

Step 6: Repeat step 5 until all the data required to be written is sent, and each data byte sending operation must wait for the memory to respond to ACK;

Step 7: After receiving the ACK, the I2C controller sends a STOP command.

Without departing from the spirit and essence of the invention, those skilled in the art can make various corresponding changes according to the present invention, but these corresponding changes should all belong to the protection scope of the claims of the present invention.

Claims (6)

1. method that adopts the I2C controller access mass storage of 10 bit addressing patterns, it is characterized in that above-mentioned I2C controller from mass storage at random the operation of reading of data may further comprise the steps at least:

Step 1, the I2C controller sends a commencing signal;

Step 2, the I2C controller sends the write operation order to mass storage, and waits for its passback response bit;

Step 3, receive response bit after, the I2C controller sends the most-significant byte of the address of above-mentioned data to mass storage, and wait for its passback response bit;

Step 4, receive response bit after, the I2C controller sends the least-significant byte of the address of above-mentioned data to mass storage, and wait for its passback response bit;

Step 5, receive response bit after, the I2C controller sends a commencing signal again;

Step 6, the I2C controller sends the read operation order to mass storage, and waits for its passback response bit;

Step 7, receive response bit after, the I2C controller reads a byte of above-mentioned data from mass storage, and wait for its passback response bit;

Step 7 ', if the size of data that reads is a byte, then directly forward step 8 to; If the data that read are greater than a byte, repeating step 7 all reads up to the data of designated length and to finish, and forwards step 8 to;

Step 8, receive response bit after, transmission is ceased and desisted order.

2. method according to claim 1 is characterized in that:

Write operation order in the step 2 is a byte, and its 1-7 position is used to determine operate specifically selected slave controller, the address of above-mentioned mass storage just, and its 8th is 0, expression is used to determine that current operation is a write operation.

3. method according to claim 1 is characterized in that:

Read operation order in the step 6 is a byte, and its 1-7 position is used to determine operate specifically selected slave controller, the address of above-mentioned mass storage just, and its 8th is 1, expression is used to determine that current operation is read operation.

4. method that adopts the I2C controller access mass storage of 10 bit addressing patterns, the operation of reading of data may further comprise the steps at least to it is characterized in that writing at random to mass storage by above-mentioned I2C controller:

Step 1, the I2C controller sends a commencing signal;

Step 2, the I2C controller sends the write operation order to mass storage, and waits for its passback response bit;

Step 3, receive response bit after, the I2C controller sends the most-significant byte of the address will write above-mentioned data to mass storage, and waits for its passback response bit;

Step 4, receive response bit after, the I2C controller sends the least-significant byte of the address will write above-mentioned data to mass storage, and waits for its passback response bit;

Step 5, receive response bit after, the I2C controller sends a byte of the data that need write to mass storage, and waits for its passback response bit;

Step 5 ', the size of the data that write if desired is a byte, then directly forwards step 6 to; The data that write if desired are greater than a byte, and repeating step 5 all writes up to the data of designated length, forwards step 6 to;

Step 6, receive response bit after, transmission is ceased and desisted order.

5. method according to claim 4 is characterized in that:

Write operation order in the step 2 is a byte, and its 1-7 position is used to determine operate specifically selected slave controller, the address of above-mentioned mass storage just, and its 8th is 0, expression is used to determine that current operation is a write operation.

6. method according to claim 4 is characterized in that above-mentioned data mostly are 15 bytes most.