CN1988156B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Abstract

The invention provides a semiconductor device which improves the collector-emitter current characteristic, shortens the fall time, and particularly improves the latch-up tolerance of a parasitic semiconductor switching element. The present invention is a lateral semiconductor device including a plurality of unit semiconductor elements, each unit semiconductor element including an IGBT, including: a semiconductor substrate of a 1 st conductivity type; a semiconductor region of a 2 nd conductivity type provided in the semiconductor substrate; a collector layer of a 1 st conductivity type provided in the semiconductor region; a ring-shaped base layer of the 1 st conductivity type provided in the semiconductor region so as to surround the collector layer, spaced apart from the collector layer; and a 1 st emitter layer of a 2 nd conductivity type disposed in the base layer in a ring configuration, wherein carrier movement between the 1 st emitter layer and the collector layer is controlled by a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Description

Semiconductor device

technical field

The present invention relates to a semiconductor device, in particular to a semiconductor device for high withstand voltage power.

Background technique

Fig. 49 is a top view of a conventional lateral n-channel IGBT (insulated gate bipolar transistor), generally designated 700; furthermore, Fig. 50 is a cross-sectional view of Fig. 49 viewed from the X-X direction.

As shown in FIG. 50 , IGBT 700 includes p-type substrate 1 . An n-layer 2 is provided in a p-type substrate 1 , and an n-type buffer layer 3 is also formed in the n ⁻ layer 2 . Furthermore, p-type collector layer 4 is formed in n-type buffer layer 3 .

On the other hand, in n ⁻ layer 2 , p-type base layer 5 is formed at a predetermined distance from p-type collector layer 4 . In p-type base layer 5 , n-type emitter layer (n ⁺ ) 6 is formed inside the peripheral portion of p-type base layer 5 , shallower than p-type base layer 5 . In addition, in p-type base layer 5, p-type emitter layer (p ⁺ ) 7 is also formed.

On the surface of n ⁻ layer 2 sandwiched between n type buffer layer 3 and p type base layer 5, field oxide film 8 is formed. Further, on channel region 15 formed in p-type base layer 5 between emitter layer 6 and n ⁻ layer 2 , gate wiring 10 is provided via gate oxide film 9 . In addition, a protective film 11 is provided covering the field oxide film 8 and the like.

A gate electrode 12 is provided to be electrically connected to the gate wiring 10 . Furthermore, emitter electrode 13 is formed, electrically connected to both n-type emitter layer 6 and p-type emitter layer 7 . Furthermore, collector electrode 14 is formed, electrically connected to p-type collector layer 4 . The emitter electrode 13, the collector electrode 14, and the gate electrode 12 are electrically separated from each other.

As shown in Figure 49, the IGBT 700 has a p-type collector layer 4 in the center, which is composed of an n-type buffer layer 3, an n ^- layer 2, a p-type base layer 5, an n-type emitter layer 6, a p-type emitter layer 7 surrounds its surrounding structures in turn, and the straight line part connects the two semicircle parts into an endless shape. 49, field oxide film 8, gate oxide film 9, gate wiring 10, gate electrode 12, protective film 11, emitter electrode 13, and collector electrode 14 are omitted.

Patent Document 1: Patent No. 3647802

Contents of the invention

_{Fig .} 51 shows the collector-emitter current ( _ICE ) characteristics. The horizontal axis represents the collector-emitter voltage (V _CE ), and the vertical axis represents the collector-emitter current (I _CE ). The measured temperature is room temperature.

As can be seen from Figure 51, when V _CE increases gradually, I _CE becomes about 0.2A when V _CE is close to 6V, and tends to be saturated from around this point. Therefore, there is a problem that I _CE cannot be significantly increased even if V _CE is increased.

In addition, even when V _CE is from 0V to 6V, I _CE shows a gentle slope, and there is also a problem of high on-resistance (V _CE /I _CE ).

FIG. 52 shows the turn-off waveform of the IGBT 700 . The horizontal axis represents the off time, and the vertical axis represents the collector-emitter voltage (V _CE ) or the collector-emitter current (I _CE ). In FIG. 35 , (A _V ) represents a change in the V _CE value, and (A _I ) represents a change in the I _CE value.

As can be seen from FIG. 52, the fall time (the time required for _ICE to change from 90% of the maximum value to 10%) is a large value exceeding 1 μs. In this way, the junction-isolated (JI) lateral IGBT 700 of the IGBT formed on the n ^- layer 2 on the p-type substrate 1 has the problems of slow switching speed and large switching loss.

In addition, on the lateral IGBT 700, there are p-type collector layer 4/n-type buffer layer 3/n ^- type layer 2/p-type base layer 5/n-type emitter layer when short-circuited on the inverter circuit etc. The problem that the parasitic semiconductor switching element formed on 6 is locked, the current density of the IGBT 700 is increased, and it is easy to be damaged.

The present invention aims to solve such problems, and an object of the present invention is to provide a semiconductor device that improves collector-emitter current characteristics, shortens fall time, and improves latch-up resistance of parasitic semiconductor switching elements.

The present invention is a lateral semiconductor device composed of a plurality of unit semiconductor elements, characterized in that each unit semiconductor element is composed of IGBT, which includes: a semiconductor substrate of the first conductivity type; a second semiconductor substrate arranged on the semiconductor substrate A semiconductor region of conductivity type; a collector layer of the first conductivity type provided in the semiconductor region; in the semiconductor region, a ring-shaped base layer of the first conductivity type arranged to surround the collector layer, separated from the collector layer ; and the first emitter layer of the second conductivity type arranged in a circular configuration in the base layer, the carriers between the first emitter layer and the collector layer move, and the channel formed on the base layer The area is controlled, and each unit semiconductor element is arranged adjacent to each other. The first emitter layer is composed of an annular and continuous main body area and a protruding area protruding from the main body area. In the protruding area, it is connected with the emitter electrode. Connected, the above-mentioned protruding area extends along the radial direction of the above-mentioned main body area, and is roughly equidistantly arranged around the main body area, and the interval (W1) between two adjacent protruding areas is larger than the width (W2) of the protruding area (W1>W2).

In addition, the present invention provides a lateral semiconductor device composed of a plurality of unit semiconductor elements, wherein each unit semiconductor element is composed of an IGBT, which includes: a semiconductor substrate; a second conductivity type IGBT disposed on the semiconductor substrate a semiconductor region; a collector layer of the first conductivity type disposed in the semiconductor region; a ring-shaped base layer of the first conductivity type arranged to surround the collector layer, spaced from the collector layer in the semiconductor region; and In the base layer, the first emitter layer of the second conductivity type is arranged in a ring shape, and the carriers between the first emitter layer and the collector layer move to form on the base layer. The channel region is controlled, the unit semiconductor elements are arranged adjacent to each other, and an insulating film is provided between the semiconductor substrate and the semiconductor region, and the above-mentioned first emitter layer is composed of an annular and continuous body region and from the The main body area is composed of a protruding area that protrudes outward, and is connected to the emitter electrode in the protruding area. The above-mentioned protruding area extends along the radial direction of the above-mentioned main body area, and is arranged approximately equidistantly around the main body area. The interval (W1) of each raised area is larger than the width (W2) of the raised area (W1>W2).

As can be seen from the above description, according to the present invention, a semiconductor device having good collector-emitter current characteristics, a short fall time, and high resistance to latch-up of parasitic semiconductor switching elements can be obtained.

Description of drawings

Fig. 1 is the top view of the IGBT of embodiment 1 of the present invention;

Fig. 2 is the sectional view of the IGBT of embodiment 1 of the present invention;

Fig. 3 is a top view of another IGBT according to Embodiment 1 of the present invention;

Fig. 4 is the relationship between the number of unit IGBTs included in the IGBT of Example 1 of the present invention and the total channel width;

Fig. 5 shows that the IGBT channel region of the traditional structure is superimposed on the IGBT of the embodiment of the present invention;

Fig. 6 is a comparative graph of the IGBT surface area of the IGBT of Example 1 of the present invention and the IGBT of the conventional structure;

Fig. 7 is a graph showing the surface area comparison between the IGBT of Example 1 of the present invention and the IGBT of a conventional structure;

Fig. 8 shows the relationship between the collector-emitter voltage (V _CE ) and the collector-emitter current (I _CE ) of the IGBT according to Embodiment 1 of the present invention;

Fig. 9 is the top view of the IGBT of embodiment 2 of the present invention;

Fig. 10 is a cross-sectional view of an IGBT according to Embodiment 2 of the present invention;

Fig. 11 is a top view of another IGBT according to Embodiment 2 of the present invention;

Fig. 12 shows the turn-off waveform of the IGBT of Embodiment 2 of the present invention;

Fig. 13 shows the potential distribution, current distribution and depletion region boundary line when the resistive load of the IGBT of Embodiment 1 of the present invention is switched off;

FIG. 14 shows the distribution of holes when the resistive load of the IGBT according to Embodiment 1 of the present invention is switched off;

Fig. 15 shows the hole distribution, electron distribution and concentration distribution in the equilibrium state when the resistive load of the IGBT according to Embodiment 1 of the present invention is switched off;

Fig. 16 shows the potential distribution, current distribution and depletion region boundary line when the resistive load of the IGBT according to Embodiment 2 of the present invention is switched off;

FIG. 17 shows the distribution of holes when the resistive load of the IGBT according to Embodiment 2 of the present invention is switched off;

Fig. 18 shows the hole distribution, electron distribution and concentration distribution in the equilibrium state when the resistive load of the IGBT of Example 2 of the present invention is switched off;

Fig. 19 is a cross-sectional view of an IGBT according to Embodiment 3 of the present invention;

20 is a cross-sectional view of another IGBT according to Embodiment 3 of the present invention;

Fig. 21 shows the electric field distribution, current distribution and depletion region boundary line when the resistive load of the IGBT according to Embodiment 2 of the present invention is switched off;

Fig. 22 shows the electric field distribution, current distribution and depletion region boundary line when the resistive load of the IGBT according to Embodiment 3 of the present invention is switched off;

Fig. 23 is a top view showing part of an IGBT according to Embodiment 4 of the present invention;

Fig. 24 is a cross-sectional view of an IGBT according to Embodiment 4 of the present invention;

Fig. 25 is a cross-sectional view of an IGBT according to Embodiment 4 of the present invention;

Fig. 26 is a top view showing a part of an IGBT according to Embodiment 4 of the present invention;

27 is a top view showing a p-type emitter layer configuration of an IGBT according to Embodiment 4 of the present invention;

Fig. 28 is a top view showing a part of an IGBT according to Embodiment 5 of the present invention;

Fig. 29 is a cross-sectional view of an IGBT according to Embodiment 5 of the present invention;

Fig. 30 is a top view of the IGBT of Embodiment 6 of the present invention;

Fig. 31 is a top view of another IGBT according to Embodiment 6 of the present invention;

32 is a cross-sectional view of an IGBT according to Embodiment 6 of the present invention;

33 is a cross-sectional view of an IGBT according to Embodiment 7 of the present invention;

34 is a cross-sectional view of another IGBT according to Embodiment 7 of the present invention;

Fig. 35 is a top view showing an IGBT of Embodiment 8 of the present invention;

36 is a cross-sectional view of an IGBT according to Embodiment 8 of the present invention;

37 is a cross-sectional view of an IGBT according to Embodiment 8 of the present invention;

Fig. 38 is a top view showing the configuration of the p-type emitter layer of the IGBT of Embodiment 9 of the present invention;

39 is a cross-sectional view of an IGBT according to Embodiment 9 of the present invention;

Fig. 40 is a top view of the IGBT of Embodiment 10 of the present invention;

Figure 41 is an enlarged view of the IGBT of Embodiment 10 of the present invention;

Fig. 42 is an enlarged view of an IGBT according to Example 10 of the present invention.

Fig. 43 is an enlarged view of an IGBT according to Example 10 of the present invention.

Fig. 44 is a top view of another IGBT according to Embodiment 10 of the present invention;

Fig. 45 is an enlarged view of another IGBT according to Embodiment 10 of the present invention.

Fig. 46 is an enlarged view of another IGBT according to Embodiment 10 of the present invention.

Fig. 47 is an enlarged view of another IGBT according to Embodiment 10 of the present invention.

Fig. 48 is a cross-sectional view of an IGBT according to Embodiment 10 of the present invention;

Figure 49 is a top view of a conventional IGBT;

50 is a cross-sectional view of a conventional IGBT;

Fig. 51 shows the relationship between collector-emitter voltage (V _CE ) and collector-emitter current (I _CE ) of a conventional IGBT;

Figure 52 shows the turn-off waveform of a conventional IGBT;

Symbol Description

1 p-type substrate 2 n ^- layer 3 buffer layer 4 p-type collector layer

5 p-type base layer 6 n-emitter layer 7 p-type emitter layer

8 Field oxide film 9 Gate oxide film 10 Gate electrode

11 Protective film 12 Gate electrode 13 Emitter electrode

14 collector electrode 15 channel region 100 semiconductor device

Detailed ways

Example 1

FIG. 1 is a top view of a lateral n-channel IGBT (insulated gate bipolar transistor) of Embodiment 1 of the present invention, generally indicated at 100 . In addition, FIG. 2 is a cross-sectional view of FIG. 1 viewed in the A-A direction.

As shown in FIG. 2 , IGBT 100 includes p-type substrate 1 of silicon or the like. An n ⁻ layer 2 is provided in a p-type substrate 1 . In n ^- layer 2, n-type buffer layer 3 is selectively formed. Furthermore, in n-type buffer layer 3 , p-type collector layer 4 is selectively formed. In addition, the buffer layer 3 may not be provided (the same applies to the following examples).

On the other hand, in n ⁻ layer 2 , p-type base layer 5 is selectively formed at a predetermined distance from p-type collector layer 4 . In p-type base layer 5 , n-type emitter layer (n ⁺ ) 6 is selectively formed shallower than p-type base layer 5 inside the peripheral portion of p-type base layer 5 . Furthermore, in p-type base layer 5, p-type emitter layer (p ⁺ ) 7 is formed.

On the surface of n layer 2 sandwiched between n-type buffer layer 3 and p-type base layer 5, for example, field oxide film 8 such as a silicon oxide film is formed. In addition, on the channel region 15 formed in the p-type base layer 5 between the emitter layer 6 and the n ⁻ layer 2, a gate wiring 10 is provided via a gate oxide film 9 such as a silicon oxide film. The gate wiring 10 is composed of, for example, aluminum. In addition, for example, a protective film 11 such as a silicon nitride film is provided to cover the field oxide film 8 .

A gate electrode 12 is provided, and is electrically connected to the gate wiring 10 . The gate electrode 12 is composed of, for example, aluminum.

Furthermore, emitter electrode 13 is formed to electrically connect both n-type emitter layer 6 and p-type emitter layer 7 . Furthermore, collector electrode 14 is formed, electrically connected to p-type collector layer 4 . The emitter electrode 13 and the collector electrode 14 are made of aluminum, for example. The emitter electrode 13, the collector electrode 14, and the gate electrode 12 are electrically separated from each other.

In addition, as shown in FIG. 1, the IGBT 100 of the present embodiment 1 has a p-type collector layer 4 in the center, surrounded by an n-type buffer layer 3, an n ^- layer 2, a p-type base layer 5, an n-type The emitter layer 6 and the p-type emitter layer 7 surround the ring-shaped unit IGBT in turn, and are arranged in parallel to form multiple adjacent structures. Here, the unit IGBT has a circular shape, but may have an elliptical shape close to a circle, or a polygonal shape close to a circle.

In addition, for easy understanding in FIG. 2 , field oxide film 8 , gate oxide film 9 , gate wiring 10 , gate electrode 12 , protective film 11 , emitter electrode 13 , and collector electrode 14 are omitted. In addition, the emitter electrode 13, the collector electrode 14, and the gate electrode 12 of the unit IGBT are electrically connected to each other.

FIG. 3 is a top view of another IGBT of the first embodiment, generally indicated by 150 . Except that the p-type emitter layer 7 of the adjacent circular unit IGBT partially overlaps, the structure is the same as that of the IGBT 100.

FIG. 4 shows the relationship between the number of unit IGBTs and the total channel width when the IGBT is formed from a conventional slender endless IGBT 700 and when it is formed from a plurality of circular unit IGBTs such as the IGBT 150 of Embodiment 1. In FIG. 4, the horizontal axis is the number of unit IGBTs, and the vertical axis is the total channel width.

Compared with a single elongated IGBT, the total channel width is longer when multiple circular unit IGBTs are arranged in parallel, and when 10 unit IGBTs are arranged in parallel, the total channel width is about twice the channel width of one IGBT.

FIG. 5 is a channel region of an IGBT 700 with a conventional structure superimposed on an IGBT 150 composed of three unit IGBTs. It can be seen that the channel width can be increased by using the IGBT 150 of the first embodiment.

Fig. 6 is a comparison diagram of the surface area (occupied surface) of the IGBT 150 of the present embodiment 1 and the IGBT 700 of the conventional structure compared in Fig. 5 . The horizontal axis represents the number of unit IGBTs, and the vertical axis represents the surface area of the IGBT. It can be seen that the larger the number of unit IGBTs in the structure, the smaller the surface area can be compared with the conventional structure.

For example, as shown in FIG. 7, in the case of IGBT 150 formed of three unit IGBTs, the surface area of the IGBT can be reduced compared with the IGBT 700 of the conventional structure, and the area of the portion indicated by the oblique lines is reduced.

In this way, in the case of forming a lateral IGBT in a region with a limited area, the IGBT 100, 150 of Embodiment 1 has a smaller surface area (occupied area) and can lengthen the total channel width compared with the IGBT 700 of the conventional structure.

8 _shows collector-emitter _currents (I _CE ) characteristics. The horizontal axis represents the collector-emitter voltage (V _CE ), and the vertical axis represents the collector-emitter current (I _CE ). The measured temperature is room temperature.

As can be seen from Figure 8, when V _CE is gradually increasing, when V _CE is close to 6V, I _CE becomes about 0.4A, and it shows a saturation trend from around here, but the I _CE at this time is different from that of the traditional IGBT (See Figure 51) In comparison, the value is about 2 times larger. In addition, it can be seen that even when V _CE is from 0V to 6V, the on-resistance (V _CE /I _CE ) is lower than that of the conventional structure IGBT.

The improvement of their I _CE characteristics is due to the elongated total channel width compared with the conventionally structured IGBT 700 .

In addition, in Figs. 4 to 8, IGBT 150 is used for explanation, but the result is almost the same with IGBT 100.

Example 2

FIG. 9 is a top view of a lateral n-channel IGBT of Embodiment 2 of the present invention, generally indicated by 200 . In addition, FIG. 10 is a cross-sectional view of FIG. 9 viewed from the B-B direction. In Figs. 9 and 10, the same symbols as those in Figs. 1 and 2 denote the same or corresponding parts.

As shown in FIG. 10, the IGBT 200 takes an SOI structure in which, for example, a buried oxide film 20 composed of a silicon oxide film is formed between a p-type substrate 1 and an n layer 2. Other structures are the same as IGBT100. The structure of IGBT 200 shown in the top view of FIG. 9 is the same as that of IGBT 100 of FIG. 2 . In such a structure, the conductivity type of the substrate 1 can be selected independently of the conductivity type of the n ⁻ layer 2 .

FIG. 11 is a top view of another IGBT of the second embodiment, generally indicated by 250 . The structure is the same as that of IGBT 200 except that the p-type emitter layer 7 of the adjacent circular unit IGBT partially overlaps.

In addition, the IGBTs 100 and 150 of the first embodiment are called junction-separated types, and the IGBTs 200 and 250 of the second embodiment can be called insulator-separated types.

FIG. 12 shows the turn-off waveform of the IGBT 200 . The horizontal axis represents the off time, and the vertical axis represents the collector-emitter voltage (V _CE ) or the collector-emitter current (I _CE ). In FIG. 12 , (1v) (1c) represent changes in the V _CE value and _ICE value of the IGBT 100 of Example 1, and (2v) and (2c) represent the V _CE value and _ICE value of the IGBT 200 of Example 2. value changes.

In the IGBT 700 of the conventional structure shown in FIG. 35 , the fall time (tf: the time required for I _CE to change from 90% of the maximum value to 10%) is large and exceeds 1 μs. However, the IGBT of Example 2 (( See (2c)) becomes approximately 0.5 μs. Thus, in the IGBT of Example 2, compared with the conventional IGBT (Fig. 52), the switching speed is accelerated and the switching loss is reduced. In addition, when the resistance load is switched, the In the turn-off waveform, when V _CE rises, I _CE decreases at a rate of decrease approximately equal to the rate of increase and absolute value of V _CE .

Fig. 13 shows the current distribution (solid line), voltage distribution (dotted line) and the boundary line (dashed line) of the depletion region when the resistive load of the junction-separated lateral IGBT 100 of the first embodiment is switched off (10.6 μs), Corresponds to the sectional view of Figure 1.

In the case of the junction-separated lateral IGBT 100, the depletion layer expanded from the emitter side not only on the collector side but also on the p-type substrate side, and the potential distribution and current distribution are also distributed on the p-type substrate side. Therefore, the depletion toward the collector side is suppressed, and the rise of V _CE becomes relatively smooth. As a result, the corresponding decrease in _ICE becomes relatively stable.

FIG. 14 shows the hole distribution (indicated by a solid line) when the resistive load of the junction-separated lateral IGBT 100 of the first embodiment is switched off (10.6 μs), corresponding to the cross-sectional view of FIG. 1 .

The junction split lateral IGBT 100, as shown in FIG. 13, distributes a large number of holes in the n ^- layer and in the p-type substrate in order to suppress depletion from the emitter side to the collector side. If a large number of holes are distributed in the n ^- layer and in the p-type substrate, the fall time (tf) becomes relatively long because it takes time until the holes disappear.

15 shows (a) hole distribution, (b) electron distribution, and (c) concentration distribution in the equilibrium state when the resistive load of the junction-separated lateral IGBT 100 of the first embodiment is switched off (10.6 μs), n ^- Distribution from the collector side to the emitter side at a certain depth within the layer.

As shown in Fig. 13, in the junction-separated lateral IGBT 100, since the depletion from the emitter side to the collector side is suppressed, in the n ^- layer where the depletion layer does not expand, excess voids exceeding the equilibrium state concentration are distributed. holes and excess electrons. Excess holes and excess electrons are distributed in a large amount in the n-layer, so the time until the excess holes and excess electrons disappear from the n ^- layer becomes longer. Therefore, the fall time (tf) acceleration is limited compared to the conventionally structured IGBT 700 .

On the other hand, FIG. 16 shows the potential distribution (solid line), (b) current distribution (dotted line) and the boundary line of the depletion region ( Dot-dash line), corresponding to the sectional view of 10.

In the case of the insulator-separated lateral IGBT 200, due to the buried oxide film between the n ^- layer and the p-type substrate, the depletion layer expanded from the emitter side does not expand toward the p-type substrate, but in the n ^- layer toward the collector The electrode side is enlarged. Thus, within the p-type substrate, there is no current distribution and no potential distribution. Therefore, depletion toward the collector side increases, and V _CE rises. As a result, the corresponding _ICE also rises, and the fall time (tf) is accelerated.

FIG. 17 shows the hole distribution (indicated by a solid line) when the resistive load of the insulator-separated lateral IGBT 200 of Example 2 is switched off (10.6 μs), corresponding to the cross-sectional view of FIG. 10 .

The insulator-separated lateral IGBT 200, as shown in FIG. 16, has fewer holes distributed in the n ^- layer due to increased depletion from the emitter side to the collector side. Therefore, the time until the holes distributed in the n layer disappear is shortened, and the fall time (tf) is shortened.

Fig. 18 shows (a) hole distribution, (b) electron distribution and (c) concentration distribution in equilibrium state when resistive load switching of insulator-separated lateral IGBT 200 is turned off (10.6 μs), in the n ^- layer for a certain The depth distribution from the collector side to the emitter side.

In the insulator-split lateral IGBT 200, as described above, since the depletion progresses from the emitter side to the collector side, there are few regions where the depletion layer does not expand in the n ^- layer. Therefore, in the n ^- layer, there are few holes and electrons (excess holes, excess electrons) at a concentration higher than the equilibrium state. If there are fewer excess holes and electrons in the n ^- layer, the time until disappearance of the excess holes and electrons is shortened, and as a result, the fall time is accelerated (tf).

Therefore, in the IGBT 200 of the second embodiment, in addition to the improvement of the emitter current (I _CE ) characteristic that can be achieved by the IGBT 100 of the first embodiment, the fall time (tf) can be shortened.

In Figs. 16 to 18, the IGBT 200 was explained, but almost the same effect can be obtained with the IGBT 250 as well.

In addition, the structure in which the insulating film 20 is provided between the p-type substrate 1 and the n ^- layer 2 may also be suitable for an IGBT of a conventional structure.

Example 3

FIG. 19 is a cross-sectional view of a lateral n-channel IGBT according to Embodiment 3 of the present invention, generally indicated by 300 , as viewed from the same direction as A-A in FIG. 1 . In FIG. 19, the same symbols as those in FIG. 2 denote the same or corresponding parts.

In the IGBT 300 shown in FIG. 19, on the emitter side, a p ^- layer 30 narrower in width than the p-type base layer 5 and deeper than the p-type base layer 5 but not reaching the depth of the p-type substrate 1 is provided, connected to the bottom surface of the p-type base layer 5. Other structures are the same as those of IGBT 100 in FIG. 2 .

FIG. 20 is a cross-sectional view of another lateral n-channel IGBT according to Embodiment 3 of the present invention, generally indicated by 350 , showing the situation viewed from the same direction as the B-B direction in FIG. 9 . In FIG. 20 , the same symbols as those in FIG. 10 denote the same or corresponding parts.

In the IGBT 350 shown in FIG. 20 , on the emitter side, an electrode that is narrower than the width of the p-type base layer 5 (the length in the left-right direction in FIG. 20 ) and not deeper than the p-type base layer 5 is provided. The p ^- layer 30 buried to the depth of the insulating film 20 is connected to the bottom surface of the p-type base layer 5 . Other structures are the same as those of IGBT 200 in FIG. 10 .

21 is the current distribution (solid line), electric field distribution (dotted line) and depletion region boundary line (dotted line) when the resistance load of the insulator-separated lateral IGBT 200 of the above-mentioned embodiment 2 is switched off (10.6 μs), corresponding to The cross-sectional view in Figure 10.

In addition, Fig. 22 shows the current distribution (solid line), electric field distribution (dotted line) and depletion region boundary line (dashed line) when the resistive load of the insulator-separated lateral IGBT 350 of Embodiment 3 is switched off (10.6 μs). , corresponding to the cross-sectional view of Figure 20.

Referring to Fig. 21, it can be seen that in the case of the insulator separation structure provided with the buried insulating film, current flows through the n ^- layer immediately above the buried oxide film.

Therefore, by providing the p ^- layer under the p-type base layer, the hole current reaching the n ^- layer on the emitter side becomes easy to flow into the high electric field portion at the bottom of the p ^- layer.

Referring to Fig. 22 showing IGBT 350, the hole current flowing directly under the n-type emitter layer becomes smaller compared with IGBT 250 (Fig. 21). As a result, in the IGBT 350, compared with the IGBT 250, the operation of the parasitic semiconductor switching element is made difficult, and the latch-up tolerance is improved.

Furthermore, in IGBT 350, the width of the p ^- layer is narrower than that of the p-type base layer. Therefore, the hole current reaching the n ^- layer on the emitter side flows substantially upward through the p ^- layer toward the emitter electrode, and the fall time (tf) can be further shortened compared with the IGBT 250 without the p ^- layer.

Thus, in the IGBTs 300, 350 of this embodiment, by providing the p layer below the p-type, it is possible to shorten the fall time (tf) while preventing latch-up of the parasitic semiconductor switching element. In particular, in the IGBT 350 in which a buried insulating film is provided, a remarkable effect can be obtained.

In addition, the structure of setting the p ^- layer under the p-type base layer can also be applied to the IGBT of the traditional structure, and the same effect can be obtained.

Example 4

23 is a top view of a portion of a lateral n-channel IGBT of Embodiment 4 of the present invention, generally designated 400, showing an n-type emitter (n ⁺ ) layer 6 formed within a p-type base layer 5 (with The area where the emitter electrode is connected (emitter contact area)).

As shown in FIG. 23, in the IGBT 400, the n-type emitter layer 6 includes a plurality of protruding portions (bulge regions) 16 outward. As shown in FIG. 23 , the width ( W2 ) of the protruding portion 16 has a relationship of W1 > W2 with respect to the interval ( W1 ) between adjacent protruding portions 16 . Other structures are the same as IGBT100.

In addition, FIG. 24 is a sectional view of FIG. 23 viewed in the C-C direction, and FIG. 25 is a sectional view of FIG. 23 viewed in the D-D direction. In Figures 24 and 25, the hole flow when the IGBT is turned off and when it is turned on in a steady state is recorded simultaneously.

Here, the width of the n-type emitter layer in the cross-sectional view shown in FIG. 24 is substantially equal to the width of the n-type emitter layer 6 of the IGBT 100 shown in FIG. 1 . On the other hand, the width of the n-type emitter layer in the cross-sectional view shown in FIG. 25 is narrower than the width of n-type emitter layer 6 of IGBT 100 shown in FIG. 1 .

In Figure 25, the width of the n-type emitter (n ⁺ ) layer is narrowed, so the n-type emitter layer of the parasitic npn bipolar transistor formed in the n ^- layer/p-type base layer/n-type emitter layer The width of the p-type base layer immediately below becomes narrow, and the base resistance of the p-type base region decreases. As a result, the operation of the parasitic npn bipolar transistor can be suppressed, and the parasitic semiconductor switching element formed in the p-type collector layer/n-type buffer layer/n ⁺ layer/p-type base layer/n-type emitter layer can be prevented. atresia.

In this way, in the IGBT 400 of the fourth embodiment, the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT is turned off and turned on in a steady state.

In addition, in IGBT 400 , protruding portion 16 is a part of n-type emitter layer 6 , and since both are electrically connected, even with such a structure, the channel width is not smaller than that of IGBT 100 . Therefore, when a collector-emitter voltage (V _CE ) is applied while a constant gate-emitter voltage (V _GE ) is applied, the collector-emitter current (I _CE ) characteristic is the same as that of the IGBT 100 become good.

Furthermore, in the IGBT 400, the n-type emitter layer has a protruding portion, and its size becomes W1>W2 (see FIG. 23 ). That is, as shown in FIG. 26, the gate electrode lead wiring is arranged to pass between the two protrusions, and it is not necessary to cut the n-type emitter layer intersecting the gate electrode lead wiring as in the conventional structure. Therefore, it becomes possible to arrange the gate electrode lead-out wiring without reducing the channel width.

Therefore, when a collector-emitter voltage (V _CE ) is applied while a constant gate-emitter voltage (V _GE ) is applied, the collector-emitter current (I _CE ) characteristic becomes better.

In addition, the n-type emitter layer with such a structure can also be applied to an IGBT with a conventional structure.

27 is a top view of the arrangement of a p-type emitter layer (described as "P ⁺ " in FIGS. 24 and 25 ) relative to the n-type emitter layer of the lateral n-channel IGBT shown in FIG. 23 .

As shown in FIG. 27( a ), the p-type emitter layer may have a stripe shape surrounding the n-emitter layer.

In addition, as shown in Fig. 27(b) and (c), the p-type emitter layer may be formed in a ring shape along the n-type emitter layer. Here, (b) is a shape in which a predetermined interval is provided between the p-type emitter layer and the n-type emitter layer, and (c) is a shape in which the p-type emitter layer and the n-type emitter layer are connected.

In addition, as shown in FIG. 27( d ), the p-type emitter layer may not be continuously arranged along the n-type emitter layer.

In addition, such a form of the p-type emitter layer can also be applied to the p-type emitter layer shown in other examples.

Example 5

28 is a top view of a portion of a lateral n-channel IGBT of Embodiment 5 of the present invention, generally designated 500, showing the n-type emitter layer and the connection region (emitter contact region) of the emitter electrode. In addition, FIG. 29 is a cross-sectional view of the IGBT 500 of FIG. 28 viewed in the E-E direction.

In the IGBT 500 of Embodiment 5, on the IGBT 400 (FIG. 25), as shown in FIG. 28, the protruding portion of the n-type emitter layer has a front end portion in a T-shape, thereby enlarging the n-type emitter layer and The contact area of the emitter electrode wiring. Other structures are the same as IGBT 400.

The n-type emitter layer newly provided in IGBT 500, as shown in FIG. 29, is formed such that the width (the lateral length in FIG. 29) is narrowed. Therefore, in the parasitic npn bipolar transistor formed in the n ^- layer/p-type base region/n-emitter layer, the base resistance of the p-type base region immediately below the n-type emitter layer decreases. Therefore, the operation of the parasitic npn bipolar transistor is suppressed, and the latch-up of the parasitic semiconductor switching element formed in the p-type collector layer/n ^- type buffer layer/n- layer/p-type base layer/n-emitter layer can also be prevented . As a result, in the lateral n-channel IGBT 500 , the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT 500 is turned off and when it is turned on in a steady state.

Furthermore, in the IGBT 500, since the contact area of the n-type emitter layer and the electrode wiring increases, the contact resistance of the n-type emitter layer and the emitter electrode wiring decreases.

In this way, in the lateral n-channel IGBT 500 of Embodiment 5, for the IGBT of Embodiment 4, the protruding portion of the n-type emitter layer is T-shaped, thereby increasing the contact between the n-type emitter layer and the emitter electrode wiring. area, reducing the contact resistance of the n-type emitter layer and emitter electrode wiring. As a result, when a collector-emitter voltage (V _CE ) is applied while a constant gate-emitter voltage (V _GE ) is applied, the collector-emitter current (I _CE ) characteristic can be made improve.

In addition, the n-type emitter layer with such a structure can also be applied to an IGBT with a conventional structure.

Example 6

FIG. 30 is a top view of an IGBT that is a double combination of the IGBT 150 of Embodiment 1 and is generally designated by 600. In addition, FIG. 31 is a top view of a double combination of IGBT 700, an IGBT generally designated 650. In addition, FIG. 32 is a cross-sectional view of the IGBT 600 of FIG. 30 viewed in the F-F direction. In Figs. 30 and 31, the same symbols as those in Figs. 2 and 3 indicate the same or corresponding parts.

As indicated by oblique lines in Figures 30 and 31, in the IGBTs 600 and 650 of Embodiment 6, the common tangent line of two adjacent unit IGBTs is sandwiched between the two IGBTs and the adjacent 3 A p-type emitter layer 17 is provided on the region sandwiched between the unit IGBTs to increase the contact area between the p-type emitter layer and the emitter electrode wiring.

In such a structure, the p-emitter layer emitter layer 7 , 17 is relatively widened compared to the n-type emitter layer 6 . As a result, the contact resistance between the p-type emitter layers 7 and 17 and the emitter wiring can be reduced, and as shown in FIG. 32, holes do not stay directly under the n-type emitter layer, but smoothly flow to the p-type emitter. (p ⁺ ) layer and the contact region of the emitter wiring (emitter electrode). This is indirectly due to the reduced base resistance of the p-type base region directly below the n-type emitter layer.

Thus, suppressing the action of the parasitic npn bipolar transistor formed in the n-layer/p-type base layer/n-type emitter layer can prevent the p-type collector layer/n-type buffer layer/n ^- layer/p-type base layer/n-type emitter layer formed in the latch-up of parasitic semiconductor switching elements. As a result, in the lateral n-channel IGBT 600, the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT 600 is turned off and when it is turned on in a steady state.

Example 7

FIG. 33 is a cross-sectional view of a lateral n-channel IGBT according to Embodiment 7 of the present invention, generally indicated by 1100 , as viewed in the same direction as the A-A direction in FIG. 1 . In FIG. 33 , the same symbols as those in FIG. 19 denote the same or corresponding parts.

IGBT 1100 (see FIG. 33 ) of Embodiment 7, compared with IGBT 300 (see FIG. 19 ) of Embodiment 3, has a structure in which no p-type emitter layer 7 is provided, and has the same structure as IGBT 300 except that. In IGBT 1100, a p-type emitter is not provided, and the p-type base layer 5 also serves as a p-type emitter.

In addition, FIG. 34 is a cross-sectional view of another lateral n-channel IGBT of Embodiment 7 of the present invention, generally indicated by 1150, showing the situation viewed in the same direction as the A-A direction in FIG. 1 . In FIG. 34, the same symbols as those in FIG. 20 denote the same or corresponding parts. The structure of GBT1150 is formed by adding buried insulating film 20 to the structure of IGBT1100.

Compared with the IGBT 350 of the third embodiment (see FIG. 20 ), the IGBT 1150 of the seventh embodiment (see FIG. 34 ) has the same structure as the IGBT 350 except that the p-type emitter layer 7 is not provided. In the IGBT 1150, the p-type emitter is also not provided, and the p-type base layer 5 doubles as the p-type emitter.

In this way, in the IGBTs 1100 and 1150 of the seventh embodiment, the ^p- layer is provided under the p-type base layer, thereby preventing latch-up of the parasitic semiconductor switching element and shortening the fall time (tf). In particular, a remarkable effect can be obtained in the IGBT 1150 in which a buried insulating film is provided.

In addition, the p-type base layer 5 also serves as a p-type emitter, so that the structure can be simplified and the manufacturing process can be omitted.

Example 8

35 is a top view of a portion of a lateral n-channel IGBT, generally indicated by 1200, showing an embodiment 8 of the present invention, showing an n-type emitter (n ⁺ ) layer 6 formed in a p-type base layer 5 (with the emitter The area where the electrodes are connected (emitter contact area)).

Same as the IGBT 400 shown in FIG. 23, in the IGBT 1200, the n-type emitter layer 6 includes a plurality of outwardly protruding parts (protruding regions) 16, and the width (W2) of the protruding parts 16, for adjacent protruding The interval (W1) of the portion 16 has a relationship of W1>W2.

FIG. 36 is a cross-sectional view of FIG. 35 viewed from the C-C direction, and FIG. 37 is a cross-sectional view of FIG. 35 viewed from the D-D direction.

The IGBT 1200 of Embodiment 8 (see FIGS. 36 and 37), compared with the IGBT 400 of Embodiment 4 (see FIGS. 24 and 25), has a structure without a p-type emitter layer, and has the same structure as the IGBT 400 except that . In IGBT 1200, a p-type emitter is not provided, and the p-type base layer 5 also serves as a p-type emitter.

By providing such a structure, in the IGBT 1200 of the eighth embodiment, substantially the same effect as that of the above-mentioned IGBT 400 can be obtained. Moreover, the p-type base layer 5 also serves as a p-type emitter, so that the structure can be simplified and the manufacturing process can be reduced.

That is, in FIG. 37, the width of the n-type emitter (n ⁺ ) layer is narrowed, so the n of the parasitic npn bipolar transistor formed in the n ^- layer/P-type base layer/n-type emitter layer The width of the p-type base layer immediately below the p-type emitter layer is narrowed, and the base resistance of the p-type base region decreases. As a result, the operation of the parasitic npn bipolar transistor can be suppressed, and the parasitic semiconductor switching element formed in the p-type collector layer/n ^- type buffer layer/n- layer/p-type base layer/n-type emitter layer can be prevented atresia.

In this way, in the IGBT 1200 of the eighth embodiment, as in the IGBT 400, the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT is turned off and turned on in a steady state.

Example 9

38 is a top view of a part of a lateral n-channel IGBT, generally indicated at 1300, showing Embodiment 9 of the present invention, showing the connection region (emitter contact region) of the n-type emitter layer and the emitter electrode. In addition, FIG. 39 is a cross-sectional view of the IGBT 1300 of FIG. 38 viewed in the E-E direction.

The IGBT 1300 of Embodiment 9 (see FIGS. 38 and 39), compared with the IGBT 500 of Embodiment 5 (see FIGS. 28 and 29), has a structure without a p-type emitter layer, and has the same structure as the IGBT 500 except that . In the IGBT 1300, the p-type emitter is not provided, and the p-type base layer also serves as the p-type emitter.

By providing such a structure, in the IGBT 1300 of the ninth embodiment, substantially the same effect as that of the above-mentioned IGBT 500 can be obtained. Moreover, the p-type base layer 5 also serves as a p-type emitter, so that the structure can be simplified and the manufacturing process can be reduced.

That is to say, in IGBT 1300, for the IGBT of Example 4, the protruding part of the n-type emitter layer is set in a T-shape, thereby increasing the contact area between the n-type emitter layer and the emitter electrode wiring, and reducing the n-type emitter layer. layer and the contact resistance of the emitter electrode wiring. As a result, when a constant gate-emitter voltage (V _CE ) is applied, collector-emitter current (I _CE ) characteristics can be improved when a collector-emitter voltage (V _CE ) is applied. .

Example 10

FIG. 40 is a top view of the lateral n-channel IGBT of the tenth embodiment, generally indicated by 1400, and the same symbols as those in FIG. 30 denote the same or corresponding parts. In addition, FIGS. 41 to 43 are enlarged views of a part marked A in FIG. 40 .

In the IGBT 1400 of the tenth embodiment, in the area sandwiched between the common tangent line of two adjacent unit IGBTs and the two IGBTs, a p-type emitter layer 17 is provided, and the p-type emitter layer and the emitter electrode are enlarged. The area of the contact region (emitter contact region) of the wiring (represents the emitter contact region in FIGS. 41 to 43). Therefore, the same effect as that of the IGBT 650 (see FIG. 31 ) of the above-mentioned Embodiment 6 can be obtained.

That is, it is possible to suppress the action of the parasitic npn bipolar transistor formed in the n ^- layer/p-type base layer/n-type emitter layer, preventing the p-type collector layer/n-type buffer layer/n ^- layer/p-type Latch-up of parasitic semiconductor switching elements formed in the base layer/n-type emitter layer. As a result, in the lateral n-channel IGBT 1400, the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT 1400 is turned off and when it is turned on in a steady state.

As shown in FIGS. 40 and 41, in the IGBT 1400, the n-type emitter layer 6 may also be disposed discontinuously along the p-type base layer 5. In addition, although not shown in the figure, endless continuous configuration is also possible.

In addition, as shown in FIG. 42, in the IGBT 1400, the n-type emitter layer 6 can also be made into an endless structure provided with a plurality of outwardly protruding parts (protruding regions).

In addition, as shown in FIG. 43, the structure of FIG. 42 may be a structure in which no p-type emitter layer 7 is provided.

In this way, the p-type emitter layer 17 provided on the IGBT 1400 of this embodiment can be formed regardless of the shape of the n-type emitter layer 6 and the presence or absence of the p-type emitter layer 7, so that in the IGBT 1400, it is possible to improve Latch-up tolerance of parasitic semiconductor switching elements during turn-off and steady-state turn-on.

Fig. 44 is a top view of another lateral n-channel IGBT of the tenth embodiment, generally indicated by 1500, and the same symbols as those in Fig. 30 indicate the same or corresponding parts. In addition, FIGS. 45 to 47 are enlarged views of a portion indicated by the symbol B in FIG. 44 .

In IGBT 1500, the p-type emitter layer 17 is set on the common tangent of two adjacent unit IGBTs and the area sandwiched by two IGBTs, and the area sandwiched by three adjacent unit IGBTs, increasing the p The area of the region (emitter contact region) where the type emitter layer and the emitter electrode wiring are in contact (represents the contact region in FIGS. 45 to 47). Accordingly, the same effect as that of the IGBT 600 (see FIG. 30 ) of the sixth embodiment described above can be obtained.

That is, the action of the parasitic npn bipolar transistor formed in the n ^- layer/p-type base layer/n-type emitter layer can be suppressed, preventing Latch-up of parasitic semiconductor switching elements formed by the base layer/n-type emitter layer. As a result, in the lateral n-channel IGBT 1500, the latch-up tolerance of the parasitic semiconductor switching element is improved when the IGBT 1500 is turned off and when it is turned on in a steady state.

As shown in FIGS. 44 and 45, in the IGBT 1500, the n-emitter layer 6 can also be arranged discontinuously along the p-type base layer 5. In addition, although not shown in the figure, it is also possible to take an endlessly continuous configuration.

Furthermore, as shown in FIG. 46, in the IGBT 1500, the n-type emitter layer 6 may also take an endless structure provided with a plurality of outwardly protruding portions (protruding regions).

In addition, as shown in FIG. 47 , a structure in which no p-type emitter layer 7 is provided may be adopted in the structure of FIG. 46 .

With such a structure, the p-type emitter layers 7 and 17 are relatively wider than the n-type emitter layer 6 . As a result, the contact resistance between the p-type emitter layers 7, 17 and the emitter wiring can be reduced, and as shown in FIG. Directly below, it flows smoothly to the contact region of the p-type emitter (p ⁺ ) layer and the emitter wiring (emitter electrode). This is indirectly due to the reduced base resistance of the p-type base region directly below the n-type emitter layer.

Thereby, the action of the parasitic npn bipolar transistor formed in the n ^- layer/p-type base layer/n-type emitter layer can be suppressed, preventing the p-type collector layer/n-type buffer layer/n ^- layer/p-type base Latch-up of parasitic semiconductor switching elements formed in the electrode layer/n-type emitter layer. As a result, in the lateral n-channel IGBT 1500, the latch-up resistance of the parasitic semiconductor switching element is improved when the IGBT 1500 is turned off and when it is turned on in a steady state.

In addition, in Embodiments 1 to 10, a lateral n-channel IGBT was described, but the present invention can also be applied to a lateral p-channel IGBT. In this case, the p-type and n-type in the description of Embodiments 1 to 10 above are interchanged.

In addition, the present invention can also be applied to lateral MOSFETs and lateral devices with other MOS gate structures.

Claims (8)

1. a lateral semiconductor devices of being made up of a plurality of elemental semiconductor elements is characterized in that,

Each elemental semiconductor element is made up of IGBT, and it comprises:

The Semiconductor substrate of the 1st conductivity type;

Be arranged on the semiconductor region of the 2nd conductivity type on this Semiconductor substrate;

Be arranged on the collector layer of the 1st conductivity type in this semiconductor region;

In this semiconductor region, separate with this collector layer, be provided with to such an extent that surround annular the 1st conductivity type base layer of this collector layer; And

Be arranged in this base layer, the 1st emitter layer of Pei Zhi the 2nd conductivity type ringwise,

Charge carrier between the 1st emitter layer and this collector layer moves, controls with the channel region that is formed on this base layer,

Each elemental semiconductor element is provided with adjacent one another arely,

Above-mentioned the 1st emitter layer is formed by annular and continuous body region with from the outwards outstanding protrusion district of this body region, in protruding the district, is connected with emitter electrode,

Extend along the radial direction in aforementioned body district in above-mentioned protrusion district, roughly configuration equidistantly around this body region, and adjacent two intervals (W1) of protruding the district are than this width (W2) that protrudes the district (W1＞W2) greatly.

2. a lateral semiconductor devices of being made up of a plurality of elemental semiconductor elements is characterized in that,

Each elemental semiconductor element is made up of IGBT, and it comprises:

Semiconductor substrate;

Be arranged on the 2nd conductive-type semiconductor area on this Semiconductor substrate;

Be arranged on the collector layer of the 1st conductivity type in this semiconductor region;

In this semiconductor region, separate, be provided with to such an extent that surround annular the 1st conductivity type base layer of this collector layer with this collector layer; And

Be arranged in this base layer, the 1st emitter layer of Pei Zhi the 2nd conductivity type ringwise,

Charge carrier between the 1st emitter layer and this collector layer moves, controls with the channel region that is formed on this base layer,

Each elemental semiconductor element is provided with adjacent one another arely,

And, between this Semiconductor substrate and this semiconductor region, dielectric film is set,

Above-mentioned the 1st emitter layer is formed by annular and continuous body region with from the outwards outstanding protrusion district of this body region, in protruding the district, is connected with emitter electrode,

Extend along the radial direction in aforementioned body district in above-mentioned protrusion district, roughly configuration equidistantly around this body region, and adjacent two intervals (W1) of protruding the district are than this width (W2) that protrudes the district (W1＞W2) greatly.

3. claim 1 or 2 described lateral semiconductor devices is characterized in that,

Above-mentioned the 1st emitter layer forms continuous annular.

4. claim 1 or 2 described lateral semiconductor devices is characterized in that,

The 2nd emitter layer of the 1st conductivity type is set, to surround above-mentioned the 1st emitter layer in the aforementioned base layer.

5. claim 1 or 2 described lateral semiconductor devices is characterized in that,

In above-mentioned semiconductor region, the zone of the 1st conductivity type is set, to be connected with aforementioned base layer bottom surface.

6. claim 1 or 2 described lateral semiconductor devices is characterized in that,

End in above-mentioned protrusion district is included in the end regions that aforementioned body district tangential direction is extended, and this end regions is connected to above-mentioned emitter electrode.

7. the described lateral semiconductor devices of claim 4 is characterized in that,

In the tangent line area surrounded common, the zone of the 1st conductivity type is set by above-mentioned the 2nd emitter layer that is contained in two adjacent said units semiconductor elements respectively and two the 2nd emitter layers.

8. the described lateral semiconductor devices of claim 4 is characterized in that,

In by above-mentioned the 2nd emitter layer area surrounded that is contained in respectively in 3 said units semiconductor elements adjacent one another are, the zone of the 1st conductivity type is set.

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