CN1983225A - Device and method for transmitting data in asynchronous clock domain - Google Patents

Abstract

The invention discloses a device for transmitting data in an asynchronous clock domain and a method for transmitting data in an asynchronous clock domain. Wherein the sender is located in the data-associated clock domain, and the receiver is located in the system work clock domain, the method includes the following steps: A. The sender buffers the data in the storage unit when the write enable signal is effective, and simultaneously generates a data-ready The indication signal is sent to the receiver; B. The receiver generates a data indication signal when detecting the edge of the data ready indication signal; C. Adjusts the phase of the first counter according to the data indication signal, and at the phase of the first counter Data is read from the memory cell when a preset phase is reached. The invention realizes the stable transmission of data between asynchronous clock domains, and controls the transmission delay error within one clock cycle of the receiver, so that the absolute error can be effectively reduced only by increasing the frequency of the receiver's system working clock value.

Description

A device and method for transmitting data in an asynchronous clock domain

technical field

The invention relates to the technical field of data transmission, in particular to a device and method for transmitting data in an asynchronous clock domain.

Background technique

In most systems, data is transmitted between different boards in a serial manner, while asynchronous clocks are used between different boards. However, even if the asynchronous clocks of different boards have the same source, because they are obtained through different phase-locked loops (PLL) or different channels, the respective clock signal jitters (Jitter) are different, and in any There will be a frequency difference in a short period of time, but the long-term statistical results show that they are synchronized to the clock source, so two clocks on different boards will have phase drift within a certain period of time, and the maximum value of the phase drift depends on The quality of components such as clock sources and PLLs.

Most systems today use first-in-first-out memory (FIFO) to transfer data between two clock domains. A typical FIFO is a dual-port access memory. As shown in Figure 1, the FIFO includes a storage unit, a write address counter, a read address counter, a write address Gray code generator, a read address Gray code generator, and empty detection and overflow detection logic. . The storage unit is used to cache data, which can be realized by random access memory (RAM) or registers. Its depth determines the maximum clock jitter, phase drift and frequency fluctuation that the FIFO can tolerate; the write address counter and read address counter are used to generate The address of the access storage unit, they are loop counters, that is, the address counts to the maximum address of the storage unit and starts counting again from 0; the write address Gray code generator and the read address Gray code generator, each time a data is written or read When there is one piece of data, the gray code of the write address and the gray code of the read address are increased by 1, and the gray code of the write address or the gray code of the read address is input into the empty detection and overflow detection logic; the empty detection and overflow detection logic is based on the gray code of the write address and the read address Gray code and the upcoming read and write operations are used to determine whether the FIFO has been emptied or overflowed, and a signal for clearing or overflow indication is sent, and the read and write control terminal makes corresponding operations according to these signals, such as stopping writing or stopping reading.

FIFO can stably transmit data from one clock domain to another clock domain when the frequency deviates or the jitter and phase drift of the read and write clocks occur. However, when any of the read and write ports of the FIFO is abnormal and the read and write addresses jump, the FIFO cannot detect it, and it is impossible to adjust the transmission delay of the data in the FIFO, so the FIFO cannot meet the requirements for the transmission delay. error-sensitive applications.

Contents of the invention

In view of this, the present invention proposes a device for transmitting data in asynchronous clock domains, the purpose of which is to effectively control transmission delay errors while realizing stable data transmission between asynchronous clock domains. Another object of the present invention is to provide a method for transmitting data in an asynchronous clock domain.

According to the above purpose, the present invention provides a device for transmitting data in an asynchronous clock domain, the device includes: a storage unit for caching data; a write data terminal for caching data in the storage unit when the write enable signal is valid Middle; the data ready indication signal generation circuit is used to generate the data ready indication signal when the write enable signal is effective; the edge detection circuit is used to detect the edge of the data ready indication signal generated by the data ready indication signal generation circuit, The data indication signal is generated when the edge of the data ready indication signal; the phase monitoring and data acquisition phase generator including the first counter is used to adjust the phase of the first counter according to the data indication signal, and when the phase of the first counter reaches A data acquisition enable signal is generated at a preset phase; the read data terminal is used to read data from the storage unit according to the data acquisition enable signal generated by the phase monitoring and data acquisition phase generator; among them, the write data terminal and the data ready indication The signal generation circuit works in the data follow-up clock domain, and the edge detection circuit, phase monitoring and data acquisition phase generator, and the data read terminal work in the system working clock domain.

The device further includes a signal delay circuit located between the data-ready indication signal generation circuit and the edge detection circuit, configured to latch the data-ready indication signal for at least two clock cycles and input it to the edge detection circuit.

The signal delay circuit is composed of a plurality of D flip-flops connected in series.

The data ready indication signal generation circuit includes a first selector, a second selector, a D flip-flop and a delayer. Wherein, the 1 input terminal of the first selector is input into 0, the 0 input terminal is connected with the output terminal of the D flip-flop, the control terminal is connected with the output terminal of the delayer, and the output terminal is connected with the 0 terminal of the second selector. The input terminal is connected; the 1 input terminal of the second selector is input to 1, the 0 input terminal is connected to the output terminal of the first selector, the control terminal is input with a write enable signal, and the output terminal is connected to the D input of the D flip-flop The D input terminal of the D flip-flop is connected with the output terminal of the second selector, and the output terminal is connected with the edge detection circuit, the 0 input terminal of the first selector and the input terminal of the delayer; The input terminal of the delayer is connected with the output terminal of the D flip-flop, and the output terminal is connected with the control terminal of the first selector.

The delayer is composed of a plurality of D flip-flops connected in series, or is a counter that waits for multiple clock cycles to output signals.

The phase monitoring and data acquisition phase generator further includes a third selector, a fourth selector, a fifth selector, a first D flip-flop, a second D flip-flop, and a second counter. Wherein, the 1 input terminal of the third selector is input to 1, the 0 input terminal is connected to the output terminal of the first D flip-flop, the control terminal is input to the data indication signal, and the output terminal is connected to the D input terminal of the first D flip-flop connected; the 1 input terminal of the fourth selector is input to the data indication signal, the 0 input terminal is input 0, the control terminal is connected to the output terminal of the first counter, and the output terminal is connected to the input terminal of the fifth selector; the fifth The 1 input terminal of the selector is input with the data indication signal, the 0 input terminal is connected to the output terminal of the fourth selector, the control terminal is connected to the output terminal of the first D flip-flop, and the output terminal is connected to the clearing terminal of the first counter connected; the D input terminal of the first D flip-flop is connected with the output terminal of the third selector, and the output terminal is connected with the 0 input terminal of the third selector, the control terminal of the fifth selector and the enabling terminal of the first counter; The D input end of the second D flip-flop is connected to the output end of the first counter, the enable end is input to the data indication signal, and the output end is connected to the clear end of the second counter; the clear end of the first counter is connected to the first counter. The output terminals of the five selectors are connected, the enabling terminal is connected with the output terminal of the first D flip-flop, the output terminal is connected with the control terminal of the fourth selector and the D input terminal of the second D flip-flop, and the output terminal of the first counter Output data acquisition enabling signal; the clearing terminal of the second counter is connected with its output terminal and the output terminal of the second D flip-flop, the enabling terminal is input with the data indication signal, and the output terminal is connected with its clearing terminal.

The storage unit is a random access storage unit or a register.

The present invention also provides a method for transmitting data in the asynchronous clock domain, wherein the sender is located in the data-associated clock domain, and the receiver is located in the system working clock domain and includes a first counter. The method includes the following steps: A. When the write enable signal is valid, the data is cached in the storage unit, and a data ready indication signal is generated and sent to the receiver; B. The receiver generates a data indication signal when detecting the edge of the data ready indication signal; C. Adjusting the phase of the first counter according to the data indication signal, and reading data from the storage unit when the phase of the first counter reaches the set phase.

The step before step B further includes the step of latching the data ready indication signal for more than one clock cycle.

The step of adjusting the phase of the first counter according to the data indication signal in step C includes: judging whether the current phase of the first counter is equal to its maximum phase when the data indication signal arrives, and if not, judging whether the current phase Whether the absolute value of the difference from the maximum phase is greater than 1, if greater than 1, when the next data indication signal arrives, trigger the first counter to count again, if less than or equal to 1, then when multiple consecutive data indication signals arrive When the difference between the current phase of the first counter and its maximum phase remains unchanged, the first counter is triggered to count again.

The step of reading data from the storage unit when the phase of the first counter reaches the set phase described in step C includes: generating a data acquisition enable signal when the phase of the first counter reaches the preset phase; The acquisition enable signal reads data from the storage unit.

It can be seen from the above technical solution that since the present invention adopts the method of transmitting the data indication signal to realize the locking of the time data phase of the asynchronous clock domain, thereby realizing the stable transmission of data between the asynchronous clock domains, and controlling the transmission delay error within Within one clock cycle of the receiving side, the absolute value of the error can be effectively reduced only by increasing the frequency of the working clock of the receiving side system. Compared with the FIFO in the prior art, it does not need complex gray code conversion and judgment of overflow clearing, and the implementation is relatively simple.

Description of drawings

FIG. 1 is a schematic structural diagram of a FIFO in the prior art.

Fig. 2 is a schematic structural diagram of the device in the embodiment of the present invention.

FIG. 3 is a timing diagram of various signals in the embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a phase generator for phase monitoring and data acquisition in the device of the embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the following examples are given to further describe the present invention in detail.

With reference to Fig. 2, the device that the present invention adopts comprises writing data end, storage unit, data ready indication signal generation circuit, signal delay circuit, edge detection circuit, phase monitoring and data acquisition phase generator, and read data end. Among them, the sender's write data terminal and data ready indication signal generation circuit work in the data follower clock domain Clk_in, and the receiver's signal delay circuit, edge detection circuit, phase monitoring and data acquisition phase generator, and read data terminal all work Work in the system clock domain Clk_sys. The structure and function of each part are introduced respectively below.

The write data terminal includes a D flip-flop, and when the write enable signal Data_wt_en is valid, write data Data_in, that is, cache the data in the storage unit.

The storage unit is a RAM or a register, which is used to cache data input from the write data end, and read and output the data by the read data end.

The data ready indication signal generation circuit generates a data ready indication signal Data_rdy according to the write enable signal Data_wt_en, and the signal Data_rdy is used to notify the receiver that the current data is ready. In order to ensure that the Data_rdy signal is collected in the system working clock domain, the high and low level pulse width of the Data_rdy signal must be greater than the width of one clock cycle in the system working clock domain. Referring to Fig. 3, the high and low level pulse width of the Data_rdy signal shown in Fig. 3 is much larger than the width of one clock cycle of the system working clock domain Clk_sys, which ensures that the modules in the system working clock domain can collect the Data_rdy signal.

Continuing to refer to Fig. 2, this data-ready indication signal generating circuit comprises two alternative selectors, a D flip-flop and a delayer, and the two alternative selectors are the first selector and the second selector. Selector. Among them, the first selector and the second selector respectively output the signal of the 0 input terminal or the 1 input terminal according to the control signal of the control terminal of itself as 0 or 1; the input signal of the D flip-flop at the enable terminal (En terminal) is valid , output the input of the D terminal, when there is no input signal at the En terminal, output the input signal of the D terminal in the previous clock cycle; the delayer is used to delay the Data_rdy signal for N clock cycles, and it can be triggered by N serially connected D It can also be implemented by a counter that outputs an input signal after waiting for N clock cycles. In the data-ready indication signal generating circuit, the 1 input terminal of the first selector is input to 0, the 0 input terminal is connected to the output terminal of the D flip-flop, the control terminal is connected to the output terminal of the delayer, and the output terminal It is connected with the 0 input terminal of the second selector; the 1 input terminal of the second selector is input with 1, the 0 input terminal is connected with the output terminal of the first selector, the control terminal is input with the write enable signal, and the output terminal is connected with all The D input end of the D flip-flop is connected; the D input end of the D flip-flop is connected with the output end of the second selector, and the output end is connected with the edge detection circuit, the 0 input end of the first selector, and the delay The input end of the timer is connected; the input end of the delayer is connected with the output end of the D flip-flop, and the output end is connected with the control end of the first selector.

In the working process, the first selector 1 input terminal is input 0, the 0 input terminal is input Data_rdy signal, and according to the control of the Data_rdy signal delayed by the counter for N clock cycles, the signal is output to the 0 input terminal of the second selector, The 1 input of the second selector is 1, it outputs a signal to the D flip-flop according to the write enable signal Data_wt_en, and then the D flip-flop outputs to the signal delay circuit, the 0 input of the first selector, and the counter as a delayer Data_rdy signal.

The signal delay circuit is used for latching the Data_rdy signal for at least two system working clock domain clock cycles and then inputting it into the edge detection circuit, the purpose of which is to reduce the occurrence probability of metastable states as much as possible. The signal delay circuit here is realized by connecting multiple D flip-flops in series. The signal delay circuit shown in Fig. 2 includes 3 D flip-flops, after latching the Data_rdy signal for three clock cycles, it is input to the edge detection circuit.

The edge detection circuit is used to detect the edge of the Data_rdy signal. When the rising edge of Data_rdy is detected, the data indication signal Data_rdy_sync in the system clock domain is generated. The Data_rdy_sync signal has only one clock cycle width. This embodiment adopts the method of comparing the current Data_rdy signal with the Data_rdy signal before one clock cycle to detect the edge of the Data_rdy signal, that is, comparing the signal before the last D flip-flop of the signal delay circuit (the Data_rdy signal before one clock cycle) and The subsequent signal (the current Data_rdy signal), obviously when the current Data_rdy signal is 1 and the Data_rdy signal before one clock cycle is 0, the Data_rdy signal has a rising edge, and then the Data_rdy_sync signal is generated according to the rising edge, and the Data_rdy_sync signal is input to the phase monitor and data acquisition phase generator.

The phase monitoring and data acquisition phase generator is used to control the transmission delay within one clock cycle, and generate a data acquisition enable signal Data_sample_en, and input the Data_sample_en signal to the read data terminal. As shown in Figure 3, the generated Data_sample_en signal is just in the middle of the two change points before and after the data buffer register signal Data_tmp, so that the impact of the jitter and phase drift between the asynchronous clock domains on the data transmission is minimized. The jitter and phase drift between asynchronous clock domains can be equivalent to the left and right movement of Clk_sys relative to the stable Clk_in. Obviously, collecting data at the middle moment of the data change can obtain the most stable transmission effect.

As shown in Figure 4, the phase generator for phase monitoring and data acquisition includes counter A (the first counter), counter B (the second counter), and three selectors and two D triggers that assist them in realizing their functions. The three alternative selectors are the third selector, the fourth selector and the fifth selector, and the two D flip-flops are the first D flip-flop and the second D flip-flop. Wherein, the 1 input terminal of the third selector is input to 1, the 0 input terminal is connected to the output terminal of the first D flip-flop, the control terminal is input to the data indication signal, and the output terminal is connected to the D input terminal of the first D flip-flop connected; the 1 input terminal of the fourth selector is input to the data indication signal, the 0 input terminal is input 0, the control terminal is connected to the output terminal of the counter A, and the output terminal is connected to the input terminal of the fifth selector; the fifth selector The 1 input terminal of the device is input with the data indication signal, the 0 input terminal is connected with the output terminal of the fourth selector, the control terminal is connected with the output terminal of the first D flip-flop, and the output terminal is connected with the clearing terminal of the counter A; The D input terminal of the first D flip-flop is connected with the output terminal of the third selector, and the output terminal is connected with the 0 input terminal of the third selector, the control terminal of the fifth selector and the enabling terminal of the counter A; the second D The D input terminal of the flip-flop is connected to the output terminal of the counter A, the enabling terminal is input to the data indication signal, and the output terminal is connected to the clearing terminal of the counter B; the clearing terminal of the counter A is connected to the output terminal of the fifth selector connected, the enabling end is connected to the output end of the first D flip-flop, the output end is connected to the control end of the fourth selector and the D input end of the second D flip-flop, and the output end of the counter A outputs a data acquisition enabling signal; The clearing terminal of the counter B is connected to its output terminal and the output terminal of the second D flip-flop, the enable terminal is input with the data indication signal, and the output terminal is connected to its clearing terminal.

Counter A starts counting according to the Receive_start signal indicating the start of receiving data when the first Data_rdy_sync signal arrives, that is, it is cleared to start counting. As shown in Figure 4, the above-mentioned Receive_start signal is generated by the third selector and the first D flip-flop according to the Data_rdy_sync signal, the input terminal of the third selector 1 is input 1, and the input terminal 0 is input Receive_start signal, according to the control of the Data_rdy_sync signal to The first D flip-flop inputs a corresponding signal, and the first D flip-flop outputs a Receive_start signal, which is respectively input to the 0 input terminal of the third selector, the enable terminal of the counter A, and the control terminal of the fifth selector.

The counting cycle PH_A of the counter A is equal to the number of clock cycles corresponding to the cycle of the input data in the system working clock domain. The counter A also generates a data acquisition enabling signal Data_sample_en at a fixed phase CON_A, wherein CON_A is pre-selected and set. In order to meet the aforementioned condition that Data_sample_en is in the middle of the two change points before and after Data_tmp, it is better to set CON_A Set to about half of PH_A. In addition, when the counter A still satisfies the following logic expression (1), it outputs a Phase_error signal, and the Phase_error signal is used to control the clearing of the counter A.

{(|Cnt_A-PH_A|＞1)‖(|Cnt_A-PH_A|＝1&&Cnt_B＞＝CON_B)}&&Data_rdy_sync＝＝1 (1)

In the logical expression (1), |Cnt_A-PH_A|>1 means that when the Data_rdy_sync signal arrives, if the absolute value of the phase difference between the phase Cnt_A of the counter A and the counting period PH_A of the counter A is greater than one clock period. |Cnt_A-PH_A|=1&&Cnt_B>=CON_B indicates that the absolute value of the phase difference between the phase Cnt_A of the counter A and the counting period PH_A of the counter A when the Data_rdy_sync signal arrives is counted by the counter B, and the continuous events of which the phase difference is equal to 1 clock period are counted, and The case where the phase Cnt_B of the counter B is greater than or equal to the preset CON_B. Data_rdy_sync==1 indicates that the current Data_rdy_sync signal is valid, that is, when Data_rdy_sync arrives. To sum up, the logical expression (1) represents a situation where one of the above two situations occurs and Data_rdy_sync is valid.

Referring to Figure 4, the Phase_error signal clears the counter A through the fourth selector and the fifth selector. The 1 input of the fourth selector is input to Data_rdy_sync, and the 0 input is input to 0. According to the control of Phase_error, the first The 1 input terminal of the five selectors inputs the corresponding signal; the 0 input terminal of the fifth selector is input with the Data_rdy_sync signal, which inputs a control signal to the clearing terminal of the counter A according to the control of the above Receive_start signal, and controls the counter A to be cleared. The priority of the clear terminal clr of the counter A is higher than that of the enable terminal en, and the high level is effective.

Counter B is used to count whether the phase difference between the phase Cnt_A of counter A and the counting period PH_A of counter A is equal to 1 when all Data_rdy_sync arrives within a given time of CON_B data samples, and the value of counter A every time all equal. If it is, counter B will continue to accumulate until the value of counter B is equal to the preset CON_B, then stop and clear counter A, which is realized by the above-mentioned Phase_error signal; if not, counter B is cleared, which is cleared by the following Signal realization, that is, the counter B outputs a clear signal when the following logic expression (2) is satisfied, and the clear signal is input to the clear terminal of the counter B to clear the counter B. The priority of the clear terminal clr of the counter B is higher than that of the enable terminal en, and the high level is effective.

Cnt_A! ＝Cnt_A_back&&|Cnt_A-PH_A|＝＝1&&Data_rdy_sync＝＝1 (2)

In logical expression (2), Cnt_A! =Cnt_A_back indicates that the phase Cnt_A_ of the counter A when the current Data_rdy_sync arrives is different from the phase Cnt_A_back of the counter A when the last Data_rdy_sync arrived; |Cnt_A-PH_A|==1 indicates that the phase Cnt_A of the counter A and the count of the counter A when the Data_rdy_sync arrives The case where the absolute value of the phase difference of the period PH_A is 1; Data_rdy_sync==1 indicates that the current Data_rdy_sync signal is valid, that is, when Data_rdy_sync arrives. To sum up, the above logical expression (2) represents a situation where the above two conditions are satisfied simultaneously and Data_rdy_sync is valid.

The phase monitoring and data acquisition phase generator works as follows:

Step 10, counter A starts counting when the first Data_rdy_sync arrives.

Step 20, when each subsequent Data_rdy_sync signal arrives, the counter A judges whether its own phase is equal to the maximum value of the counting cycle, if yes, it means normal, and the counter A continues to count; otherwise, execute step 30.

Step 30, the counter A judges whether the absolute value of the difference between its own phase and the maximum value of the counting cycle is greater than one clock cycle, if it is greater than one clock cycle, it indicates that an abnormal state has occurred so that the phase has a large jump, then in the next When the Data_rdy_sync signal arrives, the phase of the counter A is updated immediately, that is, the counter A is cleared and counted again, and the interval of the Data_out of the output data at this time changes. If the absolute value of the difference between the two is less than or equal to one clock period, execute step 40. At this time, there are two possibilities: 1. The clocks of the two clock domains are in a normal state, and this error is caused by jitter; 2. The clock domains of the two clock domains are in a normal state. The phase of at least one of the clocks has shifted.

Step 40, use the counter B to count whether the phases of the corresponding counter A when Data_rdy_sync arrives in a continuous period of time (that is, the above-mentioned CON_B data sampling points) are all equal to the same value, if so, it means that the data phase has changed, and in the next When Data_rdy_sync arrives, update the phase of counter A, that is, clear and restart counting; otherwise, clear counter B and execute step 2 to restart the judgment.

In the above process, when the phase of the counter A is equal to the preset CON_A, the data acquisition enable signal Data_sample_en is generated and input to the read data terminal.

The read data terminal reads data from the storage unit and outputs it when the data acquisition enable signal Data_sample_en is valid.

The process of using the above-mentioned device of the present invention to transmit data in the asynchronous clock domain is as follows:

Step 100, when the write enable signal Data_wt_en is valid, cache the data in the storage unit, and generate a data ready indication signal Data_rdy and send it to the receiver;

Step 200, the receiver delays the data ready indication signal Data_rdy by at least two clock cycles, then performs edge detection on it, and generates the data indication signal Data_rdy_sync when the rising edge of the data ready indication signal is detected;

Step 300, when the data indication signal Data_rdy_sync arrives, judge the relationship between the phase Cnt_A of the counter A and the counting period PH_A of the counter A at this time,

When the counter A phase Cnt_A is equal to its counting period PH_A, that is, when the difference between the two is equal to zero, the counter A counts normally, and generates a data acquisition enable signal Data_sample_en when the phase of the counter A reaches the preset phase CON_A;

When the absolute value of the difference between the two is greater than one clock cycle of the system working clock domain, the counter A is cleared and counted again when the next Data_rdy_sync arrives. During this period, the data acquisition enable signal Data_sample_en is generated when the phase of the counter A reaches the preset phase CON_A;

In the case where the absolute value of the difference between the two is less than or equal to one clock cycle, it is further judged whether the phase of counter A is equal to the same value when the CON_B consecutive Data_rdy_sync signal arrives, and if so, counter A is set when the next Data_rdy_sync arrives Clear and re-count; otherwise, clear counter B and perform step C to re-judge. During this period, the data sampling enable signal Data_sample_en is generated when the phase of the counter A reaches the preset phase CON_A.

In step 400, the data read terminal reads data from the storage unit according to the data acquisition enabling signal.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (11)

1. A device for transmitting data in an asynchronous clock domain, characterized in that the device comprises: storage unit for caching data; Write data terminal, used to cache data in the storage unit when the write enable signal is valid; A data-ready indication signal generating circuit is used to generate a data-ready indication signal when the write enable signal is valid; The edge detection circuit is used to detect the edge of the data ready indication signal generated by the data ready indication signal generating circuit, and generates the data indication signal when the edge of the data ready indication signal is detected; A phase monitoring and data acquisition phase generator including a first counter is used to adjust the phase of the first counter according to the data indication signal, and generate a data acquisition enabling signal when the phase of the first counter reaches a preset phase; The read data terminal is used to read data from the storage unit according to the data acquisition enable signal generated by the phase monitoring and data acquisition phase generator; The writing data terminal and the data ready indication signal generation circuit work in the data follower clock domain, and the edge detection circuit, phase monitoring and data acquisition phase generator, and the reading data terminal work in the system working clock domain. 2. The device according to claim 1, characterized in that the device further comprises a signal delay circuit located between the data ready indication signal generation circuit and the edge detection circuit, for latching the data ready indication signal for at least two input to the edge detection circuit after clock cycles. 3. The device according to claim 2, wherein the signal delay circuit is composed of a plurality of D flip-flops connected in series. 4. The device according to claim 1, wherein the data ready indication signal generating circuit comprises a first selector, a second selector, a D flip-flop and a delayer, wherein, The 1 input terminal of the first selector is input to 0, the 0 input terminal is connected to the output terminal of the D flip-flop, the control terminal is connected to the output terminal of the delayer, and the output terminal is connected to the 0 input terminal of the second selector. connected; The 1 input terminal of the second selector is input with 1, the 0 input terminal is connected with the output terminal of the first selector, the control terminal is input with a write enable signal, and the output terminal is connected with the D input terminal of the D flip-flop; The D input terminal of the D flip-flop is connected to the output terminal of the second selector, and the output terminal is connected to the edge detection circuit, the 0 input terminal of the first selector and the input terminal of the delayer; The input terminal of the delayer is connected with the output terminal of the D flip-flop, and the output terminal is connected with the control terminal of the first selector. 5. The device according to claim 4, wherein the delayer is composed of a plurality of D flip-flops connected in series, or is a counter that waits for multiple clock cycles to output signals. 6. The device according to claim 1, wherein the phase generator for phase monitoring and data acquisition further comprises a third selector, a fourth selector, a fifth selector, a first D flip-flop, a second D flip-flop and the second counter, where, The 1 input terminal of the third selector is input to 1, the 0 input terminal is connected to the output terminal of the first D flip-flop, the control terminal is input to the data indication signal, and the output terminal is connected to the D input terminal of the first D flip-flop; The 1 input terminal of the fourth selector is input to the data indication signal, the 0 input terminal is input to 0, the control terminal is connected to the output terminal of the first counter, and the output terminal is connected to the input terminal of the fifth selector; The 1 input terminal of the fifth selector is input to the data indication signal, the 0 input terminal is connected to the output terminal of the fourth selector, the control terminal is connected to the output terminal of the first D flip-flop, and the output terminal is connected to the clearing terminal of the first counter. Connected at zero end; The D input terminal of the first D flip-flop is connected to the output terminal of the third selector, and the output terminal is connected to the 0 input terminal of the third selector, the control terminal of the fifth selector and the enabling terminal of the first counter; The D input terminal of the second D flip-flop is connected to the output terminal of the first counter, the enabling terminal is input with the data indication signal, and the output terminal is connected to the clearing terminal of the second counter; The clear terminal of the first counter is connected to the output terminal of the fifth selector, the enable terminal is connected to the output terminal of the first D flip-flop, and the output terminal is connected to the control terminal of the fourth selector and the D input of the second D flip-flop The terminals are connected, and the output terminal of the first counter outputs a data acquisition enabling signal; The clear terminal of the second counter is connected with its output terminal and the output terminal of the second D flip-flop, the enable terminal is input with the data indication signal, and the output terminal is connected with the clear terminal. 7. The device according to claim 1, wherein the storage unit is a random access storage unit or a register. 8. A method for transmitting data in an asynchronous clock domain, wherein the sender is located in the data-associated clock domain, and the receiver is located in the system operating clock domain and includes a first counter, wherein the method comprises the following steps: A. When the write enable signal is valid, the sender caches the data in the storage unit, and at the same time generates a data ready indication signal and sends it to the receiver; B. The receiver generates a data indication signal when detecting the edge of the data ready indication signal; C. Adjusting the phase of the first counter according to the data indication signal, and reading data from the storage unit when the phase of the first counter reaches the set phase. 9. The method according to claim 8, characterized in that before step B, there is a step of latching the data ready indication signal for more than one clock cycle. 10. The method according to claim 8, wherein the step of adjusting the phase of the first counter according to the data indication signal in step C comprises: Judging whether the current phase of the first counter is equal to its maximum phase when the data indication signal arrives, in the case of not equal, judging whether the absolute value of the difference between the current phase and the maximum phase is greater than 1, if greater than 1, then in the next data indication signal When it arrives, trigger the first counter to count again; if it is less than or equal to 1, when the difference between the current phase of the first counter and its maximum phase remains unchanged when multiple consecutive data indication signals arrive, trigger the The first counter counts again. 11. The method according to claim 8, wherein the step of reading data from the storage unit when the phase of the first counter reaches the set phase in step C comprises: generating a data acquisition enable signal when the phase of the first counter reaches a preset phase; Reading data from the storage unit according to the data acquisition enable signal.