CN1976082A - CuxO-based resistance random access memory and producing method thereof - Google Patents

Abstract

The invention belongs to the technical field of microelectronics, in particular to a structure and a preparation method of a resistance random access memory using _CuxO as a storage medium. In this memory, _Cux O as a storage medium is located directly below the through hole and penetrates deep into the lower layer copper lead, the lower layer copper lead is the lower electrode, and the upper layer of _Cux O is connected to the upper layer copper lead through a copper plug located in the through hole, The upper copper lead is the upper electrode. _CuxO is produced by plasma oxidation process. The fabrication method is compatible with dual damascene copper interconnection technology.

Description

CuxO-based resistance random access memory and its preparation method

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a resistive random access memory using _CuxO film as a storage medium and a preparation method thereof.

Background technique

Memory occupies an important position in the semiconductor market. Due to the continuous popularization of portable electronic devices, the share of non-volatile memory in the entire memory market is also increasing, of which more than 90% of the share is occupied by FLASH. However, due to the requirement of storing charges, the floating gate of FLASH cannot be thinned without limit with the development of technology generation. It is reported that the limit of FLASH technology is around 32nm, which forces people to look for the next generation of non-volatile memory with better performance. Recently, resistive random access memory (RRAM) has attracted great attention due to its high density, low cost, and the ability to break through the limitations of technological development. The materials used include phase change materials ^[1] , doped SrZrO ₃ ^[2] , ferroelectric material PbZrTiO ₃ ^[3] , ferromagnetic material Pr _1-x Ca _x MnO ₃ ^[4] , binary metal oxide material ^[5] , organic material ^[6] and so on. For more than ternary materials, precise control of components, compatibility with integrated circuit technology, and cost reduction are all difficulties. Relatively speaking, binary metal oxides (such as Nb ₂ O ₅ , Al ₂ O ₃ , Ta ₂ O ₅ , TixO, NixO ^[5] , Cu _x O, etc.) are particularly concerned. Among them, Cu _x O (1<x<2) is one of the binary metal oxides, and its storage properties have been proved by experiments ^[7] .

The structure of the memory cell of the currently reported _CuxO -based resistive memory device is shown in Figure 1 ^[5] . The device on the substrate is connected to the lower copper lead 3- through the W plug 8, and the upper part of 3- is located in the through hole 7 The copper plug in the copper plug plays the role of connecting the upper layer copper lead 3+ and the lower layer copper lead 3-, the Cu _x O storage medium 4 is located on the top of the through hole 7 and below the upper layer copper lead 3+, and the lower layer copper lead 3- , the through hole 7, and the upper layer copper lead 3+ are surrounded by insulating dielectric layers 1a, 1b and 1c respectively, and between 1a and 1b, and between 1b and 1c are respectively cap layer dielectrics (cap layer) for suppressing electromigration and improving reliability. )5a and 5b. This structure is difficult to integrate with the traditional double damascene copper interconnection process, but must be prepared by single damascene copper interconnection process. That is to say, it is not possible to form all the through holes and grooves first, and then fill them with copper to form copper leads and copper plugs at one time, but must first form through holes, fill them with copper to form plugs, then form grooves, and fill them with copper to form leads.

In the above structure, when an electrical signal is applied to both ends of the _Cux O resistor, the _Cux O resistor will switch between high resistance and low resistance, so that the states of 0 and 1 can be stored.

The currently reported _CuxO used in RRAM is prepared by thermal oxidation process, and the thermal oxidation speed is relatively slow, which will cause the following problems: 1) If the reaction time is long, the photolithography used as a mask to protect local copper from participating in the oxidation reaction The glue will be damaged, or even completely removed, and will not have a protective effect; 2) The current mainstream low-k medium usually contains C, and in an oxidizing atmosphere, C will be damaged, resulting in an increase in k; 3) If the oxidation reaction is reduced The time will lead to fewer defects in the thin film formed in a short time. Since there are high-temperature steps in the subsequent process, the defects will be further reduced, resulting in a decrease in the performance of the memory.

Contents of the invention

The object of the present invention is to provide a _CuxO -based storage device structure and a preparation method thereof, so as to overcome the above-mentioned shortcomings of existing similar devices.

The _CuxO memory device proposed by the present invention is a memory device with random access to resistance, and its structure is as follows: the _CuxO as a storage medium is located below the through hole and penetrates deep into the lower layer copper lead, and the lower layer copper lead is The lower electrode and the upper part of _CuxO are connected to the upper copper lead through the copper plug in the through hole, and the upper copper lead is the upper electrode. In Cu _x O, 1<x≤2.

In the above-mentioned device, an insulating dielectric layer for accommodating a through hole and an insulating dielectric layer for accommodating a groove are also included, and the copper plug and (upper and lower layer) copper leads are located in the through hole and the groove respectively, and the through hole and the groove penetrate the insulating medium layer; there is an etch stop layer between the insulating dielectric layer accommodating the through hole and the insulating dielectric layer accommodating the trench.

In the above device, there is a diffusion barrier metal between the copper plug and (upper and lower layer) copper leads and the insulating medium layer.

In the above device, there is a lower dielectric layer between the lower copper leads and the substrate, the through hole penetrates the lower dielectric layer, the lower plug is located in the through hole and contacts a predetermined area of the substrate, and the top surface of the lower plug is connected to the lower copper lead.

In the above device, the lower layer copper lead is coupled to the first address line; the upper layer copper lead is coupled to the second address line.

The present invention provides the following method to form the above-mentioned storage device: form the lower layer copper lead on the substrate, then form a through hole for accommodating the copper plug and a groove for accommodating the upper layer copper lead, and then form a Cu _x deep inside the lower layer copper lead under the through hole O storage medium, and then form copper plugs and upper copper leads.

The further implementation of the present invention also includes: forming a lower dielectric layer on the substrate, forming a lower plug penetrating through the lower dielectric layer to contact a predetermined area of the substrate, and then forming a diffusion barrier layer dielectric on the surface.

Forming the lower-layer copper lead includes: forming an insulating dielectric layer covering the lower plug on the substrate, and then forming a trench for accommodating the lower-layer copper lead through the layer in a predetermined area of the insulating dielectric layer, and then depositing a barrier layer on the side wall of the trench And the seed layer, then deposit copper in the trench, then grind off the excess copper and barrier layer on the surface to form the underlying copper lead, and then deposit the capping dielectric layer.

Forming through holes for accommodating copper plugs and trenches for accommodating upper-layer copper leads, including: sequentially forming an insulating dielectric layer for accommodating copper plugs, an etching stop layer, and an insulating dielectric layer for accommodating upper-layer copper leads; The patterns of through holes and grooves are sequentially formed on the top, and the insulating dielectric layer for accommodating the through holes, the etching stop layer, and the insulating dielectric layer for accommodating the grooves are sequentially penetrated to form through holes filled with copper plugs and grooves filled with upper layer copper leads;

The _CuxO storage medium is formed by plasma oxidation, that is, oxygen, oxygen-containing mixed gas or other gases containing oxygen elements are used to generate O plasma, and the O plasma reacts with metal copper to form a _CuxO storage medium film .

Forming copper plugs and upper copper leads, including: forming a diffusion barrier layer and a copper seed layer on the sidewalls of vias and trenches; and filling copper in trenches and vias to form copper plugs and upper copper leads; and grinding away Excess copper and diffusion barrier layers on the surface; and a capping dielectric layer.

The present invention also provides a system comprising the randomly selectable resistance memory device of the present invention, comprising a processor, inputs and outputs communicating with the processor, and a memory coupled to the processor; The memory uses the resistive random access memory device of the present invention as its memory unit. The structure of the memory cell includes: as a storage medium, _Cux O is located directly below the through hole and penetrates deep into the lower copper lead, the lower copper lead is used as the lower electrode, and the Cu _x O is located above the through hole through the copper plug and the upper copper lead. Lead connection, the upper copper lead as the upper electrode and so on.

The provided system can also include a wireless interface coupled to the processor.

Description of drawings

Figure 1. The memory cell structure of the RRAM memory device based on the _CuxO storage medium reported so far. The _CuxO used as the storage medium is located on the upper part of the via hole and below the upper copper lead. It is integrated by a single damascene process, and the _CuxO is integrated by thermal oxidation technology. preparation

Fig. 2 The RRAM device based on the _CuxO storage medium proposed by the present invention, the _CuxO used as the storage medium is located directly below the through hole, deep inside the lower copper lead, and can be integrated with the double damascene process, and the _CuxO adopts plasma oxidation technology preparation

3 to 9 illustrate a method of forming a _CuxO storage medium based RRAM according to some embodiments of the present invention.

Figure 10 illustrates a portion of a system according to one embodiment of the invention.

Figure 11 illustrates a portion of a system according to yet another embodiment of the invention.

Labels in the figure: 1a is the lower dielectric layer, 1b is the insulating dielectric layer, 1c is another insulating dielectric layer, 1d is another insulating dielectric layer, 2a is the diffusion barrier layer, 2b is the diffusion barrier layer, 3+ is the upper copper lead , 3- is the lower copper lead, 3b+ is the trench, 3b- is the through hole, 4 is the storage medium, 5a is the capping layer, 5b is the capping layer, 5c is the diffusion barrier layer, 6 is the etch stop layer, 7 is the copper Plug, 7b is a through hole, 8 is a lower plug, 8a is a diffusion barrier layer, 8b is a through hole, 9 is a substrate, 101 is a controller, 102 is a wireless interface, 103 is a memory, 104 is I/O, 105 is bus, 1000 for the system.

Detailed ways

While the present invention is described more fully hereinafter in the Reference Examples, the invention provides preferred embodiments but should not be considered limited to the embodiments set forth herein. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, but as schematic diagrams, they should not be considered as strictly reflecting the proportional relationship of geometric dimensions.

Here, the referenced figures are schematic illustrations of embodiments of the present invention, and the illustrated embodiments of the present invention should not be considered limited to the specific shapes of the regions shown in the figures, but include resulting shapes, such as manufacturing-induced deviations . For example, the curves obtained by dry etching usually have curved or rounded characteristics, but in the illustrations of the embodiments of the present invention, they are all represented by rectangles, and the representations in the figures are schematic, but this should not be considered as limiting the scope of the present invention scope.

It will be understood that when an element is referred to as being "on" or "extending over" another element, the element may be directly "on" or "extend" directly on the other element, or it may also be There is an insert element. In contrast, when an element is referred to as being "directly on" or "directly extending over" another element, there are no intervening elements present. When it is said that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may also be present, on the contrary, when an element is said to be directly connected to When "connected to another element" or directly "coupled to" another element, there is no intervening element.

Fig. 2 is a cross-sectional view according to one embodiment of the present invention. in:

The lower dielectric layer 1a is formed on the semiconductor substrate 9 (hereinafter referred to as the substrate). The through hole 8b is patterned on the 1a and then etched until the predetermined area of the substrate 100 is exposed through the 1a. The lower plug 8 is formed in the through hole. In 8b, the predetermined region of the lower plug contacting the substrate 100 is an impurity diffusion layer (not shown in the figure), and the impurity diffusion layer may be the source or drain region of a field effect transistor, or one of a diode or a bipolar transistor. element.

The lower dielectric layer 1 a can be a doped silicon oxide layer, such as phosphorus or boron doped silicon oxide (BPSG) or phosphorus doped silicon oxide (PSG).

The lower plug 8 may be a conductive material, such as W, heavily doped polysilicon, or a conductive material containing N, such as TiN.

The diffusion barrier layer 8a is a conductive material that prevents the lower plug 8 from diffusing into the dielectric layer. In the case that the lower plug 8 is W, 8a may be a Ti/TiN composite layer.

The plane above the lower plug is covered with a diffusion barrier layer 5c, above the 5c is an insulating dielectric layer 1d, the through hole 3b- penetrates 1d and 5c, and a groove 3b- for accommodating the lower layer copper leads is formed above the lower plug, and on the side wall of the groove is The diffusion barrier layer 2a, the underlying copper leads 3- are housed in the trenches 3b-. The top surface of the lower plug is in contact with the diffusion barrier layer 2a.

Diffusion barrier layer 5c can be silicon nitride or doped silicon nitride, or other insulating dielectric materials that can significantly block the diffusion of Cu.

The insulating dielectric layer 1d may be silicon oxide, or may be doped silicon oxide with low dielectric constant, such as silicon oxide doped with C or F, or may be other types of insulating dielectric with low dielectric constant.

Diffusion barrier layer 2a is a conductive material that blocks the diffusion of Cu to the dielectric layer, and can be TaN, Ta/TaN composite layer or Ti/TiN composite layer, or other conductive materials that play the same role, such as TiSiN, WNx, WNxCy, TiZr/TiZrN, etc.

On the plane above the upper copper lead 3-, the capping layer 5a, the insulating dielectric layer 1b, the etching stop layer 6, and the insulating dielectric layer 1c are sequentially covered from bottom to top. The through hole 7b penetrates the cap layer 5a, the insulating dielectric layer 1b, and the etch stop layer 6, and the trench 3b for accommodating the upper layer copper lead + penetrates the insulating dielectric layer 1c.

Directly below the via 7b is the _CuxO storage medium 4, which penetrates into the underlying copper lead 3-.

A diffusion barrier layer 2b is covered on the sidewalls of the via hole 7b and the trench 3b+, and the top surface of the _CuxO storage medium 4 is in contact with the diffusion barrier layer 2b.

The copper plug 7 and the upper layer copper lead 3+ are housed in the via hole 7b and the trench 3b+, respectively.

The surface of the upper layer copper leads 3+ is covered with a capping layer 5b, and the capping layer medium 5b accommodates through holes (not shown) passing through the 5b to further lead out the upper layer copper leads.

The capping layer 5 a can be a silicon nitride dielectric or a doped silicon nitride dielectric, such as O-doped or C-doped. Or other insulating dielectric materials that can significantly block the diffusion of Cu and significantly inhibit the electromigration of copper, such as CoWP.

The insulating dielectric layer 1b may be silicon oxide, or may be doped silicon oxide with low dielectric constant, such as silicon oxide doped with C or F, or may be other types of insulating dielectric with low dielectric constant.

The etch stop layer 6 can be a silicon nitride dielectric or a doped silicon nitride dielectric, such as C-doped or O-doped, or other insulating dielectric materials whose etching rate is significantly different from that of the insulating dielectric layer 1c.

The insulating dielectric layer 1c may be silicon oxide, or may be doped silicon oxide with low dielectric constant, such as silicon oxide doped with C or F, or may be other types of insulating dielectric with low dielectric constant.

At least a part of the composition of the _CuxO storage medium 4 is _CuxO (x is less than 2), which can be the coexistence of _CuxO (x is less than 2) and _CuxO (x is equal to 2) or pure _CuxO ( x is less than 2).

Diffusion barrier layer 2b is a conductive material that blocks the diffusion of Cu to the dielectric layer, and can be TaN, Ta/TaN composite layer or Ti/TiN composite layer, or other conductive materials that play the same role, such as TiSiN, WNx, WNxCy, TiZr/TiZrN, etc.

The lower surface of the _CuxO storage medium 4 is in contact with the lower copper lead 3-, the top surface is connected with the upper copper lead 3+, and the lower copper lead 3- and the upper copper lead 3+ are respectively used as the lower electrode and the upper electrode of the _CuxO storage medium , the lower layer copper wire 3- is coupled to the first address line, and the upper layer copper wire 3+ is coupled to the second address line (not shown in the figure).

Next, a method of forming a resistive random access device in some embodiments of the present invention will be explained. 3 to 9 illustrate cross-sectional views of a method of forming a resistive random access device of an embodiment.

Referring to FIG. 3, the lower dielectric layer 1a is formed on the substrate 9. 1a can be a doped silicon oxide layer, such as silicon oxide doped with phosphorus or boron (BPSG) or silicon oxide doped with phosphorus (PSG). Prepared by chemical vapor deposition and surface planarization. Before forming the lower dielectric layer 1a, an impurity diffusion region (not shown) can be formed in a predetermined area of the substrate 9. The impurity diffusion region can be the source and drain regions of a field effect transistor, and can be a diode, bipolar A component of a transistor.

Pattern the predetermined area of the lower dielectric layer to form a pattern of through hole 8b that can expose the predetermined area of the substrate, and use a conventional anisotropic etching process to form the through hole 8b through the lower dielectric layer to expose the predetermined area of the substrate. A lower plug 8 is then formed in the through hole. In some embodiments of the present invention, a Ti/TiN layer is formed by physical sputtering, and then a TiN layer is formed by a chemical vapor deposition method, and then a chemical vapor deposition method is used to fill the through hole 8b to form a W plug. Mechanical polishing removes redundant W and Ti/TiN on the surface, and planarizes the surface, and then a barrier dielectric layer 5c is deposited by chemical vapor deposition. 5c may be silicon nitride or doped silicon nitride.

Referring to FIG. 4 , the plane above the lower plug is covered with a diffusion barrier layer 5c, which can be silicon nitride or doped silicon nitride, or other insulating dielectric materials that can significantly block the diffusion of Cu. Above 5c is an insulating dielectric layer 1d, which can be silicon oxide, or can be doped silicon oxide with a low dielectric constant, such as C-doped or F-doped silicon oxide, or can be other types of low dielectric constant insulating medium. In some embodiments of the present invention, 5c and 1d are prepared by chemical vapor deposition.

Pattern the predetermined area of the insulating dielectric layer 1d to form the pattern of the groove that accommodates the lower layer of copper leads, and then use an etching process to penetrate through 1d and 5c to form the groove 3b-. In some embodiments of the present invention, conventional methods are used. The anisotropic dry etching process goes through 1d and 5c.

Next, deposit a diffusion barrier layer 2a on the sidewall of the trench, which can be TaN, Ta/TaN composite layer or Ti/TiN composite layer, or other conductive materials that play the same role, such as TiSiN, WNx, WNxCy, TiZr /TiZrN etc. In some embodiments of the present invention, a Ta/TaN composite layer is deposited as a barrier layer by physical sputtering. In other embodiments, TaN is deposited as a barrier layer by atomic layer deposition.

Cu is then deposited in the trench to form the underlying copper leads. In some embodiments of the present invention, a thin layer of copper is first deposited as a seed crystal on the diffusion barrier layer 2a by physical sputtering deposition, and then the trench is filled with copper by electrochemical deposition (ECP), Then anneal to fully grow the copper grains. Then chemical mechanical polishing is used to grind away excess copper and barrier material on the surface to form upper layer copper leads. Then deposit a capping layer 5a on the surface, which can be a silicon nitride medium or a doped silicon nitride medium, such as O-doped or C-doped, or others that have a significant barrier to the diffusion of Cu and the electromigration of copper. Insulating dielectric materials with obvious inhibition, such as CoWP. In some embodiments, the capping layer 5a is prepared by chemical vapor deposition.

Referring to FIG. 5, in some embodiments, an insulating dielectric layer 1b, an etch stop layer 6, an insulating dielectric layer 1c, and an etch stop layer 7 are sequentially formed above the cap layer 5a. In some embodiments, the cap layer 5a An insulating dielectric layer 1b, an etching stop layer 6, and an insulating dielectric layer 1c are sequentially formed above. It can be formed by chemical vapor deposition. 1b and 1c may be silicon oxide, or may be doped silicon oxide with low dielectric constant, such as C-doped or F-doped silicon oxide, or may be other types of insulating medium with low dielectric constant. The etch stop layers 6 and 7 can be silicon nitride dielectric or doped silicon nitride dielectric, such as C-doped or O-doped, or other insulating dielectric materials whose etching rate is significantly different from that of the insulating dielectric layer 1c.

Referring to Fig. 6, the further implementation of the present invention is to pattern the predetermined area on the surface. In some embodiments, the pattern of the through hole 7b is first formed, and then the etching stop layer 7, the insulating dielectric layer 1c, and the etching stopper layer are sequentially penetrated. layer 6, insulating dielectric layer 1b, and form a through hole 7b; next, pattern the predetermined area of the surface again to form the pattern of the trench 3b+, and penetrate the etch stop layer 7 and the insulating dielectric layer 1c to form the trench 3b+. In some embodiments of the present invention, a conventional anisotropic dry etching process is used through.

For further implementation of the present invention, in some other embodiments, the trench 3b+ is first patterned and formed through, and then the through hole 7b is patterned and formed through.

For further implementation of the present invention, in some other embodiments, after the insulating dielectric layer 1b and the etch stop layer 6 are sequentially formed on the top of the cap layer 5a, a pattern is first patterned on the top of the cap layer 5 and penetrated through the 6 to form a pattern of a through hole, and then an insulating dielectric layer 1b is further formed. The dielectric layer 1c and the etching stop layer 7 are patterned on the surface to form groove patterns, and then the grooves 3b+ and through holes 7b are formed through each layer of dielectric at one time.

It should be noted that the sequence of forming the via hole and the trench is not a limitation of the present invention.

In a further implementation of the present invention, the etching residue is cleaned next, and in some embodiments, a conventional process of first cleaning with a plasma reaction and then wet cleaning with a chemical solution is adopted. Then gently open the capping layer 5a by dry etching, exposing the lower layer copper wire 3-.

It should be noted that the pattern of via holes and trenches is formed and the underlying copper leads are exposed by adopting the traditional double damascene copper interconnection process, and there are some changes and adjustments in the formation method and sequence, which are not limitations of the present invention.

For further implementation of the present invention, referring to FIG. 7 , a _CuxO storage medium 4 is formed by plasma oxidation technology. Oxygen, or a mixed gas of oxygen and other gases, such as a mixture of oxygen and argon, or nitrogen, or other oxygen-containing gases as the gas source, flows into the sample chamber of the plasma generating equipment at a certain flow rate, and produces O. Plasma, O plasma reacts with copper in the exposed underlying copper leads to form a _CuxO storage medium. In the formed _CuxO storage medium, 1<x≤2. Plasma equipment includes, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition), high-density plasma CVD (Chemical Vapor Deposition), strippers, etching equipment, and the like. In some embodiments of the present invention, plasma reactive etching equipment is used, the volume ratio of oxygen and argon is from 1:1 to 1:20, the flow rate ranges from 5 sccm to 60 sccm, the oxidation time ranges from 2 min to 120 min, and the substrate temperature range From room temperature to within 200 degrees, and the power range from 50w to 300w, a _CuxO storage medium with storage characteristics is obtained. It should be noted that the oxidation conditions are related to specific parameters and designs of different equipment, and therefore are not limited to the range of process parameters in the embodiments of the present invention.

For further implementation of the present invention, referring to FIG. 8 , a copper plug 7 and an upper layer copper lead 3+ are formed in the trench 3b+ and the via hole 7b. In some embodiments of the present invention, the diffusion barrier layer 2b and seed crystal copper are first formed on the sidewalls of the trench 3b+ and the through hole 7b by physical sputtering, and then the copper is filled into the through hole at one time by electrochemical deposition. and trenches to form copper plugs 7 and upper layer copper leads 3+. The diffusion barrier layer 2 b is in contact with the top surface of the _CuxO storage medium 4 . Diffusion barrier layer 2b is a conductive material that blocks the diffusion of Cu to the dielectric layer, and can be TaN, Ta/TaN composite layer or Ti/TiN composite layer, or other conductive materials that play the same role, such as TiSiN, WNx, WNxCy, TiZr/TiZrN, etc.

For further implementation of the present invention, referring to FIG. 9 , chemical mechanical polishing is used to remove excess copper, barrier layer material and etch stop layer material on the surface. Then a cap layer material 5b is formed on the surface to form the memory shown in FIG. 2 , and a through hole (not shown) passing through the cap layer medium 5b is accommodated in the cap layer medium 5b to further lead out the upper layer copper leads. The lower surface of the _CuxO storage medium 4 is in contact with the lower copper lead 3-, the top surface is connected with the upper copper lead 3+, and the lower copper lead 3- and the upper copper lead 3+ are respectively used as the lower electrode and the upper electrode of the _CuxO storage medium , the lower layer copper wire 3- is coupled to the first address line, and the upper layer copper wire 3+ is coupled to the second address line (not shown in the figure).

The storage device and the preparation method of the present invention are compatible with the conventional double damascene copper interconnection process, that is, after the through hole and the groove are formed, the copper is filled in one time, and the copper plug and the lead are formed at the same time. In addition, the use of plasma oxidation process to form _CuxO storage medium has the following significant advantages: the oxidation speed can be more than 4 times faster than that of thermal oxidation at about 200 ° C, the oxidation can be carried out at room temperature, and it is easy to integrate with other process steps, especially low dielectric Constant process steps are compatible.

Referring to FIG. 10 , an embodiment of the system provided by the present invention, a system 1000 , may include a controller 101 , an input/output (I/O) device 104 , a memory 103 , and a bus 105 .

With reference to Fig. 11, another embodiment of the system provided by the present invention, system 1000, can comprise a controller 101, input and output (I/O) device 104, memory 103, bus 105, also comprise the wireless network that is coupled to each other by bus 105 Interface 102. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller 101 may include one or more microprocessors, digital signal processors, microcontrollers, and the like. Memory 103 may be used to store information transmitted to or from system 1000, and may also be used to store instructions. Memory 103 can be made up of one or more different types of memory, such as flash memory and/or contain a kind of storage device as described in the present invention, and its structural feature is: as storage medium _CuxO is positioned at through hole Below and deep into the interior of the lower layer copper wire, the lower layer copper wire serves as the lower electrode, and the upper layer of Cu _x O is connected to the upper layer copper wire through the copper plug in the through hole, and the upper layer copper wire serves as the upper electrode.

The system can generate information using I/O devices 104 .

Radio interface 102 may be used to transmit information to and receive information from a wireless communication network using radio frequency signals. Examples of wireless interface 102 may include an antenna or a wireless transceiver, although the scope of the invention is not limited to these structures.

references

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Claims (10)

1, a kind of resistance random access memory device is characterized in that: as the Cu of storage medium _xO is positioned under the through hole and is deep into lower floor copper lead-in wire inside, and lower floor's copper goes between as bottom electrode, Cu _xThe O top then is connected with the upper copper lead-in wire by the copper embolism that is arranged in through hole, and the upper copper lead-in wire is a top electrode; Cu _xAmong the O, 1＜x≤2.

2, resistance random access memory device according to claim 1 is characterized in that also comprising the insulating medium layer of receiving opening, and the insulating medium layer that holds groove, and copper embolism and upper and lower copper lead-in wire lay respectively in through hole and the groove; The insulating medium layer of receiving opening and hold between the insulating medium layer of groove etch stop layer is arranged.

3, resistance random access memory device according to claim 1, it is characterized in that also comprising the diffusion impervious layer metal that reaches between copper embolism and the insulating medium layer between copper lead-in wire and the insulating medium layer, and following dielectric layer between lower floor's copper lead-in wire and substrate and the through hole that has connected this time dielectric layer, following embolism is arranged in through hole and contacts with the presumptive area of substrate, and the top surface of following embolism is connected to lower floor's copper lead-in wire.

4, resistance random access memory device according to claim 1 is characterized in that lower floor's copper lead-in wire is coupled with first address wire; The upper copper lead-in wire is coupled with second address wire.

5, a kind of preparation method of resistance random access memory device as claimed in claim 1 comprises: form lower floor's copper lead-in wire on substrate, form the through hole that holds the copper embolism then and hold the groove that upper copper goes between; Below through hole, form again and go deep into the inner Cu of lower floor's copper lead-in wire _xThe O storage medium forms copper embolism and upper copper lead-in wire at last.

6, method according to claim 5 also comprises: dielectric layer under forming on the substrate, and formation connects down, and dielectric layer forms the diffusion layer medium then with the following embolism of contact substrate presumptive area on the surface.

7, method according to claim 5, wherein, form lower floor's copper lead-in wire, comprise: at the insulating medium layer that forms embolism under the covering on the substrate, connect the groove that lower floor's copper lead-in wire is held in this layer formation in the presumptive area of insulating medium layer then, then and at trench sidewall deposition barrier layer and inculating crystal layer; Deposited copper in groove then; Copper that worn surface is unnecessary and barrier layer form lower floor's copper lead-in wire, then deposition block dielectric layer.

8, method according to claim 5 wherein, forms the through hole that holds the copper embolism and holds the groove that upper copper goes between, and comprising: order forms insulating medium layer, the etch stop layer that holds the copper embolism, the insulating medium layer that holds the upper copper lead-in wire successively; Order constitutes the figure of through hole and groove on the presumptive area of substrate then, order connect receiving opening insulating medium layer, etch stop layer, hold the insulating medium layer of groove, form through hole of filling the copper embolism and the groove of filling the upper copper lead-in wire;

9, method according to claim 5 wherein, forms copper embolism and upper copper lead-in wire, comprising: form diffusion impervious layer and copper seed layer on through hole and trenched side-wall; And filling copper forms copper embolism and upper copper lead-in wire in groove and through hole; And unnecessary copper and the diffusion impervious layer in worn surface; And formation block dielectric layer.

10, a kind of metal is made the system of the memory device of the described resistance random access of claim 1, comprising: a processor, and with the input and output of described processor communication, and the memory that is coupled to this processor; Said memory by the memory device of the described resistance random access of claim 1 as its memory cell.

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