CN1968036A

CN1968036A - A forward correcting decoding device and control method

Info

Publication number: CN1968036A
Application number: CN 200610085155
Authority: CN
Inventors: 潘文; 王万万; 熊焰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2006-05-31
Filing date: 2006-05-31
Publication date: 2007-05-23
Anticipated expiration: 2026-05-31
Also published as: CN1968036B

Abstract

The invention relates to a forward correcting decoder and relative control method, wherein said device comprises forward correct FEC decode circuit, frame data divide module and frame data recombine module; the FEC decode circuit has at least two parallel paths; the frame data divide module receives the frame data transmitted via FEC code method, and divides each frame data via word length sequence; feeds divided data sections into each FEC decode circuit and decodes; the frame data recombine module recombines frame data. The invention can avoid bandwidth limit, in GPON network, to send and decode descending data continuously.

Description

Forward error correction decoding device and control method

Technical Field

The present invention relates to signal transmission technologies, and in particular, to a forward error correction decoding apparatus and a control method thereof.

Background

In order to ensure that the interference of noise sources to the content of the transmission signal is avoided as much as possible in the transmission of the signal in the channel, the communication transmission system generally adopts an error control mechanism, the signal source and the signal sink are respectively a transmitting end and a receiving end of the signal in the communication system, and the purpose of the communication system is to transmit the signal from the signal source to the signal sink without error. As shown in fig. 1, the source needs to perform source coding after generating the signal S, and the sink needs to perform source decoding on the signal before receiving the signal, which are completely inverse processes. The encoding/decoding of the source, which essentially performs encryption or other format conversion of the signal, is a pre-processing of the data content prior to transmission of the signal, which is not involved in error control. The five parts of channel coding, modulator, channel, demodulator and channel decoding are the key parts of error control in signal transmission, and are described in detail below.

As can be seen from fig. 1, when a signal is transmitted in a channel, it is inevitably interfered by a noise source, and the key of error control is how to recover the signal after being interfered by the noise, and a communication system is implemented by channel coding the signal before transmission. Briefly, the channel coding is to calculate and generate a check code according to the content of the transmission data, and insert the check code into the content of the transmission data according to a certain rule. When the coded data is transmitted to a signal receiving end through a modulator, a channel and a demodulator, the channel decoding judges whether the data content is polluted by a noise source according to a check code in the transmitted data, and positions and corrects errors. Thus, data can be transmitted with a low error rate.

Error control in communication systems is classified into a wide variety of categories, of which four are currently mainly used: FEC (Forward Error Correction), ARQ (Automatic Error request equipment), HEC (Header Error Control), and IRQ (narrow information feedback).

In the ARQ transmission mode, after receiving data sent by the signal sending end, the signal receiving end can judge whether the received data is correct by calculating the check code, and feeds back a response signal of the judgment result to the ARQ signal sending end. If the data is judged to be wrong, the signal sending end retransmits the data until the receiving end can correctly receive the data. The method is more suitable for point-to-point communication transmission, can ensure the correctness of the transmitted data, but has low consistency and instantaneity. Particularly, under the environment with a strong noise background, most of the time is used for data retransmission;

in the FEC transmission mode, the receiving end of the signal does not need to feed back the response signal, and the receiving end can locate the position of the error in the transmission data according to the check code and correct the error. The transmission mode has no retransmission mechanism, so that the real-time performance of data transmission can be ensured, and simulcast communication from one user to a plurality of users can be carried out;

the HEC method combines the features of FEC and ARQ, and after receiving data, a receiving end firstly performs error correction and error correction on the received data. If error correction is possible, receiving data; if the error correction cannot be carried out, an error correction failure signal is fed back, and the signal sending party retransmits the last data.

After receiving the data, the signal receiving end in the IRQ mode returns the data to the signal sending end, and the sending end compares whether the data is correct and judges whether the data is retransmitted or not. This approach has the lowest transmission efficiency and limited application.

Because the FEC error correction method can ensure real-time data transmission, the FEC error control method is adopted in the gigabit passive optical network where data must be transmitted correctly and real-time transmission is required.

A PON (Passive optical Network) refers to a Passive electronic device system including an OLT (optical line termination), an ONU (optical Network Unit), and an ODN (optical Distribution Network). Passive means that the optical distribution network between the OLT and the ONUs does not have any active electronics. The passive optical network technology is a point-to-multipoint optical fiber transmission and access technology, a broadcast mode is adopted in the downlink, a time division multiple access mode is adopted in the uplink, tree-type, star-type, bus-type and other topological structures can be flexibly formed, node equipment is not needed at an optical branch point, and only a simple optical branch device needs to be installed, so that the passive optical network technology has the advantages of saving optical cable resources, sharing bandwidth resources, saving machine room investment, being high in equipment safety, being fast in network building speed, being low in comprehensive network building cost and the like. It is for these reasons that PON technology has been rapidly developed.

Currently, classified from the content of the bearer, the PON technology mainly includes APON (ATM Based PON, ATM passive optical network, where ATM is Asynchronous Transfer Mode, EPON (Ethernet Based PON, Ethernet passive optical network), GPON (Gigabit-capable PON, Gigabit passive optical network), and the like, as shown in fig. 2, which is a schematic diagram of a typical networking structure of the PON network, where the PON network includes an OLT located at a local end and a series of ONUs located at a customer premises, an ODN connection between the OLT and the ONUs is formed by an optical fiber, a passive optical splitter, or a coupler, and the ONUs are connected to TDM (Time Division multiplexing) customers (TDM Clients) or Data customers (Data Clients), and the OLT is connected to the internet (ipnets), TDM Networks (TDM Networks) or VIDEO Networks (deo Networks).

The PON system has the following convention: the direction from the OLT to the ONU is the downstream direction, and the direction from the ONU to the OLT is the upstream direction. In the uplink direction and the downlink direction, the OLT sends data to all ONUs in the ODN in units of frames, maintains a frame transmission period of 8KHz, and continuously sends data to the ODN, and the GPON downlink frame includes a frame header and a payload portion, as shown in fig. 3, and is described by taking the nth frame and the (n + 1) th frame as an example.

The existing OLT generally adopts RS (255, 239) coding of FEC when sending a downlink frame, and the ONU needs to decode and correct the downlink frame after receiving the downlink frame. The position of the FEC check code in the downlink frame is shown in fig. 4, the FEC check code based on the RS (255, 239) code is a check code inserted 16 bytes after every 239 bytes, a codeword is formed every 255 bytes, and for the last data segment, if the data is less than 239 bytes, 0 is added before or after the existing data byte to complete 239 bytes, and then the check code is inserted. For example, as shown in fig. 4, a 0 of 135 bytes needs to be padded in the last codeword. After receiving the downlink frame, the ONU needs to cut the downlink frame data into code words with 255 bytes as a unit, and decode the code words respectively. And after decoding and error correction, removing 16-byte check codes, and splicing the effective data groups together to form frame data required by the ONU.

Still referring to fig. 4, it should be noted that, when the mantissa portion of each downstream frame, i.e. the last codeword, is less than 255 bytes, an appropriate number of 0 s needs to be inserted after the data before decoding the ONU, so that the FEC decoding is completed after the size of the last codeword is also equal to 255 bytes, and the check is performed by using the corresponding 16-byte check code. After FEC decoding is completed, the inserted 0 needs to be removed again, and the original data is recovered.

Currently, many manufacturers provide sophisticated FEC decoding modules (FEC _ CORE) based on RS (255, 239) codes, and these FEC _ CORE are 8 bits wide and are decoded in units of 255-byte code words. Therefore, after receiving the downstream frame, the ONU must arrange the frame data into a codeword of RS (255, 239), and send the codeword of 255 bytes long into FEC _ CORE. Since the GPON downlink data is transmitted without interruption, each frame of data is immediately followed by the next frame of data. However, during decoding, extra 0 data may be inserted into the mantissa portion of each downlink frame, and the extra 0 needs to occupy a corresponding processing bandwidth, so how to ensure that downlink frame data can be decoded in real time and uninterruptedly through FEC _ CORE is a key for the FEC method to be applied in the GPON network.

Disclosure of Invention

The invention provides a forward error correction decoding device and a control method, which aim to solve the problem that the decoding part is limited by bandwidth and cannot realize real-time decoding in the actual application of the existing forward error correction error control mode.

In order to solve the technical problems, the invention provides the following technical scheme:

a forward error correction decoding device comprises a frame data segmentation module, a frame data recombination module and at least two FEC decoding circuits which are arranged in parallel; wherein,

the frame data segmentation module is connected with the input end of each FEC decoding circuit and used for receiving frame data based on FEC coding, segmenting each frame data according to a fixed byte length sequence, and respectively sending each segmented data into each FEC decoding circuit according to a set decoding sequence, wherein each data segment comprises a section of effective data and a corresponding FEC check code;

the FEC decoding circuit comprises an input buffer module, an FEC decoding module and an output buffer module which are connected in sequence and used for decoding each data segment in parallel and outputting each decoded data segment to a frame data recombination module;

and the frame data recombination module is connected with the output end of each path of decoding circuit and is used for removing the check codes in each data segment and recombining the effective data according to the segmentation sequence and then outputting the effective data.

The decoding apparatus further includes: and the first delay module is connected between the frame data segmentation module and the frame data reassembly module and is used for delaying and sending the frame header indication information sent by the frame data segmentation module to the frame data reassembly module, wherein the delay time is the time required for decoding the first data segment of each frame data.

The decoding device further comprises a second delay module; wherein:

the frame data reconstruction module is connected between the frame data segmentation module and the frame data reconstruction module and is used for delaying and sending the number of 0 inserted into the frame tail data segment by the frame data segmentation module to the frame data reconstruction module, wherein the delay time is the time required for decoding each frame data frame tail data segment; or

And the delay time is the time required for decoding each frame data frame tail data segment.

And the decoding circuit of the input buffer module connected with the second delay module is a special decoding circuit for the frame tail data segmentation.

The FEC decoding module is 8-bit wide input/output; and/or the input buffer module and the output buffer module are all first-in first-out FIFO memories.

The present invention also provides a first control method of the decoding apparatus, where one FEC decoding circuit in the FEC decoding apparatus is a dedicated decoding circuit for decoding end-of-frame data segments, and the other FEC decoding circuits are non-dedicated decoding circuits for decoding non-end-of-frame data segments, where the control method includes the following steps:

a1, a frame data segmentation module receives frame data based on FEC coding and segments the frame data according to a fixed byte length sequence, each segmented frame data segment comprises a section of effective frame data and an FEC check code corresponding to the effective frame data, according to the segmentation sequence, the frame data segmentation module synchronously writes non-frame-tail data segments into a non-special decoding circuit in turn for decoding, and writes the last frame-tail data segment into a special decoding circuit for decoding;

a2, the frame data restructuring module reads all the decoded non-frame tail data segments from the non-special decoding circuit in sequence according to the decoding sequence of the non-frame tail data segments, then reads the decoded frame tail data segments from the special decoding circuit, and according to the reading sequence, the frame data restructuring module synchronously removes the FEC check code of each data segment and restructures the effective frame data segments into frame data and outputs the frame data segments.

In the step a1, the frame data segmentation module distinguishes two adjacent frames of data according to the frame header identifier of the frame data.

In step a1, the frame data segmentation module sends frame header indication information each time a new frame of data is received; the frame header indication information is delayed and sent to a frame data recombination module through a delay module, and the delay time is the time required for decoding the first data segment of the frame data; in step a2, after receiving the frame header indication information, the frame data reassembly module reads the decoded first data segment of the frame data from the corresponding decoding circuit.

In step a2, the frame data reassembly module determines a total byte length included in each frame data according to a transmission rate of the frame data, and initializes a count value of a local byte counter according to the total byte length each time the frame header indication information is received; and determining that the next data segment that should be read is the end-of-frame data segment when the count value indicates that the total byte length minus one fixed length byte has been received.

In step a2, the frame data reassembly module determines a total byte length included in each frame data according to the transmission rate of the frame data, and distinguishes two adjacent frames of data and a frame end data segment by using the count value of the local byte counter, which specifically includes:

initializing the count value of a local byte counter according to the total byte length after recombining one frame data;

each time the count value indicates that the total byte length minus a fixed length byte has been received, the next data segment that should be read is determined to be an end-of-frame data segment.

And when the byte length of the frame tail data segment is smaller than the fixed byte length, performing 0 insertion processing on the frame tail data segment before decoding the frame tail data, and removing all inserted 0 after decoding, wherein the position of the inserted 0 is before the last section of effective data or between the last section of effective data and the last FEC check code. The specific operation comprises the following three modes:

the step a1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments written into the special decoding circuit, and simultaneously delays and sends the number of the inserted 0 to the frame data recombination module through a delay module, wherein the delay time is the time required by decoding the frame tail data segments; and the step A2 further comprises: and the frame data recombination module reads the decoded frame tail data segment from the special decoding circuit, removes all 0 inserted in the frame tail data segment according to the number of the inserted 0, and then recombines the frame data.

In step a1, the frame data segmentation module writes the tail data segment into the dedicated decoding circuit, and writes the number of 0's to be inserted into the dedicated decoding circuit, the dedicated decoding circuit performs 0 insertion processing on the tail data segment, and the dedicated decoding circuit delays and sends the number of 0's to be inserted to the frame data reassembly module through a delay module, where the delay time is the time required for decoding the tail data segment; the step a2 further includes: and the frame data recombination module reads the decoded frame tail data segment from the special decoding circuit, removes all 0 inserted in the frame tail data segment according to the number of the inserted 0, and then recombines the frame data.

The step a1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments and then inputs the frame tail data segments into a special decoding circuit; the step a2 further includes: the frame data reorganization module reads the decoded frame tail data segment from the special decoding circuit, determines the number of 0 to be inserted according to the transmission rate of the frame data, and reorganizes the frame data after removing all 0 inserted in the frame tail data segment.

The frame data is FEC encoded frame data based on RS (255, 239), the fixed byte length is 255 bytes of integral multiple, wherein each segment of 255 bytes contains effective data of 239 bytes, and the check code is 16 bytes; and is

When the transmission rate is 2.5G, 135 0 s should be inserted into the end-of-frame data segment;

when the transmission rate is 1.25G, 195 0 s should be inserted into the end-of-frame data segment.

The second method for controlling the forward error correction decoding device provided by the invention comprises the following steps:

b1, the frame data segmentation module receives frame data based on FEC coding and segments the frame data according to the fixed byte length sequence, each segmented frame data segment comprises a section of effective frame data and an FEC check code corresponding to the effective frame data, and the frame data segmentation module synchronously writes each frame data segment into each channel of decoding circuit in turn for decoding according to the segmentation sequence;

b2, the frame data restructuring module reads each frame data segment from each path of decoding circuit in sequence according to the corresponding decoding sequence, synchronously removes the FEC check code of each data segment, restructures the effective frame data segment into frame data and outputs the frame data.

In this second mode of operation, further processing is similar to that in the first mode of operation.

The invention has the following beneficial effects:

the invention adopts a multi-channel FEC _ CORE multiplexing mode, provides a corresponding control method of an FEC decoding device for parallelly setting multi-channel FEC _ CORE decoding circuits, and eliminates the problem of bandwidth limitation when 0 is additionally inserted into frame tail data of frame data transmitted in an FEC coding mode when an FEC error control mode is utilized;

the technical scheme of the invention completely meets the real-time decoding requirement of the downlink FEC frame data which are transmitted uninterruptedly in the GPON network.

Drawings

Fig. 1 is a schematic diagram illustrating the principle of error control in a communication system;

FIG. 2 is a schematic diagram of a typical PON configuration;

fig. 3 is a schematic diagram of a GPON downlink frame structure;

fig. 4 is a schematic structural diagram of inserting FEC check codes into a GPON downlink frame;

fig. 5 and fig. 6 are schematic structural diagrams of a decoding apparatus according to an embodiment of the present invention;

fig. 7 and 8 are schematic structural diagrams of a decoding apparatus according to a second embodiment of the present invention;

fig. 9 and fig. 10 are schematic structural diagrams of a decoding device according to a third embodiment of the present invention.

Detailed Description

The FEC _ CORE of the existing RS (255, 239) is 8-bit wide input and 8-bit wide output, and according to the bit width of the GPON downlink frame data and the extra bandwidth required for preprocessing the frame tail data, the present invention adopts a multiplexing manner of multi-channel FEC _ CORE, and the total input/output bit width of the decoding portion should match with the bit width of the transmitted frame data, which is described in detail below with specific embodiments and with the accompanying drawings.

Example one

When real-time FEC decoding is implemented on 16-bit wide downlink frame data, the structure of the decoding apparatus provided by the present invention is shown in fig. 5, and includes:

the first path of FEC decoding circuit comprises an input cache module CW _ BUF _0, an FEC decoding module FEC _ CORE _0 and an output cache module FEC _ BUF _0 which are connected in sequence;

the second FEC decoding circuit comprises an input cache module CW _ BUF _1, an FEC decoding module FEC _ CORE _1 and an output cache module FEC _ BUF _1 which are connected in sequence;

the third FEC decoding circuit comprises an input buffer module CW _ BUF _2, an FEC decoding module FEC _ CORE _2 and an output buffer module FEC _ BUF _2 which are connected in sequence;

the frame data segmentation module FEC _ IN is connected with the input end of each input buffer module CW _ BUF;

the frame data recombination module FEC _ OUT is connected to the output end of each output buffer module FEC _ BUF;

a first DELAY module FP _ DELAY connected between FEC _ IN and FEC _ OUT;

a second DELAY module NUM _ RESIDUE _ DELAY connected between CW _ BUF _2 and FEC _ OUT.

The buffer module with the simplest control mode is a First-in-First-out (fifo) memory.

The operation of the decoding apparatus shown in fig. 5 for decoding one frame data is described in detail as follows:

the 16-bit wide real-time data to be decoded is input from the right side of the FEC _ IN module IN fig. 5, and the FEC _ CORE modules based on the RS (255, 239) are 8-bit wide input and 8-bit wide output according to the current RS (255, 239) standard definition. It can be seen that the difference in bit width causes a bottleneck in the data stream bandwidth; meanwhile, since the tail of the FEC decoding of the downlink frame can make up the last code word of 255 bytes in length by inserting 0, the inserted 0 also causes extra bandwidth.

Referring to fig. 4, the beginning of each frame carries a frame header identifier, and FEC _ IN can distinguish two adjacent frames according to the frame header identifier.

In order to ensure that the FEC decoding device can process the input data in real time, the present invention adopts a multi-channel FEC decoding multiplexing method, and the device shown in fig. 5 multiplexes three channels of FEC _ CORE, which are FEC _ CORE _0, FEC _ CORE _1, and FEC _ CORE _2, where the three channels of FEC decoding are 8-bit wide input/output, and the three channels of FEC decoding modules cooperate to meet the bandwidth requirement of the downlink frame data. The FEC decoding apparatus shown in fig. 5 can have the following two operation modes:

one path of FEC decoding module is specially used for decoding frame end code words and not used for decoding non-frame end code words, see FEC _ CORE _2

Referring to fig. 5, the middle three FEC _ CORE modules complete FEC decoding, and the FEC _ IN and FEC _ OUT on the two sides respectively complete logic modules for frame data slicing before decoding and frame data reassembly after decoding. Because the transmission speed of frame data is far higher than the processing speed of a single FEC _ CORE module, the invention adopts a FIFO loose coupling mode to buffer the influence caused by rate mismatch.

Referring to fig. 5, the CW _ BUF buffer module and the FEC _ BUF module buffer module connected to both ends of each FEC _ CORE are FIFO memories, and these FIFO memories can absorb the bandwidth difference between the decoding module and the slicing/re-grouping module, so as to realize smooth transition of frame data between two transmission rates.

Referring to fig. 5, downlink frame data is input from the right side of FEC _ IN, and FEC _ IN identifies the start point of each downlink frame data through a frame header identification signal, initializes a local byte counter to start counting (the byte counter may be initialized to 0 for performing addition counting, or may be initialized to a total byte length value of one frame data corresponding to the current data transmission rate for performing subtraction counting), and sequentially cuts the downlink frame data into data segments with a length of 255 bytes, where the data segments with the length of 255 bytes are called as codewords. After FEC _ IN generates these code words, they are written into CW _ BUF _0 and CW _ BUF _1 FIFO modules IN turn. For example, the first codeword is written CW _ BUF _0, the second codeword is written CW _ BUF _1, the third codeword is written CW _ BUF _0, and so on.

After the code words written into the CW _ BUF _0 and the CW _ BUF _1 are converted from 16 bits to 8 bits in the FIFO, the code words are directly sent to two decoding modules of FEC _ CORE _0 and FEC _ CORE _1 for processing. The conversion of the code word from the CW _ BUF _0/CW _ BUF _1 module to complete the bit width conversion to FEC _ CORE _0/FEC _ CORE _1 decoding is uninterrupted, so that the two FIFO modules CW _ BUF _0/CW _ BUF _1 cannot be fully filled, and FEC _ IN can uninterruptedly write the code word into CW _ BUF _0 and CW _ BUF _1, thereby ensuring uninterrupted transmission of downstream data.

As described above, the downstream frame data is cut into individual code words by FEC _ IN, and the individual code words are sent to FEC _ CORE _0 and FEC _ CORE _1 through two FIFOs of CW _ BUF _0 and CW _ BUF _1, respectively, for decoding. However, when the mantissa part of the downstream frame data is cut, the last byte is not enough to form a code word 255 bytes long, so, FEC _ IN needs to determine the number of 0 to be inserted according to the number of bytes at the end of the frame, and write the number of 0 to CW _ BUF _2, CW _ BUF _2 completes bit width conversion, and when writing to FEC _ CORE _2 decoding module, 0 is inserted IN the set position of the byte (before the data byte or between the data byte and 16-bit check byte), and FEC _ CORE _2 decodes the frame end code word.

It should be noted here that, when the end-of-frame data is just 255 bytes at a specific rate, 0 insertion processing is not required. If the 0-inserting process is needed, FEC _ IN may determine whether the penultimate codeword of the frame data decoded this time has been cut out according to the count value of the byte counter, and if so, the next data segment is an end-of-frame data segment.

It should be noted here that the length of the sliced frame data segment is specifically set according to the processing capability of the FIFO, and if the FIFO can write two or three codewords at a time, the length of the sliced frame data segment can be set to 510 bytes or 765 bytes, respectively. When the 0-inserting process is required, the position of the inserted 0 is before the last section of valid data or between the last section of valid data and the last check code.

So far, each data segment of the downlink frame data is sequentially sent to FEC _ CORE _0, FEC _ CORE _1, and FEC _ CORE _2 to complete decoding, and the following details discuss a process of splicing the data into a complete downlink frame data after three-way FEC decoding.

Still referring to fig. 5, the data segments decoded by FEC _ CORE _0, FEC _ CORE _1, and FEC _ CORE _2 are written into FEC _ BUF _0, FEC _ BUF _1, and FEC _ BUF _2, respectively. Where FEC _ BUF _0, FEC _ BUF _1, and FEC _ BUF _2 are used to convert data from 8-bit wide to 16-bit wide, its effect is exactly the reverse of CW _ BUF _0, CW _ BUF _1, CW _ BUF _ 2. And the FEC _ BUF _0, the FEC _ BUF _1 and the FEC _ BUF _2 output the data after bit width conversion to the FEC _ OUT, and the FEC _ OUT completes the recombination of frame data.

FEC _ IN writes code words of downlink frame data into CW _ BUF _0, CW _ BUF _1 and CW _ BUF _2 respectively, and simultaneously sends a frame header indication signal FP of each downlink frame to the FP _ DELAY module, wherein FP is the frame header indication of the downlink frame, FP effectively represents the frame start of the downlink frame data, and plays a role of synchronous control between FEC _ IN and FEC _ OUT.

The function of FP _ DELAY is to DELAY the downstream frame header indication signal FP by a number of delayed clock cycles that is exactly equal to the total time required for the frame data to be decoded by CW _ BUF _0 and FEC _ CORE _0/CW _ BUF _1 and FEC _ CORE _1/CW _ BUF _2 and FEC _ CORE _ 2. In this way, FP _ DELAY outputs the downstream frame header FP to FEC _ OUT just synchronized with the decoded frame data after delaying by the appropriate number of clock cycles.

FEC _ OUT also determines the total byte length contained in each frame of data based on the transmission rate of the frame of data, and each time the count value indicates that the total byte length minus one fixed length byte has been received, the next data segment that should be read can be determined to be an end-of-frame data segment. When the FEC _ OUT receives the delayed downlink frame header FP output by the FP _ DELAY module, it indicates that the first data of the downlink frame has completed FEC decoding. Therefore, after receiving the downstream frame header FP output by FP _ DELAY, FEC _ OUT synchronously initializes the local byte counter of FEC _ OUT, counts the total number of bytes of the downstream frame, and alternately reads codeword data from FEC _ BUF _0 and FEC _ BUF _1, that is: the first codeword is read from FEC _ BUF _0, then the second codeword is read from FEC _ BUF _1, then the third codeword is read from FEC _ BUF _0, and so on. When the total number of the read bytes is equal to the number of bytes of frame data corresponding to the current rate, the FEC _ OUT removes check bits at the tail parts of the code words, then sequentially connects the code word contents, and then reconstructs decoded downlink frame data after removing the inserted extra 0.

Like FP DELAY block FP _ DELAY, FEC _ IN can write CW _ BUF _2 with the number of 0-insertions, CW _ BUF _2 is output to NUM _ response _ DELAY, which is a DELAY block that outputs the number of frame tail 0-insertions to FEC _ OUT block with the same DELAY as FP _ DELAY. Based on the frame end data, the FEC _ OUT removes 0 with a corresponding number from the frame end code word read from the FEC _ BUF _2, and finally obtains the residual byte of the frame end as the frame end data of the downlink frame.

As described above, the FEC _ OUT combines the data read OUT by the three codewords together to restore the data to the decoded downstream frame valid data, and outputs the data from the output port.

The function of the NUM _ response _ DELAY module is to provide a function of transferring the number of 0 inserted in each frame end data, but the existing GPON network mainly adopts two rates of 2.5G and 1.25G, and at the rate of 2.5G, each RS (255, 239) based FEC encoded downlink frame data includes 38880 bytes, which need to be cut into 153 codewords for decoding, and 135 0 need to be inserted in each frame end codeword; at the rate of 1.25G, each RS (255, 239) based FEC encoded downlink frame data includes 19440 bytes, and needs to be cut into 77 code words for decoding, and each frame end code word needs to be inserted with 195 0 s. When the codeword is sliced at other fixed length, for example, two 255-byte, i.e., 510-byte, the number of 0's inserted in each codeword is the same. If the current rate is known, FEC _ OUT can judge the number of 0 inserted IN the end frame data through the current rate, and it is not necessary to use the delivery mechanism to know the number of 0 inserted IN each end frame data from FEC _ IN, and IN this application scenario, the NUM _ response _ DELAY module may be omitted. The FEC _ OUT determines the total byte length included in each frame of data according to the transmission rate of the frame of data, and distinguishes two adjacent frames of data by using the count value of the local byte counter, specifically including: clearing the count value after recombining one frame data; the end-of-frame data segments are read from the dedicated decoding circuit each time the count value reaches the total byte length of one frame of data minus the fixed length of one frame of data segment.

If switching between a plurality of rates or the frequency of rate switching is high and the number of 0 s IN and OUT of each frame end data changes frequently, a transfer mechanism may be performed once each time rate switching occurs, FEC _ IN writes the number of 0 s IN CW _ BUF _2, CW _ BUF _2 is output to NUM _ response _ DELAY module, and NUM _ response _ DELAY is output to FEC _ OUT IN a delayed manner, and further, the transfer mechanism may be performed once when each frame end data is decoded to ensure that each frame data is correctly reassembled.

It should be noted here that each communication network is correspondingly provided with a current rate notification mechanism, and when communication starts or rate switching occurs, the current rate is notified to a corresponding processing module.

Two, alternate decoding mode

IN the working mode, FEC _ IN cuts frame data into code words, the code words are sent to FEC _ CORE _0, FEC _ CORE _1 and FEC _ CORE _2 for decoding by three-way FIFOs of CW _ BUF _0, CW _ BUF _1 and CW _ BUF _2 IN turn, when the tail part of the downstream frame data is cut, the last byte is not enough to form a code word with the length of 255 bytes, the FEC _ IN writes the frame tail code word into CW _ BUF _2, and simultaneously writes the number of 0 insertion into CW _ BUF _2, and FEC _ CORE _2 decodes the frame tail code word.

As mentioned above, when the number of 0 inserted into the end of frame is not required to be delivered, it is possible to provide that any one of the three decoding circuits decodes the first codeword of each frame data. However, if a delivery mechanism is required to guarantee, a decoding circuit for decoding the first codeword is selected in combination with an actual circuit structure, so that the end-of-frame codeword is written into a corresponding decoding circuit, and at the same time, the number of 0's that should be inserted is also written into the corresponding decoding circuit, for example: in the circuit structure shown in fig. 5, when the second decoding circuit, that is, FEC _ CORE _1, is agreed to decode the first codeword at the existing 2.5G and 1.25G rates, the end-of-frame codeword can be just input into CW _ BUF _2, and the transfer of the number of inserted 0 is completed through the second DELAY module NUM _ DELAY connected to CW _ BUF _ 2.

The frame header of the downlink frame indicates the fp signal delay mechanism and the process of re-assembling frame data at the FEC _ OUT end is completely the same as the first working mode.

Another decoding apparatus is configured as shown IN fig. 6, where a second DELAY module NUM _ DELAY is directly connected between FEC _ IN and FEC _ OUT, and the operation of inserting 0 IN the end-of-frame data segment is completed IN FEC _ IN, when the last remaining bytes are not enough to form a 255-byte-long codeword when the downstream frame data reaches the mantissa portion, FEC _ IN needs to insert 0 IN the last frame data, form a codeword by combining 0 and the end-of-frame remaining bytes, and write the end-of-frame codeword into CW _ BUF _ 2. The number of inserted 0 s is then sent to FEC _ OUT with a NUM _ response _ DELAY. The operation is exactly the same as the circuit shown IN fig. 5, except that the operation of inserting 0 is performed IN FEC _ IN.

Example two

When the real-time FEC decoding is implemented on the 8-bit wide downlink frame data, the structure of the decoding apparatus provided in the present invention is shown in fig. 7, and includes:

a first DELAY module FP _ DELAY connected between FEC _ IN and FEC _ OUT;

a second DELAY module NUM _ RESIDUE _ DELAY connected between CW _ BUF _1 and FEC _ OUT.

Similarly, the operation mode of the decoding apparatus is the same as that described in the first embodiment, and the operation process is completely similar, except that:

in the first working mode, the decoding work of the non-frame end code word is independently undertaken by FEC _ CORE _ 0;

in the second mode of operation, the two FEC _ CORE's take turns to decode.

Similarly, NUM _ response _ DELAY may be omitted when the number of 0's inserted in the end codeword of the frame need not be transferred. If the number of 0 inserted in the end of frame code word needs to be transferred, when the existing 2.5G and 1.25G rates exist, it is agreed that the FEC _ CORE _1 decodes the first code word of each frame data, so that the end of frame code word can be input into CW _ BUF _1, and the transfer of the number of 0 inserted is completed through the second DELAY module NUM _ DELAY connected to CW _ BUF _ 1.

As shown IN fig. 8, a second DELAY module NUM _ DELAY may also be connected between FEC _ IN and FEC _ OUT, where FEC _ IN specifically completes the operation of inserting 0 IN the end-of-frame data.

EXAMPLE III

When the real-time FEC decoding is implemented on 32-bit wide downlink frame data, the structure of the decoding apparatus provided by the present invention is as shown in fig. 9, and five decoding circuits are required to work in coordination, and the decoding apparatus specifically includes:

the fourth FEC decoding circuit comprises an input buffer module CW _ BUF _3, an FEC decoding module FEC _ CORE _3 and an output buffer module FEC _ BUF _3 which are connected in sequence;

the fifth FEC decoding circuit comprises an input cache module CW _ BUF _4, an FEC decoding module FEC _ CORE _4 and an output cache module FEC _ BUF _4 which are connected in sequence;

a first DELAY module FP _ DELAY connected between FEC _ IN and FEC _ OUT;

a second DELAY module NUM _ RESIDUE _ DELAY connected between CW _ BUF _4 and FEC _ OUT.

The operation mode of the decoding device is the same as that described in the first embodiment, and the operation process is completely similar, except that:

in a first working mode, the decoding work of the non-frame end code word is borne by four decoding circuits including FEC _ CORE _0-FEC _ CORE _ 3;

in the second working mode, the five-way decoding circuit decodes the data in turn.

Similarly, NUM _ response _ DELAY may be omitted when the number of 0's inserted in the end codeword of the frame need not be transferred. If the number of 0 inserted in the end of frame code word needs to be transferred, when the rate of 2.5G and 1.25G exist, it is agreed that the FEC _ CORE _3 decodes the first code word of each frame data, so that the end of frame code word can be input into CW _ BUF _4, and the transfer of the number of 0 inserted is completed through the second DELAY module NUM _ DELAY connected to CW _ BUF _ 3.

As shown IN fig. 10, a second DELAY module NUM _ DELAY may also be connected between FEC _ IN and FEC _ OUT, where FEC _ IN specifically completes the operation of inserting 0 IN the end-of-frame data.

To sum up, in a general case, assuming that the bit width of real-time data to be decoded is N, the input/output bit width of FEC _ CORE is M, and both N and M are generally integer multiples of 8, an N/M +1 multiplexing decoding circuit is required. The conventional FEC _ CORE is 8-bit wide input/output, so that the purpose of the present invention can be realized by multiplexing N ÷ 8+ 1-path decoding circuits in general.

The above embodiment takes decoding of downlink frame data of a GPON network as an example, and the technical solution provided by the present invention is also used in a network with other communication mechanisms to perform decoding processing on an uplink or downlink frame based on an FEC encoding mode, and is not limited to processing frame data based on an RS (255, 239) encoding format.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A forward error correction decoding device is characterized by comprising a frame data segmentation module, a frame data recombination module and at least two paths of FEC decoding circuits which are arranged in parallel; wherein,

2. The decoding apparatus of claim 1, wherein the decoding apparatus further comprises: and the first delay module is connected between the frame data segmentation module and the frame data reassembly module and is used for delaying and sending the frame header indication information sent by the frame data segmentation module to the frame data reassembly module, wherein the delay time is the time required for decoding the first data segment of each frame data.

3. The decoding apparatus according to claim 1 or 2, wherein the decoding apparatus further comprises a second delay module; and the frame data recombination module is connected between the frame data segmentation module and the frame data recombination module and is used for delaying the number of 0 inserted into the frame tail data segment by the frame data segmentation module and sending the frame tail data segment to the frame data recombination module, wherein the delay time is the time required for decoding each frame data frame tail data segment.

4. The decoding apparatus according to claim 1 or 2, wherein the decoding apparatus further comprises a second delay module; and the delay time is the time required for decoding each frame data frame tail data segment.

5. The decoding device according to claim 4, wherein the one-way decoding circuit in which the input buffer module connected to the second delay module is located is a dedicated decoding circuit for the end-of-frame data segment.

6. The decoding apparatus of claim 1, 2 or 3, wherein the FEC decoding module is an 8-bit wide input/output; and/or the input buffer module and the output buffer module are all first-in first-out FIFO memories.

7. The control method according to claim 1, wherein the frame data is RS (255, 239) based FEC encoded frame data, the fixed byte length is an integer multiple of 255 bytes, wherein each segment of 255 bytes contains 239 bytes of valid data, and the check code is 16 bytes.

8. A control method of the forward error correction decoding apparatus according to claim 1, wherein one FEC decoding circuit in the forward error correction FEC decoding apparatus is a dedicated decoding circuit for decoding end-of-frame data segments, and the other FEC decoding circuits are non-dedicated decoding circuits for decoding non-end-of-frame data segments, the control method comprising the steps of:

9. The method of claim 8, wherein the method further comprises: in the step a1, the frame data segmentation module distinguishes two adjacent frames of data according to the frame header identifier of the frame data.

10. The method of claim 9,

in step a1, the frame data segmentation module sends frame header indication information each time a new frame of data is received; the frame header indication information is delayed and sent to a frame data recombination module through a delay module, and the delay time is the time required for decoding the first data segment of the frame data;

in step a2, after receiving the frame header indication information, the frame data reassembly module reads the decoded first data segment of the frame data from the corresponding decoding circuit.

11. The method according to claim 10, wherein in step a2, the frame data reorganizing module determines a total byte length included in each frame data according to a transmission rate of the frame data, and initializes a count value of a local byte counter according to the total byte length each time the frame header indication information is received; and determining that the next data segment that should be read is the end-of-frame data segment when the count value indicates that the total byte length minus one fixed length byte has been received.

12. The method according to claim 9, wherein in step a2, the frame data reorganizing module determines a total byte length included in each frame data according to a transmission rate of the frame data, and distinguishes two adjacent frames of data and the tail data segment by using a count value of a local byte counter, which specifically includes:

13. The control method according to claim 11 or 12, wherein when the byte length of the end-of-frame data segment is smaller than the fixed byte length, before decoding the end-of-frame data, 0 insertion processing is performed on the end-of-frame data segment, and all inserted 0's are removed after decoding, wherein the position of the inserted 0's is before the last segment of valid data or between the last segment of valid data and the last FEC check code.

14. The control method according to claim 12,

the step a1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments written into the special decoding circuit, and simultaneously delays and sends the number of the inserted 0 to the frame data recombination module through a delay module, wherein the delay time is the time required by decoding the frame tail data segments; and

the step a2 further includes: and the frame data recombination module reads the decoded frame tail data segment from the special decoding circuit, removes all 0 inserted in the frame tail data segment according to the number of the inserted 0, and then recombines the frame data.

15. The control method according to claim 13,

in step a1, the frame data segmentation module writes the tail data segment into the dedicated decoding circuit, and writes the number of 0's to be inserted into the dedicated decoding circuit, the dedicated decoding circuit performs 0 insertion processing on the tail data segment, and the dedicated decoding circuit delays and sends the number of 0's to be inserted to the frame data reassembly module through a delay module, where the delay time is the time required for decoding the tail data segment;

16. The control method according to claim 13,

the step a1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments and then inputs the frame tail data segments into a special decoding circuit;

the step a2 further includes: the frame data reorganization module reads the decoded frame tail data segment from the special decoding circuit, determines the number of 0 to be inserted according to the transmission rate of the frame data, and reorganizes the frame data after removing all 0 inserted in the frame tail data segment.

17. The control method according to any one of claims 12 to 16, wherein the frame data is RS (255, 239) based FEC encoded frame data, the fixed byte length is an integer multiple of 255 bytes, wherein each segment of 255 bytes contains 239 bytes of valid data and 16 bytes of check code; and is

18. A control method of the forward error correction decoding apparatus as set forth in claim 1, said control method comprising the steps of:

19. The method of claim 18, wherein the method further comprises: in the step B1, the frame data segmentation module distinguishes two adjacent frames of data according to the frame header identifier of the frame data.

20. The method of claim 19,

in step B1, the frame data segmentation module sends frame header indication information each time a new frame of data is received; the frame header indication information is delayed and sent to a frame data recombination module through a delay module, and the delay time is the time required for decoding the first data segment of the frame data;

in step B2, after receiving the frame header indication information, the frame data reassembly module reads the decoded first data segment of the frame data from the corresponding decoding circuit.

21. The method according to claim 20, wherein in step B2, the frame data reassembly module determines a total byte length included in each frame data according to a transmission rate of the frame data, and initializes a count value of a local byte counter according to the total byte length each time the frame header indication information is received; each time the count value indicates that the total byte length minus a fixed length byte has been received, the next data segment that should be read is determined to be an end-of-frame data segment.

22. The method according to claim 19, wherein in step B2, the frame data reassembly module determines the total byte length included in each frame data according to the transmission rate of the frame data, and distinguishes two adjacent frames of data and the tail data segment by using the count value of the local byte counter, specifically comprising:

23. The control method according to claim 21 or 22, wherein when the byte length of the end-of-frame data segment is smaller than the fixed byte length, before decoding the end-of-frame data, 0 insertion processing is performed on the end-of-frame data segment, and all inserted 0's are removed after decoding, wherein the position of the inserted 0's is before the last piece of valid data or between the last piece of valid data and the last FEC check code.

24. The control method according to claim 23,

the step B1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments written into the corresponding decoding circuit, and simultaneously delays and sends the number of the inserted 0 to the frame data recombination module through a delay module, wherein the delay time is the time required by decoding the frame tail data segments; and

the step B2 further includes: and the frame data recombination module reads the decoded frame tail data segments from the corresponding decoding circuit, removes all 0 inserted in the frame tail data segments according to the number of the inserted 0 and then recombines the frame data.

25. The control method according to claim 23,

in step B1, the frame data segmentation module writes the frame tail data segment into the corresponding decoding circuit, and writes the number of 0's that should be inserted into the corresponding decoding circuit, the corresponding decoding circuit performs 0 insertion processing on the frame tail data segment, and the corresponding decoding circuit delays and sends the number of 0's that should be inserted to the frame data reassembly module through a delay module, where the delay time is the time required for decoding the frame tail data segment;

26. The control method according to claim 23,

the step B1 further includes: the frame data segmentation module performs 0 insertion processing on the frame tail data segments and then inputs the frame tail data segments into corresponding decoding circuits;

the step B2 further includes: the frame data recombination module reads the decoded frame tail data segments from the corresponding decoding circuit, determines the number of 0 to be inserted according to the transmission rate of the frame data, removes all 0 inserted in the frame tail data segments and then recombines the frame data.

27. The control method according to any one of claims 23-25, wherein the frame data is RS (255, 239) based FEC encoded frame data, the fixed byte length is an integer multiple of 255 bytes, wherein each segment of 255 bytes contains 239 bytes of valid data and 16 bytes of check code; and is