CN1839471B - Integrated circuit package with improved resistance and inductance of semiconductor components - Google Patents

Abstract

A semiconductor integrated circuit package includes a leadframe (108), the leadframe (108) including a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) disposed on at least two adjacent sides of the die. The addition of the bonding metal region (101a) increases the number of interconnections between the metal region (101a) and the die (100) to reduce resistance and inductance. Furthermore, if the surface area of the external termination device extending from the encapsulated plastic housing (106) continues to increase when it does not reach a maximum, heat dissipation can occur more quickly and external termination resistance can be reduced. The integrated circuit is applied to a MOSFET device, and the bonding metal region (101a) is used as a source (101). The bonding metal region may be "L" shaped, "C" shaped, "J" shaped, "I" shaped, or any combination thereof.

Description

Integrated circuit package with improved resistance and inductance of semiconductor components

technical field

The present invention relates to an integrated circuit package, in particular to an integrated circuit (IC) package for power semiconductor devices, such as metal oxide semiconductor field effect transistor (MOSFET) devices, which can reduce package resistance, inductance and thermal impedance, To make the device more efficient and release more power.

Background technique

State-of-the-art silicon technology is a MOSFET device that allows very low impedance power, resulting in the use of small chips that can be operated at relatively high power densities. In many cases, the package impedance may be equal to the silicon impedance, which is actually a very uneconomical way to use silicon as the main body of the device, and it is a constant trend to reduce the cost by reducing the package impedance . Due to the higher power density, the lower thermal impedance package is required. The reason why package parasitic inductance will be in the power supply switching mode, for MOSFET in the high frequency switching application mode often leads to wasting most of the power, while in the same package size with lower device impedance and improved technology It becomes more severe when higher operating currents are allowed.

Please refer to the bottom view shown in FIG. 1 , illustrating a conventional semiconductor package 1 including a die 10 encapsulated by a lead frame 8 and a plastic body 16 . In this prior art, the die 10 specifically describes a MOSFET device and its lead frame 8 includes a source terminal 11 , a gate terminal 12 and a drain terminal 13 . Source terminal 11 in leadframe 8 includes a plurality of separate source leadframe fingers or leads 11 b extending outward to plastic body 16 , and a plurality of separate inner source bonding regions 11 a bonded to bond wires 14 . The drain terminal 13 includes a plurality of separate drain lead frame fingers or leads 13b connected to the lead frame platform 13a. The gate terminal 12 includes an external gate lead 12b connected to an internal gate bonding region 12a connected to the gate land 17 by a wire 15 .

FIG. 2 is a bottom view of another conventional semiconductor package 19 . In this known technique, as shown in FIG. 1 , the source junction region 21 a in the source terminal 21 is added in a plurality of places where the source junction region 11 a is separated to form a bond wire 24 to the die 20. A single source junction region 21a. As in the prior art described above with respect to FIG. 1 , the separate source lead frame fingers or leads 21 b, and the separate drain lead frame fingers or leads 23 b of the drain terminal 23 are formed from the plastic body 26. Separate narrow metal strips radiate outwards and are suitable for installation as depicted in Figure 1, and plug into matching socket locations on the motherboard of a personal computer.

Similar to the known technique of FIG. 1 , the die 20 is disposed on the lead frame platform 23 a and a narrow edge frame is provided around the periphery of the die 20 . In addition, the bonding region 22a of the gate 22 is connected to the gate land 27 located at the closest corner by a wire 25 . In known techniques, the source and gate junction regions 11a, 21a and 12a, 22a share the same left side of the dies 10 and 20 . Likewise, source lead 21b and gate lead 22b radiate from the same left side.

Please refer to the bottom view of a conventional dual die semiconductor package 29 shown in FIG. 3 . The dual die semiconductor package 29 has a plastic body 36 encapsulating a first die 30 disposed on a first lead frame platform 33a and a second die 40 disposed on a second lead frame platform 43a . The first source terminal 31 at least includes a source lead frame lead 31 b and a source bonding region 31 a distributed along the left side of the first die 30 . The source bonding region 31 a is connected to the first die 30 through bonding wires 34 . The first gate terminal 32 includes a gate bonding region 32a sharing the left side of the first die 30, and a gate lead frame lead 32b. The gate bonding region 32 a is connected to the gate platform by a bonding wire 35 . The first drain terminal 33 includes a plurality of separate drain lead frame leads 33b combined with the first lead frame platform 33a.

Similar to the first die 30 , the second source 41 at least includes a source lead frame lead 41 b and a source bonding region 41 a distributed along the left side of the second die 40 . This source bonding region 41 a is interconnected with the second die 40 via a bonding wire 44 . The second gate terminal 42 has a gate bonding region 42 a sharing the left side of the second die 40 and a gate lead frame lead 42 b. Bonding wires 45 are used for interconnection. The second drain terminal 43 includes a plurality of separate drain lead frame leads 43b combined with the second lead frame platform 43a.

As explained above, in order to improve the power dissipation of a MOSFET device carrying high current, it is necessary to reduce the package resistance, inductance and design a new lead frame and package.

In this regard, the source terminal and the interconnection between the die can be reduced by reducing the size of the die and the lead frame platform to increase the bonding area by utilizing some of the entities in the package plastic body, so that the resistance and inductance of the package can be reduced . The reduction in impedance comes from having more wires connected in parallel, although the improved inductance not only comes from having more wires connected in parallel, but also by spreading the wires further apart, thereby reducing the mutual coupling inductance effect between the wires.

In addition, increasing the lead surface area of the external source and drain, so that a larger surface area is exposed to the air, can effectively reduce the external terminal impedance and speed up the heat dissipation efficiency.

Contents of the invention

The improved integrated circuit package provided by the present invention effectively solves the long-standing problems in the above-mentioned background art in a direct and simple manner.

In general, the present invention provides a method of improving semiconductor packaging by redistributing a bonding area, such as for a source or other high current-carrying terminal, by discarding some physical locations reserved for silicon or die, Increased interconnection between this bonding region and the conductive surface at the top of the die near the corners and adjacent sides of the die reduces resistance and inductance.

The present invention provides an "L" shaped bonding area, a "C" shaped bonding area, a "J" shaped bonding area and/or an "I" shaped bonding area, or any number of dies integrated into the package combined.

In addition, the present invention provides a method for increasing the surface area of the external source and the terminal area of the drain to achieve faster heat dissipation and reduce external terminal resistance. In other words, increasing the area of leadframe metallization improves the thermal resistance of the package. This may include fusing all or some of the leads of a terminal or a portion thereof.

Description of drawings

1 is a bottom view of an example of a first embodiment in a conventional semiconductor package;

2 is a bottom view of a second embodiment example in a conventional semiconductor package;

3 is a bottom view of a third embodiment example in a conventional dual-die semiconductor package;

4 is a bottom view of an exemplary semiconductor package for describing the first embodiment of the present invention;

5 is a bottom view of an exemplary semiconductor package for describing a second embodiment of the present invention;

6 is a bottom view of an exemplary semiconductor package for describing a third embodiment of the present invention;

FIG. 7 is a bottom view of a design example of a semiconductor package with dual platforms for dual dies describing the fourth embodiment of the present invention;

8 is a bottom view illustrating a design example of a semiconductor package with dual platforms for multiple dies according to a fifth embodiment of the present invention;

9 is a bottom view illustrating a design example of a semiconductor package with a single platform for multiple dies according to the sixth embodiment of the present invention;

FIG. 10 is a bottom view illustrating a design example of a semiconductor package with a single platform for multiple dies according to the seventh embodiment of the present invention;

FIG. 11 is a bottom view illustrating an example design of a semiconductor package with dual platforms for dual dies according to the eighth embodiment of the present invention;

12 is a bottom view illustrating a design example of a semiconductor package with a single platform for a dual die according to the ninth embodiment of the present invention;

13 is a bottom view of an exemplary semiconductor package design including a single platform for a single die, illustrating a tenth embodiment of the present invention;

FIG. 14 is a bottom view illustrating a design example of a semiconductor package with a single platform for a dual die according to an eleventh embodiment of the present invention;

15 is a bottom view illustrating a design example of a semiconductor package with a single platform for a dual die according to a twelfth embodiment of the present invention;

16 is a bottom view illustrating a design example of a semiconductor package with a single platform for multiple dies according to a thirteenth embodiment of the present invention;

FIG. 17 is a bottom view illustrating a design example of a semiconductor package with dual large platforms for multiple dies according to the fourteenth embodiment of the present invention;

18 is a bottom view illustrating a design example of a semiconductor package for multi-die of the fifteenth embodiment of the present invention, and

FIG. 19 is a bottom view illustrating an exemplary design of a semiconductor package for multi-die according to the sixteenth embodiment of the present invention.

Detailed ways

Referring to FIG. 4 , the semiconductor integrated circuit (IC) package of the present invention is denoted by reference numeral 99 . In general, the semiconductor integrated circuit (IC) package 99 includes a semiconductor die 100 disposed on a lead frame platform 103 a and molded in a plastic body 106 . The package 99 also contains the necessary interconnections known in the art, whereby the die 100 can be incorporated in the leadframe platform 103a and/or the leadframe 108 . The specific description is as follows:

As with any description provided below, the present invention is applicable to many related semiconductor devices. In other words, any third person describing any applicability of the invention should be prohibited. For example, the bottom view of FIG. 4 in this embodiment shows that at least three terminals (such as: a source terminal 101, a gate terminal 102, and a drain terminal 103) can be applied to the metal oxide semiconductor integrated into the lead frame 108 Semiconductor integrated circuit package 99 for field effect transistor devices.

The interconnection of the semiconductors of the present invention is described below. By reducing the size of the die 100 and leadframe platform 103a to approximately at least the length of a portion of the top of the die 100, and increasing the size of the metal bonding region 101a of the source terminal 101 near the corners thereof, the described aspects of the present invention can be achieved. Purpose.

The "L" shaped footprint of the source metal bonding region 101a can increase the source bonding area more than in the prior art. In this embodiment, its partial length is approximately equal to half the length above the die. However, as in the other embodiments below, this length can also be exactly equal to the entire length of its packaged upper surface. However, the increase of the source bonding region 101 a also increases the number of source bonding wires 104 interconnecting the source terminal 101 and the die 100 . Furthermore, the distance between the bond wires 104 does not result in an increase in the number of bond wires 104 . Instead, increasing its wire distance does improve inductance. For example, it is estimated that the number of source bond wires 104 can be increased by 30% to 40% compared to known lead frame designs, as shown in FIGS. 1 and 2 . The addition of these source bond wires 104 bonded to the top of the conductive surface of the die provides a lower bond loop for the interconnect. In this way, the impedance and inductance of the package are reduced.

Furthermore, in this embodiment, since the first leg 101aa is shorter than the second leg 101ab, the "L" shaped footprint exhibits a rotation of approximately 180 degrees. However, in other embodiments or designs, the first pin 101aa may be longer due to different configurations. For example, as shown in FIG. 7, the footprint of the "L" shape shows that the "L" shape is rotated approximately 90 degrees because the second leg 201ab appears to be shorter than the first leg 201aa.

In the embodiment shown in FIG. 4 , the increase in the number of bonding wires 104 is achieved by reducing the portion of the leadframe platform 103 b along the bottom surface of the die 100 . Generally, a bonding wire 105 is sufficient for interconnecting the die 100 and the gate terminal 102 since the gate of the Mosfet device handles a relatively small current. The gate bonding region 102a of the gate terminal 102 extends along a portion of the bottom surface of the die 100 or its lead frame platform 103a. In this embodiment, the gate bonding region 102 a extends slightly less than half the length of the bottom surface of the package 99 . Along the bottom surface of the die 100 , a gate mesa 107 is provided substantially at the center of the die 100 . The distribution of the gate bond region 102 a along a portion of the length of the bottom surface of the die 100 provides a direct path for the connection of the bond wire 105 . The gate lead 102b protrudes from the left side of the plastic body 106 .

The movement of the gate platform 107, away from the bottom left corner, releases the left side including the bottom left corner corresponding to the gate platform 107, so that the source bonding wire 104 can be fully and uniformly bonded along the left side, including Down to the bottom left corner of die 100 . In addition, the "L"-shaped bonding region 101a for the source terminal 101 allows the source bonding wire 104 to bond to the first leg 101aa to interconnect to the top surface of the die 100 and be closely spaced on the top of the die 100. right corner.

Within the plastic body 106, the die 100 is attached using conductive silver (Ag) epoxy on top of the leadframe platform 103a, which is part of the metal termination 103 of the drain. Within the plastic body 106 , the leadframe platform 103 a extends to the physical area of the plastic body 106 along the top and bottom surfaces of the die 100 next to the first pin 101 aa of the source bonding region 101 a and the gate bonding region 102 a. Therefore, the area of the leadframe portion 103b where the leadframe platform 103a is fused or integrated outside the right drain of the die 100 is generally not reduced.

In this embodiment, the footprint of the lead frame platform 103a is not limited to the general shape of the die 100, so that a narrow width edge can be created around it. The perimeter of the die 100 about the edge of the plastic body 106 has been reduced to provide the necessary space for placement of the first leg 101aa of the source "L"-shaped bonding region 101a and the gate bonding region 102a. Therefore, references to the "L" shape can be defined for the two embodiments described above.

The source outer lead frame termination portion 101b and the drain outer lead frame termination portion 103b extending outwardly to the plastic body 106, both of which are substantially continuous, sufficiently complete individual lead frame connections or leads of conventional known art , as shown in Figure 1 and Figure 2. More particularly, the enlarged surface area of the source lead frame termination portion 101b and the drain lead frame termination portion 103b increases the surface area exposed to air that is nearly conventional for individual lead frame connections or leads 11b and 13b. package twice as shown in Figure 1. Therefore, the enlarged outer lead frame terminal portions 101b and 103b will dissipate heat more quickly, especially the heat generated during current loading. In addition, its enlarged source and drain lead frame termination portions 101b and 103b will reduce package thermal resistance.

In this embodiment, the external surface areas of the source terminal 101 and the drain terminal 103 are increased. In the embodiment of FIG. 4 , the external surface area of source terminal 101 and drain terminal 103 is maximized by providing a single integral external leadframe termination for each along the left and right sides of plastic body 106 . However, conventional designs of PC motherboards (not shown) use holes that match the pattern and number of lead frame connections or leads so that the package can be surface mounted. Therefore, a PC motherboard (not shown) needs to be modified to adapt to the design of the source terminal 101 , the gate terminal 102 and the drain terminal 103 of the present invention.

Please refer to another embodiment of the integrated circuit package 109 shown in FIG. 5 . The embodiment shown in FIG. 5 is similar to that of FIG. 4, and only the differences will be described in detail here. In order to eliminate the above-mentioned need to modify the connection method of the PC main board, the bottom parts 111bb and 113bb of the lead frame can be separately provided and attached to the bottom parts of the source terminal 111 and the drain terminal 113 respectively. However, the upper portions of the source terminal 111 and the drain terminal 113 remain continuously extended and substantially fixed, such that a single metal strip 111ba for the source terminal 111 can radiate from the left side of the plastic body 116, and a single metal strip 111ba for the drain terminal 113 The metal strip 113ba can radiate from the right side of the plastic body 106 . The source terminal 111 includes an “L”-shaped metal bonding region 111 a whose pins 111 aa and 111 ab can be fused to the single metal strip 111 ba and bonded to the die 110 through the bonding wire 114 .

Another embodiment of the present invention is shown in FIG. 6 . Since the embodiment shown in FIG. 6 is similar to the embodiments described in FIGS. 4 and 5 , only the differences are described in detail here. The embodiment shown in FIG. 6 depicts an integrated circuit package 119 including a discontinuous "L" shaped bonding area 121a. More particularly, the second leg of the "L"-shaped bonding region 121 a is formed by a plurality of separate metal portions distributed along the entire length of the left side of the die 120 . However, it can be seen that the first leg 121aa is continuous and may be fused or integrated to the highest portion of the discontinuous second leg 121ab.

In addition, in this embodiment, the external terminal portions of the source and the drain may include separate lead frame wires or leads 121 b and 123 b for the source terminal 121 and the drain terminal 123 , respectively. Each metal portion of the second discontinuous leg 121 ab is associated therewith with a respective lead frame wire or lead 121 b that extends outwardly to the plastic body 126 . The die 120 may be disposed on a leadframe platform 123a.

Each metal portion of the discontinuous second pin 121 ab is connected to the die 120 through the bonding wire 124 . Although, the embodiment shown in FIG. 6 provides a discontinuous "L"-shaped joint area 121a, the surface area of this joint area 121a is sufficiently increased to exceed the joint area shown in FIG. 3 in the prior art.

Please continue to refer to FIG. 7 , which shows a dual die integrated circuit package 199 . For purposes of the present invention, FIG. 7 is a bottom view showing a two-MOSFET device, in a dual die integrated circuit package 199, each die comprising three dies provided by its leadframes 208 and 218. terminals (eg, source terminals 201, 211, gate terminals 202, 212 and drain terminal devices 203, 213). The first source terminal 201 includes an outer lead frame terminal portion 201b and a first “L”-shaped metal bonding region 201a integrated with the outer lead frame terminal portion 201b. The first source metal bonding region 201a generally has an "L" shaped footprint including a first pin 201aa connecting the first die 200 to a portion of the highest surface (first side) of the first lead frame platform 203a , and a second pin 201ab extending along a portion of the left side (second side) of the first die 200 or the lead frame platform 203a. This wire 204 is evenly bonded along the uppermost side of the first die 200 and along the left side.

In this embodiment, the gate bonding region 202 a of the first die 200 and the second pin 201 ab can share the left side. Besides that, bonding wires 205 are sufficient for the interconnection between the first die 200 and the gate terminal 202. In this embodiment, a gate platform 207 is provided at the bottom left corner of the first die 200 . Gate leads 202b and 212b may share the same left side of plastic body 206 .

The second source terminal 211 includes an outer lead frame terminal portion 211b and a second “L”-shaped metal bonding region 211a integrated with the outer lead frame terminal portion 211b. The metal bonding region 221a of the second source typically has an "L" shaped footprint that includes a first pin that connects the second die 210 to a portion of the highest surface (first side) of the second leadframe platform 213a. 211aa, and a second pin 211ab extending along a portion of the left side (second side) of the second die 210 or the lead frame platform 213a. The connecting wires 214 are evenly bonded along the highest surface of the second die 210 and along the left side.

Similar to the gate bonding region 202a of the first die 200, its gate bonding region 212a shares the left side with the second pin 211ab. Besides, a single bonding wire 215 is sufficient for the interconnection between the second die 210 and the gate terminal 212. A gate platform 217 is provided at the bottom left corner of the second die 210 .

In this embodiment, the source junction regions 201a and 211a have been increased to more than twice the prior art design, as shown in FIG. 3 . In this regard, this embodiment not only reduces the impedance of the source interconnection lines 204 and 214 and the surface propagation impedance of the dies 200 and 210, but also reduces the inductance effect.

The first die 200 is attached on top of a lead frame or copper (control device) platform 203 a containing a plurality of separately disposed drain leads 203 b that contact and extend outwardly outside the plastic body 206 . Likewise, a second die 210 is attached on top of a lead frame or copper (control device) platform 213a containing a plurality of separately disposed drain leads 213b that contact and extend outwardly outside the plastic body 206 .

Please refer to another embodiment of a multi-die semiconductor package 299 shown in FIG. 8 . As shown in the bottom view of FIG. 8 , there is a dual die semiconductor package 299 containing two MOSFET devices. Die 310 includes three terminals (eg, source terminal 312 , gate terminal 305 and drain terminal 313 ). Die 300 includes a gate terminal 303 and a drain terminal 301 . The source of the die 300 is connected to the leadframe platform 313 a by a bond wire 302 . The dual die semiconductor package 299 further includes an electronic component 320, which may be another die, a resistor or a capacitor, and so on. In this embodiment, electronic component 320 is a die structure of an integrated circuit bonded to die 310 by bonding wire 318 .

The source terminal 312 of the die 310 includes an external lead frame termination portion or lead 312b and an "L" shaped metal bonding region 312a integrated with the external lead frame termination portion or lead 312b. The source metal bonding region 312a generally has an "L" shaped footprint including a first pin 312aa connecting the die 310 to a portion of the bottom surface (first side) of the second leadframe platform 313a and along the die 313a. 310 or the second pin 312ab extending from a part of the left side (second side) of the lead frame platform 313a. The bonding wire 315 is substantially evenly bonded along the bottom and left sides of the die 310 .

In this embodiment, the bonding wire 302 is evenly bonded to the bottom of the die 300 and to the lead frame platform 313a.

In this embodiment, the gate bonding region 303 a of the first die 300 is bonded to the gate mesa at the uppermost right corner of the die 300 through a bonding wire 304 a. The gate bonding region 305a of the second die 310 is bonded to the gate mesa at the uppermost left corner of the die 310 by a bonding wire 307a.

The drain terminal 301 of the die 300 includes a lead frame platform 301a to which a drain lead 301b is bonded. The drain terminal 313 of the die 310 includes a drain lead 313b. Drain terminals 301 and 313 are located on opposite sides of package 299 . In addition, the gate terminals 303 and 305 and the corresponding gate leads 303b and 305b are disposed opposite to the package 299, respectively.

Please refer to FIG. 9 , which shows an embodiment of a multi-die semiconductor package 339 . In this embodiment, there are at least three die structures 346a having MOSFET devices and an integrated circuit die 354 . The three dies 340 and 354 share the same leadframe platform 346a. In addition, source terminal 342 includes a discontinuous "L" shaped junction region 342a. More particularly, the second leg of the "L"-shaped bonding region 342a is formed by the first leg 342aa fully extending along the length of the uppermost surface of the plastic body 350, so that the die 340 is at least There are two that can share the first pin 342aa to connect the bonding wires 352 and 356 to their respective die 340 .

In addition, the second leg 342ab of the “L”-shaped joint region 342a includes a plurality of separately disposed metal portions, which are distributed along the entire length of the left side of the plastic body 350 . However, it can be seen that the first leg 342aa is continuous and may be fused or integrated to the highest portion of the discontinuous second leg 342ab. Each of the plurality of separately disposed metal portions of the second pin 342ab is bonded to a source lead 342b and 344b.

Besides, in this embodiment, the drain terminal 346 includes a plurality of lead frame wires or lead wires 346 b combined with the lead frame platform 346 a and radiating out from the right side of the plastic body 350 .

Gate terminal 348 and its lead 348 b are shared by die 340 . The bonding region 348 a of the gate is connected to a gate platform of the die 340 through a bonding wire 349 . In this embodiment, each die 340 has two gate mesas used to interconnect the gate terminals of the die 340 through bonding wires 351 . This die 354 is connectable to the uppermost side of die 340 to the left and above by bond wires 358 .

Notably, the embodiment of FIG. 9 provides an "L" shaped junction area that extends substantially along the length of the uppermost face of plastic body 350 and its left side, and shares this area with the multi-grain structure. Thus, a higher density package can be produced without compromising its in-line impedance and inductance parameters.

Referring to FIG. 10 , another embodiment of a multi-die semiconductor package 358 is shown. In this embodiment, the package contains two mosfet devices 360 in close proximity with "L" shaped source terminals 368 and 372 .

The source terminal 368 includes an outer lead frame termination portion 368b and an "L" shaped metal bonding region 368a integral with the outer lead frame termination portion 368b. “L” shaped metal bond region 368 a is bonded to die 360 by bond wire 366 . The other source terminal 372 includes an outer lead frame termination portion 372b and an "L" shaped metal bonding region 372a integral with the outer lead frame termination portion 372b. Each "L" shaped metal bonding area 368a and 372a is disposed at opposite corners of the plastic body 378 . In this embodiment, it may be located at the bottom corner. In addition, the second leg 368ab of the "L"-shaped bonding area 368a includes a plurality of separate metal portions that are substantially distributed along the entire length of the left side of the plastic body 378 . Each of the plurality of separately disposed metal portions of the second pin 368ab includes a bonded source lead 368b. Likewise, each of the plurality of separately disposed metal portions of the second pin 372ab includes a combined source lead 372b. The "L" shaped bonding region 372a is bonded to its die 360 by a bonding wire 374 .

In this embodiment, the source lead 368b of a first die 360 can be on the opposite side of the plastic body 378 as the source lead 372b of the second die 360 . The die 360 may be disposed on top of a lead frame platform 376 . The lead frame platform 376 also contains another integrated circuit die 370 with a plurality of terminals A and a pair of terminals B. This B terminal is bonded to the gate platform of die 360 . This A terminal is bonded to leads 362 distributed across the package 358 . Leads 362b are bonded to bond regions 362a whose bond wires are each connected to the A terminal.

Please refer to FIG. 11 , which shows another embodiment of a dual-die semiconductor package 390 . Package 390 contains two dies 400, the first on lead frame platform 410a and the other on lead frame platform 414a. The lead frame platform 410a has a plurality of drain leads 410b; and the lead frame platform 414a has a plurality of drain leads 414b. Source terminals 402 and 404 contain "L" shaped metal junction regions 402a and 404a, respectively. While its "L" shaped metal joint area 404a is located at the bottom left corner of the plastic body 408, the "L" shaped metal joint area 402a is located at the top left corner of the plastic body 408. Region 402a is made bondable to the tallest die 400 by bond wire 418 ; and region 404a is made bondable to the bottom die 400 by bond wire 416 .

In this embodiment, the pins 402aa extend substantially along the length of the topmost surface of the first die 400 ; the pins 404aa substantially extend along the length of the bottommost surface of the second die 400 .

Gates 406 and 412 have gate leads bonded to the gate mesa by bond wires 420 and 424, respectively. The gate mesa is substantially centered on one side of die 400 . These gate leads are bonded between source leads 402b and 404b of source terminals 402 and 404, respectively.

In this embodiment, the left side of each die 400 is shorter than the top and bottom sides of the die 400 . Thus, the "L" shaped bonding regions 402a and 404a contain second legs 402ab and 404ab extending along the left sides of their respective dies.

Please refer to FIG. 12 , the embodiment in FIG. 12 is different from FIG. 11 , in that the die 450 in FIG. 12 shares the same lead frame platform 460 a. Thus, the drain lead terminal 460 b of the drain terminal 460 may be distributed along one side of the plastic body 458 of the package 440 .

Please refer to FIG. 13 , which is a single die structure package 498 . The die structure package 498 includes a die 500 disposed on a lead frame platform 510 a , wherein the lead frame platform 510 a includes a plurality of drain leads 510 b forming the drain 510 . Die 500 includes a source terminal including two "L" shaped metal bonding regions 502a and 504a, respectively. When the "L" shaped metal joint area 504a is located at the bottom left corner, this "L" shaped metal joint area 02a can be located at the top left corner of the plastic body 508 . The second pin 502ab includes a plurality of metal parts. The first pin 502aa and the second pin 502ab of the "L"-shaped metal bonding region 502a are combined with the top of the die 500 through the bonding wire 518 along the topmost surface and the left side of the die structure. The first leg 504aa and the second leg 504ab of the "L"-shaped metal bonding region 504a are bonded to the top of the die 500 by bonding wires 516 along the bottommost and left sides of the die structure.

Please refer to FIG. 14. The package 530 of FIG. 14 is different from the source terminals 542 and 544 in FIG. 13. The source terminals in FIG. 544a. The "J" shaped metal bonding area 542a includes a top "C" shaped metal bonding area radiating from the opposite side of the plastic body 548 that radiates from the exact opposite corresponding lead 542b. The "C" shaped metal bonding region 542a includes a single continuous highest region 542aa and two end side regions 542ab vertically integrated with the continuous region 542aa. Side areas 542ab are provided on the left and right, respectively. The “J” shaped metal joint area 542 a further includes a metal joint area 556 extending along the left side of the plastic body 548 . Metal bond region 556 is where source lead 542b is bonded. The "J"-shaped metal bonding region 542a is combined with the top of the die 540 by bonding wires 558 evenly distributed on the highest surface and the highest parts of the left and right sides.

The "C" shaped metal bonding region 544a includes a single continuous bottom region 544aa and two end side regions 544ab vertically integrated with the continuous region 544aa. The side regions 544ab are diametrically opposite to the left and right of the plastic body 548 . The "C"-shaped metal bonding region 544a is combined with the bottom of the die 540 through the bonding wires 546 evenly distributed on the bottom surface and the bottom surface portions of the left and right sides.

The package 530 further includes an electronic component 554 on the lead frame platform 550a, such as a semiconductor die structure, a resistor or a capacitor, and the like. In this embodiment, the grain structure of the electronic component 554 is bonded to the uppermost surface of the grain structure 540 by a bonding wire 560 .

The drain terminal 550 includes a plurality of drain leads 550b disposed between the topmost source lead 542b and the bottom source lead 544b , which are located on the right side of the plastic body 548 . Gate terminal 552, and more particularly, its gate lead 552b, is disposed to the left of plastic body 548 between "J" shaped metal junction region 542a and "C" shaped metal junction region 544a. This gate bonding region 552a can be combined with a gate land via bonding wire 557 . 

Referring to FIG. 15, the package 570 includes a source terminal 582 formed by a single "J"-shaped metal bonding region 582a. The "J" shaped metal bonding area 582a includes a top "C" shaped metal bonding area containing two pairs of diametrically opposite corresponding leads 582b radiating from opposite sides of the plastic body 586 . The "C" shaped metal junction region 582a may include a single continuous top region 582aa and two end side regions 582ab vertically integrated opposite the continuous region 582aa. The side areas 582ab are respectively disposed on the left and right, however, they are not directly connected to the continuous area 582aa. Instead, its side regions 582ab are discontinuous near the uppermost left and right corners. The "J" shaped metal joint area 582a further includes a metal joint area 584 extending along the left side of the plastic body 586 below the left side area 582ab. Metal bond region 556 has source lead 582b bonded there. The "J"-shaped metal bonding region 582a is bonded to the top of the die 580 by bonding wires 588 evenly distributed on the highest surface and the highest portions of the left and right sides.

Die 580 is disposed on lead frame platform 590 and has drain lead 590b radiating from the right side of plastic body 586 to form drain terminal 590 . The drain lead 590b can share the right side with the lead 582b of the source terminal 582 . Gate terminal 592 may be provided at the bottom left corner of package 570 . The bonding region of the gate is bonded to die 580 by bonding wire 554a and includes gate lead 592b. Obviously, the number of drain leads 590b of the drain terminal 590 has been reduced, while the number of source terminals has been increased, so that there are source leads 582b on both sides of the plastic body 586 .

Package 570 further includes an electronic component 594 bonded to the top of die structure 580 by bonding wire 598 .

Please refer to FIG. 16 , the package 599 is similar to the package 339 in FIG. 9 . The embodiment shown in FIG. 16 differs from FIG. 9 in that the "L"-shaped metal bonding region 602a of the source terminal 602 includes two sets of diametrically opposite corresponding leads 602b emanating from the left and right sides of the package 599 . The source lead 602b extends from the opposite end of the first pin 602aa.

Referring to Figure 17, package 747 is similar to Figure 14 except that the package is doubled. In this embodiment, the tallest die 750 contains a top "J" shaped metal junction region 752a and a bottom "C" shaped metal junction region 754 . The bottom die 750 includes a bottom "C" shaped metal junction region 760 and a top "J" shaped metal junction region 756. The two "C" and "J" shaped metal joining regions 754 and 756, due to their close proximity to each other, can be sufficiently fused together to form a substantially central "I" shaped metal joining region 777. . This center may be bonded wires 780 and 785 through metal bond region 777 to the top and bottom of die 750, respectively.

Please refer to FIG. 18, the package 818 includes two dies 800a and 800b and two electronic components 802a and 802b arranged on lead frame platforms 820a and 830a respectively, wherein the electronic components can be semiconductor dies, capacitors, transistors, etc. wait. In this embodiment, the electronic components 802a and 802b are respectively bonded to the dies 800a and 800b through bonding wires 814 .

The source terminal 804 of the die 800a includes a source lead 804b and a metal bonding region 804a extending substantially the length of the die 800a. Likewise, source terminal 808 of die 800b includes source lead 808b and a metal bonding region 808a extending substantially the length of die 800a.

The gate terminal 806 of the die 800a includes a gate lead 806b, wherein the gate lead 806b and the source lead 804b are parallel to each other. The gate metal bonding region 806a is parallel to the partial metal bonding region 804a. The gate metal bonding region 806 a is bonded to the gate mesa by bonding wire 824 . In this embodiment, the gate mesa is bonded to the right lower corner of die 800a. Likewise, the gate terminal 810 of the die 800b has a gate lead 810b parallel to the source lead 808b. The gate metal bonding region 810a is parallel to the partial metal bonding region 808a. Gate metal bonding region 810a is bonded to the lower corner gate mesa on the right side of die 800a via bonding wire 824 .

Drains 820 and 830 include drain leads 820b and 830b bonded to leadframe lands 820a and 830a, respectively.

Please refer to FIG. 19 , which is a top view of a semiconductor package 888 , which is a more specific design of a single die according to the sixteenth embodiment of the present invention. This package 888 differs from previous designs in that the source terminal 844 includes a plurality of leads 844b, 846b, and 848b connected to metal bonding regions 844a, 846a, and 848a, respectively. Metal bond regions 844 a and 848 a extend along the length of die 840 and are bonded to die 840 by bond wire 856 . Source lead 846b is located between leads 844b and 848b. However, metal bonding region 846a is parallel to at least a portion of metal bonding regions 844a and 848a. Likewise, metal bond region 846 a is bonded to die 840 by bond wire 856 . Inside the plastic body 866, the grains 840 decrease in size along the source facet. According to the above, the size of the source capping metal junction regions (regions 844a, 846a and 848a) is increased.

Gate lead 850b of gate terminal 850 is parallel to source leads 844b, 846b, and 848b. The gate metal bonding region 850 a is bonded to the gate mesa by bonding wire 864 . In this embodiment, the gate mesa is bonded to the center of the bottom surface of the die 840 .

The drain terminal 880 includes a plurality of drain leads 880b, wherein the drain leads 880b are bonded to the lead frame platform 880a.

In summary, although the present invention has only been described above as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Modification and retouching, so the scope of protection of the present invention should be defined by the claims.

Claims (31)

1. a semiconductor integrated circuit package is characterized in that, comprises:

One grainiess comprises an integrated circuit; And

One lead frame, this lead frame includes a leadframe pad that is arranged under this grainiess, with one source pole metal bond zone, this source metal engaging zones contains a first along a part of distribution of lengths of first of this grainiess, with a second portion that distributes along second of this grainiess physical length, described first is the highest of this grainiess, and described second is the left side of this grainiess.

2. encapsulation as claimed in claim 1 is characterized in that, further comprises:

The closing line of a plurality of first and second distributions along this grainiess, this closing line can along with the interconnective metal bond of this grainiess zone in first and second part distribute and combine with it.

3. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One plastic body, it is around grainiess, and the lead frame of at least a portion and moulding; And

One first single continuous outer lead frame slice, it is that to be positioned at this plastic body outside and radiate out from the second portion in this metal bond zone.

4. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One second single continuous outer lead frame slice, it is that to be positioned at this plastic body outside and radiate out from this leadframe pad.

5. encapsulation as claimed in claim 4 is characterized in that:

Described integrated circuit is a mos field effect transistor device;

The described first single continuous outer lead frame slice is the one source pole end; And

The described second single continuous outer lead frame slice is a drain electrode end.

6. encapsulation as claimed in claim 5 is characterized in that, described lead frame further comprises:

One gate terminal comprises a gate metal engaging zones along a part of distribution of lengths of the 3rd of grainiess, and described the 3rd face is in abutting connection with second; And

One lead frame lead-in wire, it is positioned at the plastic body outside; And

One gate pad, it is bonded to grainiess.

7. encapsulation as claimed in claim 6 is characterized in that, described gate pad is the 3rd the center that is incorporated into this grainiess fully.

8. encapsulation as claimed in claim 4 is characterized in that, is combined with the lead frame pin that a plurality of branches are arranged on the described first and second single continuous outer lead frame slices.

9. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One plastic body, it is around grainiess, and the lead frame of at least a portion and moulding;

One first a plurality of outer lead frame lead-in wires, it is positioned at this plastic body outside, and is radiated out by the second portion in metal bond zone; And

One second a plurality of outer lead frame lead-in wires, it is positioned at this plastic body outside, and radiates out from leadframe pad.

10. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One second grainiess includes one second integrated circuit; And

One second lead frame, include second leadframe pad that is arranged under this second grainiess, with one second metal bond zone, this second metal bond zone contains one along the first of a part of distribution of lengths of first of second grainiess and a second portion along a part of distribution of lengths of second of second grainiess.

11. encapsulation as claimed in claim 10 is characterized in that, the described lead frame and second lead frame also comprise respectively:

One gate terminal contains a gate metal engaging zones along the remaining part distribution of lengths of this second grainiess; And

One lead frame lead-in wire, it is positioned at the plastic body outside, and

Further also comprise:

One first grid platform, it is bonded to a corner of described grainiess; And

One second grid platform, it is bonded to a corner of described grainiess.

12. encapsulation as claimed in claim 1 is characterized in that, described second portion is along whole length of second of grainiess and distribute in discontinuous part.

13. encapsulation as claimed in claim 1 is characterized in that, described metal bond zone is " L " shape near top corners.

14. encapsulation as claimed in claim 1 is characterized in that, described metal bond zone comprises the zone of two " L " shapes, one near top corners, another is near bottom corner.

15. encapsulation as claimed in claim 1 is characterized in that, described metal bond zone is " J " shape being positioned near the top end of grainiess.

16. encapsulation as claimed in claim 1 is characterized in that, described metal bond zone also comprises one " C " shape zone in the bottom end that is positioned at grainiess.

17. encapsulation as claimed in claim 1 is characterized in that, described metal bond zone is " J " shape.

18. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One second grainiess is integrated on this leadframe pad and with described grainiess is parallel and separates;

One second metal bond zone,

Wherein, described metal bond zone comprises near first " L " shape metal bond zone of two adjacent surfaces that is distributed in grainiess, and the described second metal bond zone comprises near second " L " shape metal bond zone of two adjacent surfaces that is distributed in second grainiess.

19. encapsulation as claimed in claim 18 is characterized in that, further comprises an electronic building brick, it is integrated on the described leadframe pad, and is bonded to the grainiess and second grainiess.

20. encapsulation as claimed in claim 18 is characterized in that, two adjacent surfaces of described grainiess comprise an end face and a left side, and two adjacent surfaces of this second grainiess comprise a bottom surface and a left side.

21. encapsulation as claimed in claim 18 is characterized in that, two adjacent surfaces of described grainiess comprise a bottom surface and a left side, and two adjacent surfaces of described second grainiess comprise a bottom surface and a right side.

22. encapsulation as claimed in claim 18 is characterized in that, further comprises an electronic building brick or is arranged at the 3rd grainiess of 1 on the leadframe pad.

23. encapsulation as claimed in claim 1 is characterized in that, further comprises:

At least one other be arranged at grainiess on the leadframe pad;

Wherein, described metal bond zone comprises that one is distributed near " L " shape metal bond zone of two adjacent surfaces of packaging body, and its inner closing line is connected to this " L " shape metal bond zone and this grainiess reaches the top surface of these other grainiesses at least.

24. encapsulation as claimed in claim 1 is characterized in that, further comprises:

One second grainiess;

One second leadframe pad contains setting this second grainiess thereon, and wherein this second grainiess is arranged under this grainiess; And

One second metal bond zone;

Wherein, described metal bond zone comprises near a shape metal bond zone, top " J " and " I " shape metal bond zone around the top end center of the bottom end of this grainiess and this second grainiess that is distributed in the top end of this grainiess; And the wherein said second metal bond zone comprises that one is distributed near the shape metal bond zone, bottom " C " of bottom end of this second grainiess.

25. encapsulation as claimed in claim 24 is characterized in that, further comprises:

One electronic building brick or be arranged on the leadframe pad and be bonded to a grainiess of grainiess.

26. encapsulation as claimed in claim 24 is characterized in that, further comprises:

One second electronic building brick or be arranged on this second leadframe pad and be bonded to a grainiess of this second grainiess.

27. a semiconductor integrated circuit package is characterized in that, comprises:

One grainiess comprises an integrated circuit; And

One lead frame, this lead frame includes a leadframe pad that is arranged under this grainiess, with one source pole melts combine zone, this source metal calmodulin binding domain CaM contains a parallel zone along a part of distribution of lengths of the highest of this grainiess, with a parallel zone that distributes along the physical length on the left side of this grainiess, and closing line is arranged all on each parallel zone.

28. encapsulation as claimed in claim 27 is characterized in that, further comprises:

There is closing line to interconnect between the parallel zone of described source metal engaging zones and the described grainiess.

29. encapsulation as claimed in claim 27 is characterized in that:

Described grainiess is a mos field effect transistor device;

Described lead frame more comprises:

One grid structure, this grid structure comprise a gate metal engaging zones and a closing line, and this closing line connects the gate pad on the described grainiess.

30. encapsulation as claimed in claim 27 is characterized in that, further comprises:

One second grainiess;

One second lead frame, this second lead frame includes second leadframe pad that is arranged under this second grainiess, with one second source metal calmodulin binding domain CaM, this second source metal calmodulin binding domain CaM contains a parallel zone along a part of distribution of lengths of the highest of this second grainiess, with a parallel zone along a part of distribution of lengths on the left side of this second grainiess, and closing line is arranged all on each parallel zone.

31. encapsulation as claimed in claim 30 is characterized in that, described each lead frame all comprises a gate metal engaging zones and one source pole metal bond zone.

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