CN1818893A

CN1818893A - LPC bus interface sequential conversion and converter of peripheral apparatus

Info

Publication number: CN1818893A
Application number: CN 200610064836
Authority: CN
Inventors: 陈军
Original assignee: Hangzhou Huawei 3Com Technology Co Ltd
Current assignee: New H3C Technologies Co Ltd
Priority date: 2006-03-14
Filing date: 2006-03-14
Publication date: 2006-08-16
Anticipated expiration: 2026-03-14
Also published as: CN100373361C

Abstract

The invention discloses a timing conversion method for an LPC bus interface of a peripheral device, comprising: keeping the LPC bus in a long waiting state when the peripheral device performs an access operation; after the peripheral device completes the access operation, ending the long waiting state and driving the LPC bus Proceed to the operation of the next clock domain. The invention makes each waiting time just match the access time of the peripheral equipment, improves the access efficiency to the peripheral equipment, and can prevent the bus from being occupied for a long time when the access operation of the peripheral equipment is wrong. The invention can be realized in the glue logic in the CPLD, the logic design is flexible and simple, and the additional cost is low.

Description

The lpc bus interface sequence conversion method and the conversion equipment of peripherals

Technical field

The present invention relates to the interface switching device that peripherals inserts LPC (Low Pin Count, low pin number) bus, relate in particular to the lpc bus interface sequence conversion method of peripherals and the interface switching device of application thereof.

Background technology

LPC is a kind of bus of Intel (Intel) company definition, and it is the new interface that replaces ISA (IndustryStandard Architecture, industrial standard architectures), X-bus (X bus), gains the name because of number of pins is few.Lpc bus is a multiplex bus, is operated in 33MHz (megahertz), with PCI (Peripheral Component Interconnect, peripheral parts interconnected) bus synchronous.

Yet, still have a lot of peripherals that the bus interface of other types only is provided at present, as isa bus, LocalBus (local bus) bus etc.Because frequency of operation, data address bus figure place and the read-write sequence etc. of these buses are different with lpc bus, thereby peripherals need carry out could inserting the lpc bus operate as normal after the bus interface conversion.

In the bus interface conversion, one of of paramount importance task is the conversion of reading sequential and writing sequential.Need wait for that at read operation and write operation that certain peripherals carries out this peripherals returns execution result after finishing read-write.At LPC in the defined read-write cycle, the equipment of control lpc bus keeps waiting for that by making lpc bus (SYNC) state waits for that peripherals finishes read-write.

The waiting status of LPC comprises short waiting status (Short Wait) and long waiting status (Long Wait).In the prior art, the bus interface conversion equipment connects the time set scheduled duration that peripherals is finished read operation or write operation according to it, in this scheduled duration lpc bus is remained short the wait, returns execution result after scheduled duration finishes.The enough peripherals of this scheduled duration is finished corresponding read or write.Adopting the Flash of LocalBus bus interface with certain is example, 8 bit data address widths, require the read-write operation time greater than 90ns, when lpc bus being made as short the wait, a counter is set, each clock period counter increases 1, regains lpc bus and finishes read-write operation one time after waiting for 4 clock period at least.

The implementation method of this wait sequential is applicable to the peripherals that the visit duration is determined substantially.And some are had the peripherals of variable access duration, the required time of its read operation and/or write operation may have variation in a big way because of the difference of conditions such as access mode, reference address, adopt this method can only scheduled duration be set according to the possible maximum access time, make this peripherals and overall system efficiency reduce greatly.

Summary of the invention

The present invention will solve is to cause the low excessively problem of access efficiency when bus interface sequential conversion is applied to have the peripherals of variable access duration in the prior art.

The lpc bus interface sequence conversion method of peripherals of the present invention may further comprise the steps:

When peripherals is carried out accessing operation, lpc bus is remained long waiting status;

After peripherals is finished accessing operation, finish long waiting status, drive lpc bus and carry out the operation of next clock zone.

Preferably, described method also comprises: when the duration of long waiting status surpasses predetermined threshold, finish long waiting status and send error message to lpc bus simultaneously.

Preferably, the duration of described long waiting status obtained by the clock period of adding up long waiting status process.

Preferably, described peripherals is finished accessing operation and is specially: the indication that peripherals output expression visit is finished.

Preferably, described method also comprises before peripherals is carried out visit: obtain the lpc bus control.

The invention provides and a kind of peripherals is inserted the interface switching device of lpc bus, comprise LPC interface, Peripheral Interface and accessing time sequence control module, wherein:

The LPC interface is used for being connected lpc bus and peripherals respectively with Peripheral Interface;

The accessing time sequence control module is used for carrying out according to the accessing time sequence of lpc bus the accessing operation of peripherals, be included in by behind the Peripheral Interface output access operational order by the long waiting status of LPC interface output, and finish the indication back and finish long waiting status receiving accessing operation from Peripheral Interface.

Preferably, described lpc bus comprises the LPC clock signal;

The accessing time sequence control module also finishes long waiting status by LPC interface output access error message according to the duration of the long waiting status of LPC clock signal statistics when the duration surpasses predetermined threshold.

Preferably, described interface switching device is complex programmable logic equipment CPLD or on-site programmable gate array FPGA.

The invention provides a kind of input and output I/O system that adopts lpc bus, comprise processing unit and peripherals, and interface switching device, by lpc bus connection processing unit and connection peripherals, be used for the LPC that processing unit is initiated is converted to access cycle the access cycle of peripherals, wherein the wait SYNC clock zone of LPC in access cycle realized by long waiting status, finishes the SYNC clock zone when receiving the peripheral access operating result.

Preferably, described interface switching device is by being connected with peripherals with the different bus of LPC.

The present invention realizes SYNC clock zone in the LPC sequential to grow waiting status, finish end with the peripherals accessing operation as the SYNC clock zone, thereby make each wait duration just in time meet the visit duration of peripherals, improved access efficiency to peripherals;

Simultaneously, the present invention carries out timing to the access time of peripherals, returns error message after overtime, avoids taking for a long time bus.

Description of drawings

Fig. 1 is the read operation sequential chart of lpc bus firmware internal storage access cycle (Firmware Memory Cycle);

Fig. 2 is the write operation sequential chart in lpc bus firmware internal storage access cycle;

Fig. 3 is the process flow diagram of lpc bus interface sequence conversion method of the present invention;

Fig. 4 is the structural representation of I/O of the present invention system;

Fig. 5 is the structural drawing of interface switching device of the present invention;

Fig. 6 uses the read operation sequential chart of MAC chip in the example for the present invention;

Fig. 7 uses the write operation sequential chart of MAC chip in the example for the present invention;

Fig. 8 uses the bus connection diagram of interface switching device in the example for the present invention;

Fig. 9 uses the state machine conversion synoptic diagram of example for the present invention.

Embodiment

Lpc bus has defined the access cycle of some types, and (FirmwareMemory Cycle) is example with the firmware internal storage access cycle, its read operation sequential as shown in Figure 1, wherein LCLK is the LPC clock signal; LAD[3:0] be 4 bidirectional buses of LPC, be used for transmitting control, address and data-signal; With the LFRAME_N signal continue 1 clock period during low level at LAD[3:0] go up and drive the beginning that 0000b represents a LPC access cycle.The firmware internal storage access cycle is initiated by the LPC main equipment, the slave unit response.

Main equipment was possessed the control of lpc bus when the read operation in firmware internal storage access cycle began, main equipment begins access cycle with the low level of 1 clock period, send the chip selection signal of 1 clock period at the IDSEL clock zone, with 7 clock period maximum 28 reference address is sent to slave unit at the ADDR clock zone again, MSIZE afterwards is optional clock zone, is used for representing the byte number of each visit.After above-mentioned information is sent to slave unit, by the main equipment driving lpc bus control is handed to slave unit, this control transfering clock territory TAR is 2 clock period.After slave unit is obtained bus control right, during read operation lpc bus is remained waiting status, be the SYNC clock zone this moment, may continue a plurality of clock period; After read operation was finished, slave unit was sent to the data that main equipment reads on the lpc bus at the DATA clock zone, took 2M clock period when reading M byte; Slave unit is given back main equipment at second TAR clock zone with bus control right afterwards, finishes the read operation sequential.

Figure 2 shows that the write operation sequential chart in firmware internal storage access cycle, be main equipment before first TAR clock zone is given to slave unit with bus control right with the difference of read operation sequential among Fig. 1, give slave unit in the data transmission that the DATA clock zone will write; And slave unit does not need during occupying bus control right to the main equipment return data, after the SYNC clock zone is finished write operation, can return bus control right.

Other access cycles of lpc bus and firmware internal storage access periodic group are seemingly, all be after main equipment address information that accessing operation is required and data message are sent to slave unit, the conversion bus control right, slave unit is finished accessing operation at the SYNC clock zone, finishes the back to main equipment return result and return bus control right at the SYNC clock zone.

In the SYNC clock zone, slave unit is grasped bus control right.Slave unit can be by at LAD[3:0] go up and drive different signals and keep two kinds of waiting statuss, in this time period, finish accessing operation.When slave unit drives 0101b, be short waiting status, promptly scheduled visit operation duration be set in the prior art by this state; Be long waiting status when slave unit drives 0110b, long waiting status can continue to surpass 1 millisecond time, drives 0000b or 1010b end up to slave unit; Wherein 0000b represents that accessing operation normally finishes, and 1010b represents that accessing operation makes a mistake.

To having the peripherals of variable access duration, can both be used as the indication that accessing operation is finished on certain signal line, to drive certain signal usually, with the notice access means.In the present invention, long waiting status is set, when indication is finished in peripherals output access operation, finish long waiting status, thereby the difference that realizes each accessing operation is very neatly waited for duration at the SYNC clock zone.

Figure 3 shows that the bus interface sequential conversion process flow diagram of peripherals among the present invention.At step S310, obtain the control of lpc bus.As previously mentioned, the 1st the TAR clock zone of LPC access cycle carry out bus control right by main equipment to the delivering of slave unit, when arriving the SYNC clock zone, slave unit one side has obtained bus control right.

At step S320, peripherals begins to carry out accessing operation.According to the information that receives from lpc bus before, peripherals begins to carry out specified accessing operation this LPC access cycle.

At step S330, when peripherals begins to carry out accessing operation, start timing to its accessing operation.Owing to have clock signal on the lpc bus, thus can by to accessing operation clock period of process count the duration that obtains accessing operation easily.

At step S340, keep lpc bus to be long waiting status.The SYNC clock zone, driving 0110b on lpc bus, can to keep lpc bus be long waiting status.

At step S350, judge the peripherals indication whether the output access operation is finished, if change step S380; If not, change step S360.

At step S360, judge that whether the duration of accessing operation surpasses predetermined threshold, if then think this accessing operation failure, execution in step S370; If not, change step S340.

At step S370, on lpc bus, drive 1010b, finish long waiting status and send the information of accessing operation mistake to main equipment, change step S390.At this moment, the SYNC clock zone finishes with the end of long waiting status.

At step S380, receive the indication that peripheral access operation finishes after, on lpc bus, drive 0000b, notice main equipment accessing operation is normally finished, and finishes long waiting status simultaneously, the SYNC clock zone also finishes.

At step S390, drive lpc bus and carry out the operation of next clock zone.

Step S330, S360, S370 are used for realizing the timeout mechanism of peripheral access, take lpc bus when avoiding the peripherals operation irregularity for a long time.In some applications, timeout mechanism also can be in peripherals inside or main equipment one side realize that this moment, step S330, S360 and S370 can omit.

The above-mentioned sequential conversion of the present invention can be applied to adopt I/O (input and output) system of lpc bus, and its structure as shown in Figure 4.Processing unit 410 is connected by lpc bus 420 with interface switching device 430, and interface switching device 430 is connected by peripheral bus 440 with peripherals 450.Peripheral bus 440 is non-lpc bus.Interface switching device 430 also can directly be connected with peripherals 450.

Processing unit 410 is as the main equipment of lpc bus 420, the LPC access cycle of initiating peripherals 450 by lpc bus 420.Interface switching device 430 is converted to the sequential of the access cycle of peripherals 450 with the sequential of LPC access cycle, drives peripherals 450 by peripheral bus 440 and finishes accessing operation.To the LPC SYNC clock zone that confession peripherals 450 conducts interviews and operates in access cycle, interface switching device 430 keeps lpc bus 420 to be long waiting status, and finishes long waiting status and SYNC clock zone after receiving the accessing operation result of peripherals 450.

Figure 5 shows that the inner structure of interface switching device 430, interface switching device 430 comprises LPC interface 431, accessing time sequence control module 432 and Peripheral Interface 433, accessing time sequence control module 432 is connected with Peripheral Interface 433 with LPC interface 431 respectively, LPC interface 431 connects lpc bus 420, and Peripheral Interface 433 connects peripherals.

Accessing time sequence control module 432 is carried out the accessing operation of peripherals 450 according to the accessing time sequence of lpc bus 420.At the LPC SYNC clock zone of access cycle, accessing time sequence control module 432 is from Peripheral Interface 433 output access operational orders, start the accessing operation of peripherals 450, on lpc bus 420, drive 0110b by LPC interface 431 afterwards, keep lpc bus 420 to be long waiting status; After peripherals 450 was finished accessing operation, accessing time sequence control module 432 received accessing operation from Peripheral Interface 433 and finishes indication, finished the long waiting status of lpc bus 420 afterwards.

Accessing time sequence control module 433 can utilize LPC clock signal in the lpc bus 420 to long waiting status timing, finish indication if receive the access operation at Peripheral Interface 433 not yet when the duration of long waiting status surpasses predetermined threshold, then pass through LPC interface 431 output access error message on lpc bus 420, and finish long waiting status simultaneously.

Interface switching device can adopt CPLD (Complex Programmable Logic Device, complex programmable logic equipment), FPGA realizations such as (Field Programmable Gate Array, field programmable gate arrays).

Below be example with the CPU (Central ProcessUnit, central processing unit) of the employing lpc bus that generally uses in the network equipment to the visit of MAC (Media Access Control, medium access control system) chip, concrete application of the present invention is described.

The cpu i/f of MAC chip is the LocalBus bus interface normally, establishes the MAC chip A2511 that the MAC chip is selected the Harrier of Ample producer series for use, and its synchronous cpu i/f is supported 16 access modules.In the A2511 write operation sequential of the A2511 of Fig. 6 read operation sequential and Fig. 7, CPU_ADDR is used for importing the address information of CPU accessing operation; The CPU_TS_N low level is effective, and expression is the beginning of visit once; CPU_CS_N is a chip selection signal, and low level is effective; The CPU_RDY_N low level is effective, represents current bus CPU end of transmission (EOT); CPU_DATA is used for transmitting data between MAC chip and CPU.

With reference to A2511 read operation sequential shown in Figure 6, for the CPU read operation, CPU_Rdy_N signal low level represents that effectively the MAC chip delivers to data on the data bus, can be read by CPU safety; With reference to A2511 write operation sequential shown in Figure 7, for the CPU write operation, the CPU_Rdy_N signal represents that effectively the MAC chip has received the data that CPU sends, and writes in the corresponding M AC chip internal register.

Register in the MAC chip all is 32, adopts 16 access modules, and each register need be initiated twice CPU and just can be finished access cycle.Usually when write operation, in preceding 4 cpu clock cycles of 16 needs, then 16 write operation probably needs 14 clock period; For read operation, the needed CPU access time is just in time opposite, and preceding 16 visits need 14 cycles, and then 16 only need 4 clock period just can finish.The duration of accessing operation is except outside the Pass having with cpu clock frequency, also relevant with the register type of visit, for example visit MDIO (Management Data Input Output, the management data input and output) register, access time will be very long, the longest situation is to finish the read-write needs 2 μ s (microsecond) of a MDIO register under 10Mbps (megabit per second) pattern when the MAC chip operation, if cpu clock frequency is 33MHz, then nearly 67 clock period just can be finished once read-write.

In addition for MAC chip A2511, the time upper limit that CPU waits for is 256 clock period, if visited an illegal register address, the CPU_RDY_N signal still is a disarmed state after 256 clock period, the internal counter of MAC chip can overflow, so need make corresponding error handling processing.

Should be with FWH (the Firmware Hub by LPC in the example, FWH) realizes visit access cycle to the MAC chip, FWH access cycle, the data length for each visit was the firmware access cycle of 2 bytes, its read operation sequential, write operation sequential are distinguished as depicted in figs. 1 and 2, and wherein the value of M is 2.The interface switching device that the cycle that conducts interviews changes adopts CPLD to realize, its bus connecting mode is referring to Fig. 8, wherein the LPC interface connects lpc bus, and the MAC interface connects MAC chip A2511, and the accessing time sequence control module in the interface switching device is realized by State Machine (state machine).

Fig. 9 is the state machine conversion synoptic diagram of interface switching device, and its state is corresponding to the read-write operation clock zone of LPC, and wherein TAR and TAR1 correspond respectively to the first time and the TAR clock zone second time; WRITE and WRITE1 correspond respectively to the write operation of first byte and second byte in the DATA clock zone of write operation; READ and READ1 correspond respectively to the read operation of first byte and second byte in the DATA clock zone of read operation.

Main equipment is initiated the read-write cycle on lpc bus, CPLD is with the data decode of four bus transfer of LPC, produce read-write control signal, wherein address and data are deposited in the temporary register, be combined into 32 or 28 bit addressing addresses and 8 or 16 bit data, and, then address, data and control signal are driven on the Local Bus bus from temporary register according to the choosing of reference address generation relevant device sheet.

Main equipment is initiated the FWH cycle access, represents the visit beginning when rising edge clock detects LFRAME_N for low level.Send START frame in effective last clock period of LFRAME_N, send 1101b and represent read operation, 1110b represents write operation.State machine forwards the IDSEL state to, judges read operation or write operation.The address that the ADDR state needs 7 clock period to finish 28 bit mac interfaces sends, and begins transmission from the highest effective half-word joint earlier.Because the address bus of MAC chip A2511 has only 24, so not enough high 4 zero paddings.

To write operation, state machine forwards WRITE, WRITE1 to, and each WRITE state is finished the write operation of 2 nibbles, and totally 16 bit data are transmitted low four earlier.Data have been delivered in the inner temporary register of CPLD behind two WRTIE states, and are driven on the data bus of MAC interface; At this moment, the sheet of MAC interface selects CPU_CS_N and read-write CPU_READ and not yet in effect, so data are not also write in the internal register of MAC chip.Forward the TAR state this moment to, and main equipment is at four bus LAD[3:0 of LPC] go up driving 1111b, next cycle TAR1 give CPLD with bus control right, produces sheet and select the low level of CPU_CS_N and CPU_READ with imitating signal.Sequence state machine arrives SYNC, and CPLD judges the CPU_RDY_N signal of MAC interface, and constantly sends long outstanding message 0110b to main equipment, data is write internal register and drive CPU_RDY_N effective up to the MAC chip.This moment, CPLD finished long waiting status, and it is invalid that the sheet choosing of MAC interface and write signal are changed to.CPLD enabling counting simultaneously device when lpc bus is in sync state, each clock period accumulation once, if counter to 256 does not also detect effective CPU_RDY_N signal, then send the error message of 1010b to lpc bus, finish FWH access cycle simultaneously.

To read operation, behind the ADDR state, change TAR over to.Same main equipment is at LPC_LAD[3:0] go up driving 1111b, next cycle TAR1 bus control right is given slave unit CPLD, and CPLD produces sheet and selects the high level of CPU_CS_N and CPU_READ to read useful signal.Detect the CPU_RDY_N signal of MAC interface at sync state CPLD, constantly send long outstanding message 0110b to main equipment, effective up to CPU_RDY_N, data have been delivered on 16 bit data bus of MAC interface and have been deposited in the temporary register of CPLD.At the READ state, CPLD will divide two clock period to deliver to lpc bus from temporary register from the low eight bit data that the MAC interface is read, READ1 state, transmission high eight-bit data.The same enabling counting device of read operation is counted 256 clock period, prevents that main equipment is in waiting status for a long time always, does not meet with a response and hangs dead.

The cpu i/f accessing time sequence that the lpc bus sequential is converted to the MAC chip can be realized by glue logic (glue logic), need take about 300 of macroelement, about about 60 of I/O mouth can be selected Xilinx XCR3512XL-10 for use, Lattic LC4512V-75F256C or other model C PLD.

Have the peripherals that the visit of Ready signal indication finishes for needs, the present invention has realized the solution that LPC interface bus sequential is changed by long waiting status, can effectively improve access efficiency for the unfixed peripherals of visit duration.Because generally more complicated veneer all can add a slice programming device CPLD when design, the present invention can add the sequential conversion in the glue logic therein again, and logical design is simple flexibly, and fringe cost is low.

Above-described embodiment of the present invention does not constitute the qualification to protection domain of the present invention.Any any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection domain of the present invention.

Claims

1. a low pin count LPC bus interface timing conversion method of peripheral equipment, is characterized in that, comprises the following steps:

Keep the LPC bus in a long wait state while the peripheral device performs an access operation;

After the peripheral device completes the access operation, the long waiting state is ended, and the LPC bus is driven to perform the operation of the next clock domain.

2. the LPC bus interface timing conversion method of peripheral equipment as claimed in claim 1, is characterized in that, described method also comprises: when the duration of long waiting state exceeds predetermined threshold value, end long waiting state and send error simultaneously to LPC bus information.

3. The LPC bus interface timing conversion method of peripheral equipment as claimed in claim 2, characterized in that: the duration of the long waiting state is obtained by counting the clock cycles passed by the long waiting state.

4. The method for converting the LPC bus interface timing of the peripheral device according to any one of claims 1 to 3, wherein the completion of the access operation by the peripheral device is specifically: the peripheral device outputs an indication indicating that the access is completed.

5. The method for timing conversion of the LPC bus interface of the peripheral device according to any one of claims 1 to 3, characterized in that, before the peripheral device executes the access, the method further comprises: obtaining the control right of the LPC bus.

6. A kind of interface conversion device that peripheral equipment is inserted into LPC bus, it is characterized in that, comprises LPC interface, peripheral hardware interface and access timing control module, wherein:

The LPC interface and the peripheral interface are used to connect the LPC bus and peripheral equipment respectively;

The access timing control module is used to perform peripheral device access operations according to the access timing of the LPC bus, including outputting a long wait state through the LPC interface after outputting an access operation instruction through the peripheral interface, and receiving an access operation completion instruction from the peripheral interface After the end of the long wait state.

7. the interface conversion device that peripheral equipment is inserted into LPC bus as claimed in claim 6, is characterized in that: described LPC bus comprises LPC clock signal;

The access timing control module counts the duration of the long waiting state according to the LPC clock signal, and outputs access error information through the LPC interface when the duration exceeds a predetermined threshold and ends the long waiting state.

8. The interface conversion device for connecting peripheral equipment to the LPC bus as claimed in claim 6 or 7, wherein the interface conversion device is a complex programmable logic device (CPLD) or a field programmable gate array (FPGA).

9. A kind of input and output I/O system that adopts LPC bus, comprises processing unit and peripheral equipment, is characterized in that: also comprises interface conversion device, connects processing unit and peripheral equipment by LPC bus, is used for processing unit initiated The LPC access cycle is converted into the access cycle of the peripheral device, wherein the waiting SYNC clock domain in the LPC access cycle is implemented by a long wait state, and the SYNC clock domain is ended when the peripheral device access operation result is received.

10. The I/O system using the LPC bus as claimed in claim 9, wherein the interface conversion device is connected to the peripheral equipment through a bus different from the LPC.