CN1811979A - Improved sensing amplifier - Google Patents

Abstract

The present invention provides an improved sensing amplifier to generate a sensing delay. The sensing amplifier includes a reference data line to couple to a small array of analog cell currents. The sensing amplifier separates a precharge path and a sensing path, and connects the precharge path and the sensing path respectively with a common gate MOS (Metal Oxide Semiconductor) pair, and the sensing delay time is adjusted by changing the size ratio of the MOS pair.

Description

An Improved Sense Amplifier

The present invention is a divisional application with the application number 02140251.5, the application date is July 2, 2002, and the invention name is a control clock generator and a control clock generation method for high-speed sense amplifiers

technical field

The present invention relates to sense amplifiers, and more particularly to an improved high-speed sense amplifier.

Background technique

Typically, sense amplifiers are used to read the state ("0" or "1") of a memory cell in a memory array, such as a read-only memory. A ROM array may contain millions of memory cells arranged in columns and rows. The source of each memory cell in a row can be connected to a row source line, and the sense amplifier reads During the selection of memory cells, the row source lines of the selected memory cells may be connected to a reference potential or to ground. The drain of each memory cell in a row is connected to a separate bit line, also known as the row drain line, and during the read of the selected memory cell by the sense amplifier, the row of selected memory cells The drain line is connected to the input of the sense amplifier. The control gate of each memory cell in a column is connected to a word line, and during reading of the selected memory cell, the word line of the selected memory cell is connected to a predetermined voltage.

During a read operation, the current flowing through the selected memory cell is compared with a reference current to determine whether the selected memory cell is programmed "0" or "1". The reference circuit is connected to the input of a current sense amplifier whose output is connected to one side of the difference amplifier. When the selected memory cell is read, the differential amplifier compares the output voltage of the current sense amplifier with the output voltage of another current sense amplifier connected to the selected memory cell. If the reference circuit includes a memory cell which is essentially the same as the memory cell being read, to achieve a reference current between the current of the selected memory cell programmed to "0" and the current of the selected memory cell programmed to "1" Between cell currents, it is usually necessary to break the balance of the current sense amplifier.

In the sense amplifier, the precise control of the timing of the control clock is one of the conditions to achieve high-speed operation. However, due to different process dead angles, temperatures and voltages, the control clock lacks good tracking ability, resulting in sense amplifiers. It is difficult to increase the speed of the test amplifier. Referring to the US Patent No. 5771196 issued to Yang Nianzhao as an example, its control circuit includes three parts, namely, an address transfer pulse (AddressTransition Pulse; ATP) generator, a precharge (precharge) signal PCB generator, and a latch (latch) signal LATB generator, the address transfer pulse signal ATP is used as the trigger source of the control clock such as the precharge signal PCB, the latch signal LATB and the sense amplifier enable signal SAB, and the precharge signal PCB should be word line delay and bit The slower of the line pull-up delays. For flat ROMs, the word line delay is much greater than the bit line pull-up delay. Therefore, the word line delay is usually used to control the pre-charge signal PCB, and the width of the latch signal LATB should be greater than the pre-charge signal PCB. The width of , the time difference between the precharge signal PCB and the latch signal LATB must be chosen to be sufficient to latch the correct data, and it is related to the sensing time, which is directly proportional to the cell current. The latch signal LATB is generated from the pre-charge signal PCB plus a delay time, the delay time is controlled by the cell current from the mini-array, and the pre-charge signal PCB is after the latch signal LATB Go high after a few nanoseconds to ensure correct data is latched. In conventional techniques, the control signals are generated with reference to the cell currents of the small array using RC (ie, word line) delays and logic gate delays. It is difficult to improve the speed due to the poor tracking ability of the control clock under different process dead angles, temperatures and voltages.

Contents of the invention

The object of the present invention is to propose a control clock generator and control clock generation method for high-speed sense amplifiers, the generation of the control clock combines RC delay, gate delay and reference sense from the reference sense amplifier Delay, so to obtain good tracking effect, not afraid of process dead angle, temperature and voltage changes.

According to the present invention, a clock generator uses an address transfer pulse signal as a trigger source, and the clock generator includes:

The first RC delay device, the address transfer pulse signal and the signal generated by the address transfer pulse signal are simultaneously input to a gate circuit through the first RC delay device to generate a precharge signal;

The second RC delay device, the signal generated after the address transfer pulse signal and the address transfer pulse signal pass through the second RC delay device is simultaneously input to the signal generated by the gate circuit, input to the first gate delay device, and then input to a reference sensing delay means to generate a latch signal; and

The second gate delay device, the latch signal passes through the second gate delay device to generate a sense amplifier enabling signal.

In a preferred embodiment, the circuit for generating the latch signal includes three paths, wherein the main path is to pass the address transfer pulse signal through RC delay, gate delay and reference sensing delay, and the other two paths are for the main A guard time interval (guardtime) is added before and after the delay generated by the path to ensure that the generated latch signal falls within a safe range. The second path is to pass the precharge signal through RC delay and gate delay, so that the The delay of the latch signal to the precharge signal does not exceed a maximum value, and the third path is to delay the address transfer pulse signal through an RC delay AND gate, so that the delay of the latch signal to the precharge signal is not lower than a minimum value .

The present invention further provides an improved sense amplifier circuit to generate a sense delay. The sense amplifier consists of:

a reference data line to connect to a small array of analog cell currents;

a sensing path, connected between the first power supply voltage and the reference data line, the sensing path is connected to the reference data line through one side of a transfer transistor, and the other side of the transfer transistor is connected to a sensing node , the sensing path further includes an input transistor connected to the sensing node, the input transistor has a gate connected to an input signal;

a pre-charge path connected between the second supply voltage and the reference data line, the pre-charge path connected to the reference data line through a transistor with the common gate of the pass transistor; and

A latch circuit, connected to the sensing node, generates an output signal in response to the input signal.

It also includes a bias voltage connecting the transfer transistor and the common gate transistor.

The sensing path also includes a diode between the first supply voltage and the input transistor.

The diode is selected from the group consisting of PMOS, NMOS and depletion NMOS.

The size ratio of the pass transistor and the common gate transistor determines a sensing delay time.

The sense amplifier includes a reference data line to couple to a small array of analog cell currents. The sense amplifier separates the pre-charging path and the sensing path, and connects the pre-charging path and the sensing path with a common-gate MOS (Metal Oxide Semiconductor) pair, and adjusts the sensing delay time by changing the size ratio of the MOS pair .

The present invention also provides a method for generating a control clock for a high-speed sense amplifier, which uses an address transfer pulse signal as a trigger source, and the method includes the following steps:

Inputting the signal generated after the first delay of the address transfer pulse signal and the address transfer pulse signal to the gate circuit at the same time to generate a precharge signal;

inputting the address transfer pulse signal and the signal of the address transfer pulse signal after the second RC delay to the gate circuit, performing a first gate delay and a reference sensing delay to generate a latch signal; and

Delaying the latch signal with a second gate to generate a sense amplifier enabling signal.

The above method further includes performing a third RC delay and a third gate delay on the precharge signal to generate a first guard time interval for the latch signal.

The above method further includes performing a third RC delay and a third gate delay on the address transfer pulse signal to generate a second guard time interval for the latch signal.

Therefore, the clock generator of the present invention has a very close to the actual sensing delay, thereby providing good tracking effect for high-speed sense amplifiers with process dead angle, temperature or voltage variation.

Description of drawings

FIG. 1 is a control circuit architecture for generating control signals PCB, LATB and SAB in a sense amplifier;

Fig. 2 is a preferred embodiment of the clock generator according to the present invention;

FIG. 3 is a preferred embodiment of a reference sense amplifier according to the present invention;

Figure 4 is a typical RC delay circuit;

Figure 5 is a typical gate delay circuit;

FIG. 6 is a timing diagram of control signals according to the present invention.

Detailed ways

FIG. 1 is a block diagram showing the generation structure of the control signal for the sense amplifier, wherein the address transfer pulse generator 10 generates the address transfer pulse signal ATP according to the chip enable signal PCEB, and then generates the pre-charge through the clock generator 20. There are three control signals including the signal PCB, the latch signal LATB, and the sense amplifier enabling signal SAB.

A preferred embodiment of the clock generator 20 is shown in FIG. 2 , which uses the address transfer pulse signal ATP as a trigger source to generate the required control clock. In the clock generator 20, in order to generate the precharge signal PCB, the two input ends of the NAND gate (NAND gate) 21a are respectively connected to the address transfer pulse signal ATP and the signal through the RC delay 22a, and the output of the NAND gate 21a After passing through an inverter (inverter) 23a, the pre-charging signal PCB is generated. The circuit for generating the latch signal LATB is relatively complex, including three paths Path1, Path2 and Path3, the main delay time is determined by the path Path2, which passes the address transfer pulse signal ATP and its signal after RC delay 22b through the NAND gate 21b After the inverter 23b, the output is passed through the gate delay 26 and the reference sensing delay 27. In addition, the path Path1 passes the output signal of the aforementioned inverter 23a through the RC delay 24 and the gate delay 25, and the path Path3 passes the address transfer pulse signal ATP and its signal after the RC delay 22c pass through the NAND gate 21c and the inverter 23c, then pass through the gate delay 28, and then combine the delays generated by the three paths Path1, Path2 and Path3. In detail, the aforementioned reference sensing delay After the output of 27 passes through the inverter 29, the output of the AND gate delay 28 passes through the NOR gate 30 and the inverter 31 together, and then passes through the NAND gate 32 and the inverter 33 together with the output of the aforementioned gate delay 25 to generate Latch signal LATB. In the foregoing operations, the timing of the latch signal LATB is controlled by Path2, and the other two paths Path1 and Path3 add a guard interval to the latch signal LATB to ensure that the latch signal LATB falls within a safe range. In other words, the minimum delay of the latch signal LATB is controlled by Path3, and the maximum delay is controlled by Path1. The output of the aforementioned inverter 33 is passed through the gate delay 34 to generate the sense amplifier enabling signal SAB.

In order to obtain a good tracking effect, the above-mentioned reference sensing delay 27 should be as close as possible to the sensing delay of the actual circuit. FIG. 3 provides an improved sense amplifier 40 to achieve this purpose. In the sense amplifier 40, the pre-charging path and the sensing path are separated, the sensing path is established from the power supply VDD through MOS47, 41 and 42 to the reference data line DLref, and the pre-charging path is established from the power supply VDD through the MOS48 and 42R to the reference data line DLref established. The reference data line DLref is connected to a small array of analog cell currents. The NMOS 42 serves as a pass transistor, and has a common gate with the MOS 42R, and is biased by the output Vx of the NOR gate 43 . The precharge signal PCB is applied to the gate of the PMOS 41 as the input IN of the sense amplifier 40 . The voltage signal of the sensing node Vz passes through the inverter circuit composed of MOS44a, 44b, 45a and 45b, and the latch circuit composed of inverters 46a and 46b to generate the output signal OUT. In the sensing path, the PMOS47 is connected as a diode, which can reduce the voltage disturbance (swing) of the sensing node Vz and shorten the sensing time without interfering with the pre-charging mechanism of the reference data line DLref, and by increasing The size of NMOS 42 improves the sensing speed. The PMOS (Positive MOS) 47 as a diode can also be replaced by NMOS (Negative MOS) or depletion mode NMOS (Depletion mode NMOS). On the other hand, the pre-charging current can also be adjusted by changing the size of the NMOS 48 and 42R. Therefore, the pre-charging of the reference data line DLref can also be well controlled without hindering the sensing speed. The reference sensing delay time of the sense amplifier 40 can be adjusted by changing the size ratio of the NMOS 42 and 42R.

The RC delay in FIG. 2 can be achieved by using any commercially available or known RC delay circuit, and the circuit shown in FIG. 4 is an example. A series of inverters 51 and 52, resistors 53, and inverters 56 and 57 are included between the input IN and the output OUT of the RC delay 50, and a MOS54 is connected between the input terminal of the inverter 56 and the reference potential or ground terminal, The gate of the latter is connected to the input terminal of the inverter 52 , and at the same time, the input terminal of the inverter 56 is connected to a capacitor 55 connected by NMOS.

The gate delay shown in FIG. 2 can also be realized by using any commercial or known gate delay circuit. The circuit shown in FIG. 5 is an example. A series of inverters 61 , 62 , 64 and 66 are included between the input IN and the output OUT of the gate delay 60 . The input and output ends of the inverter 64 are respectively connected to a capacitor 63 and 65 connected by NMOS.

FIG. 6 is a timing diagram showing the relative relationship between several signals generated using the aforementioned circuit. First, the address transfer pulse signal ATP is generated in response to the chip enable signal PCEB and the address signal ADD. As mentioned above, other control signals are generated in response to the address transfer pulse signal ATP. During T1, the precharge signal PCB, the latch signal LATB, and the sense amplifier enable signal SAB are generated, and, due to the delay, the widths of the latch signal LATB and the sense amplifier enable signal SAB are shorter than The width of the precharge signal PCB is long. During this period, the voltage of the sensing node Vz will be pulled up to a diode conduction voltage level lower than the power supply voltage VDD (because the diode 47 is between the power supply voltage VDD and the PMOS41), therefore, it can be is considered a precharge period. Then, during T2, the precharge signal PCB goes high, at this time, the voltage of the sensing node Vz can be changed, and it will remain at a high level or drop to a predetermined level according to the read data. Therefore, during this period can be considered as the sensing period. During T3, the latch signal LATB goes high, then the data is latched by the latch circuit in the sense amplifier 40, and the sense amplifier enable signal SAB goes high later than the latch signal LATB to ensure that the correct data is latched . After the T3 period, the sense amplifier 40 can be turned off to reduce power consumption, and the output driver is turned on so that correct data appears on the data output bus, as shown by the data output signal DOUT in the figure.

The purpose of the narration done above for the embodiment is in order to clarify the present invention, and has no intention to limit the present invention, it is possible to modify or change based on the above description or learning from the embodiments of the present invention, therefore, the technical thought of the present invention The intent is to be determined by the scope of the claims in this case and their equivalence.

Claims (5)

1. An improved sense amplifier, characterized in that: the sense amplifier comprises: a reference data line to connect to a small array of analog cell currents; a sensing path, connected between the first power supply voltage and the reference data line, the sensing path is connected to the reference data line through one side of a transfer transistor, and the other side of the transfer transistor is connected to a sensing node , the sensing path further includes an input transistor connected to the sensing node, the input transistor has a gate connected to an input signal; a pre-charge path connected between the second supply voltage and the reference data line, the pre-charge path connected to the reference data line through a transistor with the common gate of the pass transistor; and A latch circuit, connected to the sensing node, generates an output signal in response to the input signal. 2. The sense amplifier of claim 1, further comprising a bias voltage connecting the pass transistor and the common gate transistor. 3. The sense amplifier of claim 1, wherein the sense path further comprises a diode between the first supply voltage and the input transistor. 4. The sense amplifier as claimed in claim 3, wherein the diode is selected from the group consisting of PMOS, NMOS and depleted NMOS. 5. The sense amplifier as claimed in claim 1, wherein a size ratio of the pass transistor and the common gate transistor determines a sensing delay time.

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