CN1809928A - Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses - Google Patents

Abstract

A semiconductor gate structure includes a shielding electrode and a switching electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

Description

Method and apparatus for improving MOS gating to reduce Miller capacitance and switching losses

Related patent application reference

This patent application claims the benefit of priority to US Provisional Patent Application Serial No. 60/405,369, filed August 23,2002.

technical field

This invention relates to semiconductors, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs).

Background technique

MOSFETs are widely used in the field of switching, for example, switching power supplies hardly use other types of transistors. MOSFETs are suitable for this switching application because they have a relatively high switching speed and require low power. However, dynamic losses in MOSFETs account for a large percentage of the total losses in a DC-DC converter. The dynamic loss is proportional to the rise and fall time of the device, and the rise and fall time of the device is proportional to the gate-drain capacitance of the device, that is, the Miller capacitance (C _GD or Q _GD ).

As shown in Figure 3, Miller capacitance also causes a "flat" region in the gate curve of a conventional MOSFET. This flat region, known as the Miller region, represents the transition of the device from a blocking state to a conducting state, or vice versa. It is in the Miller zone that most of the switching losses occur because of the high device current and voltage. Reducing the Miller capacitance reduces the time it takes for the device to turn on to block, or vice versa, thereby reducing switching losses.

Miller capacitance can be reduced by reducing the overlap area between the gate and drain regions. In prior art devices, the overlapping region includes the bottom of the gate trench. Therefore, many prior art attempts to reduce Miller capacitance have focused on shrinking the width of the trench thereby reducing the width of the bottom of the trench, thereby reducing the overlap area. However, the ability to further reduce the channel width is limited by the ability to etch the narrow channel, and there is a corresponding need to be able to fill the narrow channel with gate electrode material.

Therefore, there is a technical need to make MOSFETs with lower Miller capacitance, thereby reducing switching losses.

Also, there is a technical need for MOSFETs with lower Miller capacitance for a given channel width.

Contents of the invention

The present invention provides a gate structure for a semiconductor device.

One form of the invention includes a switch electrode and a shield electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

One advantage of the present invention is that, for a given channel width, the Miller capacitance of the semiconductor device is smaller than prior art devices.

A further advantage of the invention is that the switching times and switching losses of the device are reduced.

Description of drawings

The above and other features and advantages of the present invention, and the manner in which they are obtained, will become apparent and more readily understood by reference to the following description of an embodiment of the invention in connection with the accompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view of a channel metal oxide semiconductor gate control (MOS gate control) structure in the prior art;

2 is a schematic cross-sectional view of an embodiment of the MOS gate control structure of the present invention;

Fig. 3 is a graph of the gate switching waveforms of the traditional MOS gate control structure and the MOS gate control structure of Fig. 2;

Fig. 4 is a graph of a typical net doping profile of the well of the MOS gate control structure of Fig. 2;

Fig. 5 is a schematic cross-sectional view of an embodiment of a planar MOSFET of the present invention;

6 is a schematic cross-sectional view of a second embodiment of a planar MOSFET of the present invention;

Fig. 7 is a schematic cross-sectional view of an embodiment of the side MOSFET of the present invention;

8 is a schematic cross-sectional view of the second embodiment of the side MOSFET of the present invention;

9 is a schematic cross-sectional view of an embodiment of the channel MOS gate control structure of the present invention; and

FIG. 10 is a process diagram illustrating one embodiment of a process for fabricating the device shown in FIG. 2 .

In the drawings, corresponding parts are indicated by corresponding reference numerals. The example presented herein illustrates one form of a preferred embodiment of the invention and should not be considered as limiting the scope of the invention in any way.

Detailed ways

Referring now to the drawings and in particular to FIG. 1, there is shown a schematic cross-sectional view of a prior art trench-gated MOSFET device. MOSFET device 10 includes drain region 12 , well region 14 , body region 16 , source region 18 , gate region 20 and channel 24 , all of which are formed on substrate 26 .

More specifically, the N+ type substrate 26 includes an upper layer 26a in which the N- drain region 12 is formed. The P-type well region 14 is located above the drain region 12 . A heavily doped P+ body region 16 is defined within an upper surface (not indicated) of upper layer 26 a and a portion of well region 14 . A heavily doped N+ source region 18 is formed on the upper surface of upper layer 26 a and within a portion of well region 14 and adjacent to channel 24 . The sidewalls and bottom (not shown) of trench 24 are lined with a dielectric material 28, such as oxide. Gate region 20 is formed of conductive material 30, such as doped polysilicon, which is deposited in trench 24 and extends continuously from the bottom of trench 24 to near the upper surface of upper layer 26a. Thus, the gate 20 is continuous with respect to the channel region 32 or passes through the channel region 32 . An interlevel dielectric layer 34 , such as borophosphosilicate glass (BPSG), overlies gate region 20 and a portion of source region 18 . Source metal layer 36 overlies the upper surface of upper layer 26 a and contacts body region 16 and source region 18 .

Referring now to FIG. 2, there is shown a schematic cross-sectional view of one embodiment of the trench-gated MOSFET device of the present invention. Many features and structures of MOSFET 100 are substantially similar, if not identical, to MOSFET 10. Similar to MOSFET 10, MOSFET 100 includes drain 112, well 114, body 116, source 118, gate structure 120, and channel 124, all of which are formed on substrate 126. However, unlike the gate structure 20 of the MOSFET 10, the gate structure 120 of the MOSFET 100 includes a dual overlapping gate structure, which reduces Miller capacitance and improves switching speed, as will be explained in particular below.

MOSFET 100 is formed on N+ type substrate 126 which includes upper layer 26a in which N− drain region 112 is formed. The P-type well region 114 is located above the drain region 12 . A heavily doped P+ body region 116 is defined within an upper surface (not indicated) of upper layer 126 a and a portion of well region 114 . A heavily doped N+ source region 118 is also formed on the upper surface of the upper layer 126 a and within a portion of the well region 114 and near the channel 124 . The lower portion of the sidewalls near shield electrode 120b and the bottom (not indicated) of trench 24 are lined with a dielectric material 128, such as an oxide.

The gate structure 120 of MOSFET 100 is not a single and monolithic electrode that is continuous without discontinuity as in MOSFET 10, but is divided into isolated switch and shield electrodes that overlap each other. More specifically, the gate structure 120 includes a gate electrode 120a and a gate electrode 120b. An intervening dielectric layer 134 overlies the gate electrode 120 a and partially overlies the source region 118 . Each of electrodes 120 a and 120 b is formed of a conductive material, such as doped polysilicon, which is deposited in channel 124 . The first or upper electrode 120a formed of a conductive metal layer is approximately level with the upper surface of the upper layer 126a, or is recessed below the upper surface. First/upper electrode 120 a extends a predetermined distance from near the upper surface of upper layer 126 a horizontally coplanar with source region 118 to the bottom of channel 124 such that a lower portion of first/upper electrode 120 a is horizontally coplanar with well region 114 .

Extending from near the bottom of the channel 124 is a second or lower electrode 120b formed from a second layer of conductive material. A part (lower) of the second electrode 120b is horizontally coplanar with the junction (not specified) of the drain region 112 and the well region 118, and another part (upper) of the second/bottom electrode 120b is horizontally coplanar with the source region 118 and the first electrode 120a. noodle. Accordingly, the first and second electrodes 120 a and 120 b overlap each other with respect to the depth of the channel 124 , respectively. Upper portions of the sidewalls adjacent to the switch electrode 120a and the top of the shield electrode 120a are covered with a dielectric material 138, such as oxide. Accordingly, dielectric material 138 is located between gate electrodes 120a and 120b.

As described above, the shield electrode 120b and the switch electrode 120a at least partially overlap each other along the depth of the trench 124 . More specifically, in the embodiment shown in FIG. 2, the gate electrode 120a defines a recess 140 at its surface adjacent to the shield electrode 120b, which is located between and/or surrounds sidewalls 142, and The top hat portion 144 of the shield electrode 120b is located in the recess. The sidewall 142 of the switch electrode 120 a and the top hat portion 144 of the shield electrode 120 b at least partially overlap each other in the axial or depth direction of the channel 124 . Thereby an overlapping gate electrode structure is provided. Further, as will be described more fully below, the top hat portion 144 and ledge 146 of shield electrode 120b are formed by etching a portion of dielectric layer 128 that is positioned above the layer of conductive material comprising shield electrode 120b. Adjacent to, above, and below an upper surface (not specified).

In general, the gate or switch electrode 120a functions as a switching electrode and turns MOSFET 100 on and/or off, while the gate or shield electrode 120b functions to create at least part of the channel 132. In order to set MOSFET 100 into conduction mode, bottom/shield electrode 120b must be properly biased and/or turned on. The bottom or shield electrode 120b is either continuously biased to the on or conducting state, or can be biased just prior to switching activity to prime the device by setting it to the conducting state. When the bottom/shield electrode 120b is turned on, the current through the MOSFET is controlled through the gate/bottom electrode 120a.

As described above for the prior art MOSFET 10, the overlap region OL between the gate region 20 and the drain region 12 includes the bottom of the gate channel 24 as shown in FIG. In contrast, the gate switch electrode 120 a does not overlap the drain region 112 . The only area of overlap between the gate switch electrode 120a and the drain region 112 is the channel region 132 of width W, which is typically only a few hundred Angstroms wide. Channel 132 is created by biasing shield electrode 120b. Channel region 132 extends from drain region 112 through well region 114 along channel 124 and shield electrode 120b. The effective gate-drain overlap (ie, the width of channel 132) in MOSFET 100 is thus significantly reduced relative to MOSFET 10 (ie, the bottom region of channel 124, which is typically about 0.3-1.0 microns). Thus, the Miller capacitance of MOSFET 100 is significantly reduced relative to the Miller capacitance of MOSFET 10 because, as mentioned above, Miller capacitance is generally proportional to the gate-drain overlap area.

The improvement (ie, reduction) in the Miller capacitance of MOSFET 100 relative to MOSFET 10 is schematically illustrated in FIG. 3, where the gate voltage waveforms for each device are plotted. The gate voltage waveform Vg ₁₀ of MOSFET 10 has a substantially flat region in which the gate charge Q _gate increases from about 0.0 (zero) to about 2.00×10 ⁻¹⁵ coulombs/micron, while the gate voltage waveform of MOSFET 100 Vg ₁₀₀ has few corresponding roughly flat areas. Thus, it can be seen that the Miller capacitance is substantially and significantly reduced.

It should be particularly noted that in order to avoid any significant adverse effect on the current flow of MOSFET 100, when the device transitions from a state in which only shield capacitor 120b is biased to a state in which main or switch gate 120b is also biased, channel region 132 must be present and Always open. The threshold voltage at which this transition occurs and the final drive voltage level are determined by the cross-over doping concentration at the junction of the P-type well region 114 and the source region 118 .

FIG. 4 plots the net doping profiles at various depths below the source region 118 in the well region 114 . The vertical axis of FIG. 4 corresponds to the interface of the source region 118 and the well region 114 (ie, the “top” of the well region 114 ), and thus is assigned the zero depth value of the well region 114 . The depth of the shielding electrode 120b is about 0.6-0.8 microns below the zero depth, and the drain side of the well region is about 0.7-0.9 microns below the zero depth. Therefore, it can be seen that the net doping in the well region 114 is relatively high, for example, about 1.0×10 ¹⁷ near the source region 118 and decreased to about 3.0×10 ^{− 16} - a doping concentration of about 1.5 x 10 ^-16 . The interface of the well region 114 and the drain region 112 has a minimum dopant concentration, which is 0.84-0.86 microns below the zero depth.

Since the threshold and drive voltage are directly proportional to the oxide thickness and net doping level, the doping profile described above enables the use of a much thicker oxide layer, eg, about 100-1500 Angstroms, near the drain region 112 . The increased thickness of the oxide layer enables the transition from the shield gate 120b to the switch gate 120a with continuous current flow in the channel region 132 .

In operation, the shield electrode 120b is raised or biased to a potential sufficient to support the drive voltage level. In effect, the shield electrode 120b charges the gate-drain overlap region, which is the aforementioned region where Miller capacitance occurs in conventional devices. Once the gate-drain overlap region is charged by the shield electrode 120a, the MOSFET 100 can be easily turned on and/or off by a relatively small change in voltage applied to the switch electrode 120a.

Fabrication of MOSFET 100 constructed as a vertical channel MOSFET is accomplished through the process flow best shown in FIG. 10 . Process flow 300 through the formation of gate 120 is a conventional process flow for forming trench-gated MOSFETs. More specifically, trenches 124 are etched by a conventional trench formation process 302 . A dielectric layer 128 is then deposited on the sidewalls and bottom of the trench 124 , also by a known conventional first dielectric layer deposition process 304 . Thereafter, the fabrication process 300 for fabricating MOSFET 100 differs from conventional process flows.

After the dielectric layer 128 is deposited by the first dielectric layer deposition step 304 , a first layer of conductive material is deposited within the trench 124 with oxidized sidewalls as part of the deposition shield electrode step 306 . Then in a shield electrode etching step 308, the first layer of conductive material is etched to a desired thickness by, for example, reactive ion isotropic etching. Next, the gate dielectric layer 128 is etched in a gate dielectric layer etch step 310 . Gate dielectric etch step 310, eg isotropic etch, also removes a predetermined amount of conductive material 130b adjacent to dielectric material 128, thereby forming top hat structure 144 and ledge 146 of shield electrode 120b. One or more additional etching steps 312 may optionally be performed to remove sharp edges and/or corners in shield electrode 120b. Gate dielectric layer 138 is then deposited by second dielectric layer deposition step 314 . A dielectric layer 138 is deposited on the upper surface (not indicated) of the top cap 144 and ledge 146 of the shield electrode 120b, and on the sidewalls of the channel 124 above the shield electrode 120b. A second layer of conductive material is then deposited within trench 124 as part of step 316 of depositing a switch electrode. The remaining processing steps 318 include conventional processing and polishing steps and are known in the art.

Referring now to FIG. 5, there is shown a second embodiment of the MOSFET of the present invention. MOSFET 400 is a surface-gated vertical MOSFET that includes a double-staggered-gate structure substantially similar to MOSFET 100. Many features and structures of MOSFET 400 are generally similar to MOSFET 100 . Similar to MOSFET 100, MOSFET 400 includes a drain 412, a well 414, a body 416, a source 418, and a gate structure 420, all of which are formed on a substrate 426. In contrast to MOSFET 100, MOSFET 400 is constructed as a surface-gated vertical MOSFET. However, similar to the gate structure 120, the gate structure 420 includes a double-overlap gate structure, which can reduce Miller capacitance and switching losses relative to conventional MOSFET devices.

MOSFET 400 is formed on an N+ type substrate 426 including an upper layer 426a in which N− drain region 412 is formed. The P-type well region 414 is located above the drain region 412 . A heavily doped P+ body region 416 is defined within an upper surface (not indicated) of upper layer 426 a and a corresponding portion of well region 414 . A source region 418 is also formed on the upper surface of the upper layer 426 a and within corresponding portions of the well region 414 . Source regions 418 are formed adjacent to body regions 416 such that source regions 418 are located between body regions 416 . A gate dielectric layer 428, such as oxide, is deposited on the upper surface of the upper layer 416a. Gate dielectric layer 428 partially covers well region 414 and source region 418 .

Like gate structure 120 of MOSFET 100, gate structure 420 of MOSFET 400 is divided into isolation switches and shield electrodes that overlap each other. Gate structure 420 includes a pair of switch electrodes 420a and a pair of shield electrodes 420b on and/or over dielectric layers 428, 434, and 438, as will be more clearly described below.

The switch electrode 420a is formed from a layer of conductive material, such as doped polysilicon, which is deposited on top of the gate dielectric layer 428 and etched to form two isolated switch electrodes 420a. Respective portions of each switch electrode 420a are overlying and/or vertically coplanar with the corresponding source region 418 and well region 414 . The switch electrode 420a and the gate dielectric layer 428 are then covered with a second dielectric layer 438, such as oxide. The portion of the second dielectric layer 438 covering the region between the switch electrodes 420a is then removed by an etching step, leaving the portion of the second dielectric layer 438 covering the switch electrode 420a itself intact.

Shield electrode 420b is then formed by depositing a second layer of conductive material, such as doped polysilicon, on top of first and second dielectric layers 428 and 438 . The second conductive material layer is etched to form the shielding electrode 420b. Respective portions of each shield electrode 420 b are located above and/or vertically coplanar with adjacent portions of the corresponding well region 414 and drain region 412 , thereby forming an overlying double-gated structure 420 . More specifically, etching the shield electrode 420b leaves intact a predetermined portion of the second layer of conductive material that is above the switch electrode (ie, covers the switch electrode 420a). Thus, a portion of each shield electrode 420b overlies and overlaps the corresponding switch electrode 420a, thereby forming a double-overlapping surface-gated structure 420, which reduces Miller capacitance and increases switching times compared to conventional MOSFET devices. Interlayer dielectric layer 434 is then deposited over gate structure 420 and dielectric layers 428 and 438 .

Referring now to FIG. 6, another embodiment of the MOSFET of the present invention is shown. MOSFET 500 is also constructed as a surface-gated vertical MOSFET comprising a double-overlap gate structure 520 similar to gate structure 420 of MOSFET 400. However, in gate structure 420, a portion of each shield electrode 420b overlaps a corresponding switch electrode 420a, whereas each switch electrode 520a of gate structure 520 includes a portion that overlaps (ie, covers or is deposited on) a corresponding shield electrode 420a. parts of (unspecified). The rest of MOSFET 500 is basically similar to MOSFET 400 and therefore will not be discussed in detail.

Referring now to FIG. 7, a further embodiment of the MOSFET of the present invention is shown. MOSFET 600 is constructed as a side MOSFET, which is generally conventional except for the overlapping gate structure 620. The gate structure 620 of MOSFET 600 is divided into overlapping switching electrodes 620a and shielding electrodes 620b, which are located on or over dielectric layers 628, 634, and 638, and are more specifically described below.

A layer of conductive material, such as doped polysilicon, is deposited over gate dielectric 628 and then etched to form shield electrode 620a, with portions of shield electrode 620a at least partially overlying and/or vertically coplanar with well region 614 and drain region 612 . The shield electrode 620a and gate dielectric layer 628 are then covered by a second dielectric layer 638, such as oxide. An etch process is performed, leaving the top and sides of the shield electrode 620b covered by the second dielectric layer 638 , the second dielectric layer 638 is also removed from the gate dielectric layer 628 .

The switch electrode 620a is then formed by depositing a second layer of conductive material, such as doped polysilicon, on the first and second dielectric layers 628 and 638 . The second conductive material layer is then etched to form switch electrode 620a, wherein various parts of switch electrode 620a are located above and/or vertically coplanar with well region 614 and source region 618, thereby forming overlapping double gate structure 620. More specifically, a portion of the switch electrode 620a overlies the second dielectric layer 638 and covers the shield electrode 620b, thereby forming an overlapping gate structure 620 that reduces Miller capacitance and increases switching times relative to conventional MOSFET devices. .

Referring now to FIG. 8, a further embodiment of the MOSFET of the present invention is shown. MOSFET 700 is constructed as a side MOSFET substantially similar to MOSFET 600. However, in MOSFET 600, a portion of switch electrode 620a covers and overlaps shield electrode 620b, while MOSFET 700 includes a portion of shield electrode 720b that covers and/or overlaps switch electrode 720a. The rest of the structure of MOSFET 700 is basically similar to MOSFET 600, so it will not be discussed in detail.

Referring now to FIG. 9, a further embodiment of the MOSFET of the present invention is shown. MOSFET 800 is constructed as a trench-gated MOSFET that is generally similar to MOSFET 100 except for the structural details of the overlapping gate structure 820. In general, MOSFET 800 does not overlap the gate structure by forming recesses and top hat structures as described above with reference to the overlapped gate structure 120, but instead implements the overlapped gate structure 820 by forming the opposing or facing surfaces of the switch and the shield electrode, wherein the switch and the shield electrode The shield electrodes have substantially complementary recesses and protrusions, respectively.

More specifically, MOSFET 800 includes an overlapping gate structure 820 having a switch electrode 820a and a shield electrode 820b formed within a channel 824. The switch electrode 820a has a convex lower surface 821a, while the shield electrode 820b has a concave upper surface 821b. A layer of dielectric material 838 is deposited thereon such that the upper surface of the layer of dielectric material 838 has substantially the same concavity as the recessed upper surface 821b. The switch electrode 820a is located above the recessed layer of dielectric material 838 such that the shape and convexity of the raised lower surface 821a of the switch electrode 820a is substantially complementary to the recessed upper surface 821b. Thus, the concavity of the recessed upper surface 821b ensures that the direction or depth of the switch and shield electrodes 820a and 820b relative to the channel 824 respectively overlaps each other. Thus, the formation of the overlapping trench-gated structure 820 reduces the Miller capacitance of the MOSFET 800 and increases switching speed.

It should be particularly noted that in the embodiment shown in FIG. 9 and described above, the switch electrode 820a has a convex lower surface 821a, while the shield electrode 820b has a concave upper surface 821b, the concavity of the concave upper surface 821b and the convex lower surface 821 The convexity of is such that the direction and depth of the switch and shield electrodes 820a and 820b with respect to the trench 824 overlap each other, respectively. However, it should be understood that MOSFET 800 can be constructed otherwise such that switch electrode 820a has a recessed lower surface 821a and shield electrode 820b has a raised upper surface 821b, the convexity of raised upper surface 821b and the height of recessed lower surface 821. The concavity is such that the orientation and depth of the switch and shield electrodes 820a and 820b relative to the trench 824 respectively overlap each other, thereby forming an overlapping trench gated structure.

In the embodiment shown in FIG. 2, the sidewall 142 of the switch electrode 120a and the top hat portion 144 of the shield electrode 120b at least partially overlap each other in the axial or depth direction of the trench 124, thereby providing overlapping gate electrodes. structure. However, it should be understood that the gate of MOSFET 100 can be configured otherwise, such as having a top cap or protrusion for the switch electrode and a recess for the shield electrode, thereby enhancing a similar overlapping gate electrode structure, that is, generally MOSFET 100. The grid 120 is upside down.

While this invention has been described in terms of its preferred designs, the invention is capable of further modification within the spirit and scope of its disclosure. Accordingly, this patent application is intended to cover any variations, uses or adaptations of the invention which use the general principles disclosed herein. Further, this patent application is intended to cover modifications of the present disclosure, which come from known or conventional technical practice, to which the invention is suited to such practice and which come within the scope of the appended claims.

Claims (23)

1. A gate structure of a semiconductor device, the semiconductor device has a drain region, a well region and a source region, and the gate structure comprises: a shield electrode, portions of which are coplanar with said drain region and said well region, with a first dielectric layer between said shield electrode and said drain region and said well region; a switch electrode, portions of which are coplanar with the well region and the source region, with a second dielectric layer between the switch electrode and the well region and the source region; and The third dielectric layer is located between the shielding electrode and the switching electrode. 2. The gate structure of claim 1, wherein said second and third dielectric layers are layers of the same dielectric material. 3. The gate structure of claim 1, wherein said first and second dielectric layers are layers of the same dielectric material. 4. The gate structure of claim 1, wherein a portion of the switch electrode and a portion of the shield electrode are coplanar. 5. The gate structure of claim 1, wherein a portion of the switch electrode, a portion of the shield electrode, and a portion of the well region are coplanar. 6. The gate structure of claim 5, wherein said common plane is substantially horizontal. 7. The gate structure of claim 5, wherein said common plane is substantially vertical. 8. The gate structure of claim 1, wherein each of said switch electrode and said shield electrode comprises a respective layer of conductive material. 9. The gate structure of claim 1, wherein said first, second and third dielectrics comprise oxide. 10. A semiconductor device having a substrate, said semiconductor device comprising: a well region having a first conductivity type and located on said substrate; a source region defined within said well region, said source region having a second conductivity type; a drain region adjacent to the well region, the drain region having the second conductivity type; a gate structure comprising a shielding electrode and a switch electrode, portions of the shielding electrode being coplanar with the drain region and the well region, a first dielectric layer between the shielding electrode and the drain region and the well region Between regions, each part of the switch electrode is coplanar with the well region and the source region, the second dielectric layer is located between the switch electrode, the well region and the source region, and the third dielectric layer is located between the well region and the source region. between the shielding electrode and the switch electrode. 11. A semiconductor device according to claim 10, wherein said device is constructed as a vertical MOSFET, and further comprising a channel at least partially defined by said well region and adjacent to said source region, said gate structure At least partially within the channel. 12. The semiconductor device according to claim 10, wherein said shield electrode and said switch electrode overlap each other along a portion of said channel depth dimension. 13. The semiconductor device according to claim 12 , wherein said shield electrode includes a top hat portion, said switch electrode has sidewalls defining a recess, said top hat portion is at least partially located on said recessed such that the sidewall overlaps the top hat portion along a portion of the depth dimension of the trench. 14. The semiconductor device according to claim 13, wherein said sidewall overlaps said top hat portion over a predetermined range of depths in said trench, said predetermined range of depths corresponding to and adjacent to said well region. 15. The semiconductor device according to claim 12, wherein said shield electrode has a raised upper surface, said switch electrode has a recessed lower surface, said recessed lower surface is substantially complementary to said raised upper surface, whereby said The switch electrode and the shield electrode overlap each other along a portion of the channel depth dimension. 16. The semiconductor device according to claim 15, wherein said switch electrode and said shield electrode overlap each other over a predetermined range of depth of said channel, said predetermined range of depth corresponding to and adjacent to said well region. 17. The semiconductor device according to claim 12, wherein said shielding electrode has a concave upper surface, said switch electrode has a convex lower surface, said convex lower surface is substantially complementary to said concave upper surface, so that The switch electrode and the shield electrode overlap each other along a portion of the channel depth dimension. 18. The semiconductor device according to claim 15, wherein said switch electrode and said shield electrode overlap each other over a predetermined range of depth of said channel, said predetermined range of depth corresponding to and adjacent to said well region. 19. A semiconductor device according to claim 10, wherein said device is constructed as a vertical MOSFET, said switch electrode is located at least partially over said source and well regions, said shield electrode is at least partially located over said well region and above the drain region. 20. The semiconductor device according to claim 19, wherein said shield electrode and said switch electrode overlap each other on said well region. 21. A semiconductor device according to claim 10, wherein said device is constructed as a side MOSFET, said switch electrode is located at least partially above said source and well regions, said shield electrode is at least partially located in said well region and above the drain region. 22. The semiconductor device according to claim 21, wherein said shield electrode and said switch electrode overlap each other on said well region. 23. A process for manufacturing a semiconductor device, comprising: etching a trench in the well region of the semiconductor, the trench being adjacent to the source region of the semiconductor; lining the walls and the bottom of the trench with a first dielectric layer; depositing a first layer of conductive material; etching the first layer of conductive material to form a shield electrode; etching the first dielectric layer; depositing a second dielectric layer over the shield electrode and over the walls of the trench; and A switch electrode is deposited on the second dielectric in the trench.

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