CN1893540A - Image sensors including active pixel sensor arrays and system - Google Patents

Abstract

In one aspect, an image sensor is provided, which includes a unit active pixel array. Each unit active pixel includes a first active area having a plurality of photoelectric conversion areas, and a second active area separated from the first active area. The first active regions are arranged in rows and columns to define row-extending intervals and column-extending intervals therebetween, and the second active regions are located at the row-extending intervals and column-extending intervals defined between the first active regions corresponding intersections of intervals.

Description

Image sensor and system including active pixel sensor array

technical field

The present invention generally relates to image sensors. More specifically, the present invention relates to active pixel sensors in which the readout circuitry is shared by two or more sensor elements.

Background technique

Certain types of image sensors utilize photodetectors to capture incident light and convert the light into electrical charges that enable image processing. Examples include complementary metal oxide semiconductor (CMOS) image sensors (CIS). CIS devices typically feature analog sensing circuitry coupled to CMOS control circuitry. The analog sensing circuit includes an array of photodetectors with access devices (eg, transistors) for connecting to wordlines and bitlines. The CMOS control circuit may include a timing signal generator and various image processing circuits, such as row decoders, column decoders, column amplifiers, output amplifiers, etc. In general, the construction of CIS devices is similar to that of CMOS memory devices.

FIG. 1 is a block diagram of an example of a CMOS image sensor (CIS). The CMOS image sensor of FIG. 1 generally includes an active pixel sensor (APS) array 10, a timing signal generator 20, a row decoder 30, a row driver 40, correlated double sampling and digital conversion (CDS) circuit 50 , analog to digital converter (ADC) 60 , latch circuit 70 and column decoder 80 .

Those skilled in the art are very familiar with the operation of the CIS shown in FIG. 1 , therefore, detailed description is omitted here. However, timing generator 20 generally controls the timing of operation of row decoder 30 and column decoder 80 . Row driver 40 selectively activates rows of active pixel array 10 in response to row decoder 30 . CDS 50 and ADC 60 respond to column decoder 80 and latch circuit 70 to sample and output the column voltage of active pixel array 10. In this instance, image data is output from the latch circuit 70 .

APS array 10 contains a plurality of active unit pixels arranged in rows and columns. Each active unit pixel includes a photoelectric conversion device and a readout circuit for transferring charges of the photoelectric conversion device to an output line.

Referring now to FIG. 2 , FIG. 2 is an equivalent circuit diagram of an example of an active pixel 22 of the APS array 10 shown in FIG. 1 .

A photoelectric conversion element PD (such as a photodiode, a photo-gate type picture element, etc.) of the active pixel 22 captures incident light and converts the captured light into charges. The charge is selectively transferred from the photoelectric conversion element PD to the floating diffusion region FD through the transfer transistor TX. The transfer transistor TX is controlled by the transfer gate TG signal. The floating diffusion FD is connected to the gate of Dx, and the driving transistor Dx functions as a source follower (amplifier) that buffers the output voltage. The output voltage is selectively converted to the output voltage OUT by the selection transistor Sx. The selection transistor Sx is controlled by a row selection signal SEL applied to the gate of the selection transistor Sx. Finally, the reset transistor Rx is controlled by the reset signal RS, so as to selectively reset the charges accumulated in the floating diffusion area to the reference voltage level.

Note that one or more transistors shown in FIG. 2 may be selectively omitted. For example, the floating diffusion FD may be electrically connected to the photoelectric conversion element PD, and in this case, the transfer transistor TX may be omitted. As another example, the drive transistor Dx may be electrically connected to the output line OUT, in which case the select transistor Sx may be omitted.

In the process of trying to increase the pixel density, it has been known that CIS devices can be constructed so that their unit active pixels contain a plurality of photoelectric conversion elements PD, and the plurality of photoelectric conversion elements PD share a common readout circuit. However, the conventional shared pixel CIS configuration and layout has the disadvantage that the photoelectric conversion element PD is defined as a small light photoelectric conversion area. Furthermore, the photoelectric conversion regions are spaced apart from one another at different pitches in the row and/or column direction. Therefore, the conversion efficiency and/or image quality of these CIS devices are adversely affected.

Contents of the invention

According to one aspect of the present invention, there is provided an image sensor including an active pixel array including a plurality of unit pixels on a substrate. Each unit pixel includes at least one first active region of the substrate, and second and third active regions of the substrate spaced apart from each other and from the at least one first active region. The at least one first active region includes four photoelectric conversion regions.

According to another aspect of the present invention, there is provided an image sensor including an active pixel array including a plurality of unit active pixels formed on a substrate. The first unit pixel includes at least one first active region of the substrate, and second and third active regions of the substrate spaced apart from each other and from the at least one first active region, Wherein, the at least one first active region includes four photoelectric conversion regions aligned along the first direction. The second unit pixel includes at least one fourth active region of the substrate, and fifth and sixth active regions of the substrate spaced apart from each other and from the at least one fourth active region, Wherein, the at least one fourth active region includes four photoelectric conversion regions aligned parallel to the first direction and respectively adjacent to the four photoelectric conversion regions of the first unit pixel.

According to another aspect of the present invention, an image sensor is provided, which includes an active pixel array including a unit active pixel array. Each unit active pixel includes at least one first active region and elongate second and third active regions within the substrate, the at least one first active region includes four photoelectric conversion regions. The elongated second and third active regions are spaced apart from the first active region and extend longitudinally along the first direction.

According to yet another aspect of the present invention, there is provided a system comprising a processor connected to a data bus, a memory and an image sensor. The image sensor includes an active pixel array, wherein, for each unit active pixel of the active pixel array, the readout circuit is shared by at least four photoelectric conversion regions, and wherein the distance between adjacent photoelectric conversion regions The directions along the columns and rows of the active pixel array are substantially the same.

Description of drawings

The above and other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

Fig. 1 is the block diagram of CMOS image sensor (CIS) device;

FIG. 2 is an equivalent circuit diagram of active pixels in the active pixel array of the CIS device of FIG. 1;

3 is a circuit diagram of an active pixel sensor (APS) array according to an embodiment of the present invention;

Fig. 4, Fig. 5 and Fig. 6 show the active pixel layout of the APS array according to the embodiment of the present invention;

Fig. 7 shows the layout of the microlens of the APS array according to the embodiment of the present invention;

8 is a cross-sectional view of an active pixel according to an embodiment of the present invention;

9 is a timing diagram (timingdiagram) explaining the operation of the APS array according to an embodiment of the present invention;

FIG. 10 shows an active pixel layout of an APS array according to another embodiment of the present invention;

11 shows an active pixel layout of an APS array according to another embodiment of the present invention; and

12 is a block diagram of a processor-based system employing an image sensor including an APS array according to an embodiment of the present invention.

Detailed ways

The invention will now be illustrated by means of preferred non-limiting examples.

3 is a circuit diagram illustrating a shared four-pixel active pixel array (APS) according to a non-limiting embodiment of the present invention. Here, the phrase "shared four-pixel APS" means that the four photoelectric conversion elements of the APS share the same readout circuit. This paper refers to each group of four photoelectric conversion elements and their associated readout circuits as a "unit active pixel".

Referring to FIG. 3, the shared four-pixel APS includes a plurality of rows (i, i+1, ...) and columns (j, j+1, j+2, j+3, ...) arranged Unit active pixel P. Each unit active pixel P has a similar structure, so only the unit active pixel P(i, j+1) will be described below.

The unit active pixel P(i, j+1) includes a group 11 composed of four photoelectric conversion elements 11a, 11b, 11c, and 11d and a group 15 composed of four transfer transistors 15a, 15b, 15c, and 15d, and a common Floating diffusion area 13. As shown in FIG. 3, transfer transistor 15a and photoelectric conversion element 11a are connected in series between floating diffusion region 13 and a reference potential (eg, ground potential). The transfer transistor 15b and the photoelectric conversion element 11b are connected in series between the floating diffusion region 13 and a reference potential (for example, ground potential). The transfer transistor 15c and the photoelectric conversion element 11c are connected in series between the floating diffusion region 13 and a reference potential (for example, ground potential). The transfer transistor 15d and the photoelectric conversion element 11d are connected in series between the floating diffusion region 13 and a reference potential (for example, ground potential).

The transfer transistor 15a is gated to and controlled by a transfer gate line TX(i)a connected to each unit active pixel of row (i) p. The transfer transistor 15b is connected through a gate to and controlled by a transfer gate line TX(i)b connected to each unit active pixel P of the row (i). The transfer transistor 15c is connected through a gate to and controlled by a transfer gate line TX(i)c connected to each unit active pixel P of the row (i). The transfer transistor 15d is connected through a gate to and controlled by a transfer gate line TX(i)d connected to each unit active pixel P of the row (i).

The floating diffusion region 13 is connected to the gate of the driving transistor 17, and the driving transistor 17 and the selection transistor 19 are connected in series between a reference voltage (for example, Vdd) and an output line Vout. The selection transistor 19 is connected through a gate to and controlled by a selection line SEL(i) connected to each unit active pixel P of the row (i). The reset transistor 18 is connected between a reference voltage (for example, Vdd) and the floating diffusion region 13, and the reset transistor 18 is connected through a gate to and controlled by a reset line RX(i), which is connected to the row Each unit active pixel P of (i).

During operation, the photoelectric conversion elements 11a to 11d of the unit active pixel P(i, j+1) capture incident light, and convert the captured light into charges. The photoelectric conversion elements 11a to 11d may be selectively realized by photodiodes or shutter-type picture elements, but other types of photoelectric conversion devices may also be employed. Charges are selectively transferred from the photoelectric conversion elements 11a to 11d to the floating diffusion region 13 through the transfer transistors 15a to 15d under the control of the transfer gate lines TX(i)a to TX(i)d, respectively.

The drive transistor 17 connected to the floating diffusion region 13 functions as a source follower (amplifier) that buffers the output voltage. The selection transistor 19 selectively transmits the output voltage to the output line Vout in response to the selection line SEL(i). Finally, the reset transistor 18 is controlled by the reset line RX(i), so as to selectively reset the charges accumulated in the floating diffusion region 13 to a reference voltage level (eg, Vdd).

4 is a top view illustrating a layout of active regions and transistor gates of a unit active pixel according to an embodiment of the present invention.

Referring to FIG. 4, each unit active pixel includes four (4) active region patterns A1 to A4 on the surface of a semiconductor substrate. The non-active region of the substrate may be, for example, an insulating region such as a shallow trench isolation (STI) region or a local oxidation of silicon (LOCOS) region. Alternatively, the non-active region of the substrate may be, for example, a junction isolation region, such as a highly counter-doped impurity region.

The first active region pattern A1 of this example contains two photoelectric conversion element regions PD1 and PD2 , a floating diffusion region FD, transfer gates TG1 and TG2 , and a reset gate RG. The photoelectric conversion regions PD1 and PD2 correspond to the photoelectric conversion elements 11a and 11b of FIG. 3, the floating diffusion region FD corresponds to the floating diffusion region 13 of FIG. 3, and the transfer gates TG1 and TG2 correspond to the transfer transistors 15a and 15b of FIG. , the reset gate RG corresponds to the gate of the reset transistor 18 in FIG. 3 .

The second active region pattern A2 of this example contains two photoelectric conversion element regions PD3 and PD4, a floating diffusion region FD, transfer gates TG3 and TG4, and a dummy gate DG. The photoelectric conversion regions PD3 and PD4 correspond to the photoelectric conversion elements 11c and 11d of FIG. 3, the floating diffusion region FD corresponds to the floating diffusion region 13 of FIG. 3, and the transfer gates TG3 and TG4 correspond to the transfer transistors 15c and 15d of FIG. the grid.

The floating diffusion region FD of the first active region pattern A1 is electrically connected to the floating diffusion region FD of the second active region pattern A2 through a wire (not shown). A dummy gate DG is optionally provided to match the layout of the gate pattern of the first active region pattern A1.

The third active area pattern A3 includes a source follower gate SFG, and the fourth active area pattern A4 includes a row selection gate RSG. The row select gate RSG corresponds to the gate of the select transistor 19 of FIG. 3 , and the source follower gate SFG corresponds to the gate of the drive transistor 17 of FIG. 3 .

Still referring to FIG. 4 , the first active region pattern A1 includes two vertically aligned active region portions a11 and a12 including photoelectric conversion elements PD1 and PD2 , respectively. For explanation purposes, the vertical direction is defined as the dashed line "x" in FIG. 4, which coincides with the column direction of the APS array shown in FIG. Each active region portion a11 and a12 has multi-faceted polygonal outer peripheries. It is intended that these outer borders be approximately circular to conform as closely as possible to the configuration of the microlenses (not shown) located above the photoelectric conversion regions PD1 and PD2. Furthermore, in the example of this embodiment, the active area portions a11 and a12 are separated by a local space SL, and the active area portions a11 and a12 substantially define mirror images of each other with respect to a horizontal axis centrally located between them. The horizontal direction is parallel to the dotted line "y" in FIG. 4 and parallel to the row direction of FIG. 3 .

The active area portions a11 and a12 are connected at opposite corners by the active area portion c1 of the first active area pattern A1. As shown, the active region portion c1 contains at least a portion of the floating diffusion region FD. A transfer gate channel region is defined in the active region portion a11 and/or c1 located below the first transfer gate TG1, and a transfer gate channel region is defined in the active region portion a12 and/or c1 below the second transfer gate TG2. /or c1 defines another transfer gate channel region.

Other corners of active area portions a11 and a12 (ie, corners not connected to active area portion c1 ) include notched or indented peripheral portions to allow for close placement of adjacent unit active pixel portions. This aspect of the embodiment is described in more detail below with reference to FIG. 5 .

Still referring to FIG. 4 , the first active region pattern A1 further includes an active region extension portion b extending outward from the active region portion c1 in a horizontal direction. A reset gate channel region is defined within the active region portion c1 and/or b located below the reset gate RG. Although not shown, the active region extension b may be connected to a reference potential (eg, Vdd).

The second active region pattern A2 includes two vertically aligned active region portions a21 and a22 including photoelectric conversion elements PD3 and PD4, respectively. Again, the vertical direction is defined as the dashed line "x" in FIG. 4, which coincides with the column direction of the APS array shown in FIG. Each active region portion a21 and a22 has a faceted polygonal outer boundary, which is intended to be substantially circular. Active area portions a21 and a22 are separated by local spacing SL, and active area portions a21 and a22 substantially define mirror images of each other with respect to a centrally located horizontal axis (parallel to the "y" or row direction).

The active area portions a21 and a22 are connected at opposite corners by the active area portion c2 of the second active area pattern A2. As shown, the active region portion c2 contains at least a portion of the floating diffusion region FD. A transfer gate channel region is defined in the active region portion a21 and/or c2 below the first transfer gate TG3, and a transfer gate channel region is defined in the active region portion a22 and/or c2 below the second transfer gate TG4. /or c2 defines another transfer gate channel region.

Other corners of active area portions a21 and a22 (ie, corners not connected to active area portion c2) include notched or indented peripheral portions to allow for close placement of adjacent unit active pixel portions. This aspect of the embodiment will again be described in more detail below with reference to FIG. 5 .

The first and second active area patterns A1 and A2 are separated by the active pixel spacing SAP about the horizontal axis (parallel to “y” or Row direction) essentially define mirror images of each other. Preferably, referring to Fig. 4, the active pixel spacing SAP is substantially the same as the local spacing SL.

As shown in FIG. 4, the third active area pattern A3 is extended in the vertical direction, and is between and separated from the first and second active area patterns A1 and A2, the first and second active area patterns A1 A2 and A2 adjoin the lower and upper corners of the third active area pattern A3, respectively. Also, in this instance, the left side of the third active area pattern A3 is substantially vertically aligned with the right side of the active area portions a11 to a22.

The fourth active area pattern A4 is also elongated in the vertical direction and spaced apart from the second active area pattern A2 adjacent to its upper corner. In this instance, the left side of the fourth active area pattern A4 is substantially vertically aligned with the right side of the active area portions a11 to a22.

Note that the floating diffusion region FD is an example of a readout storage node region for reading out charges accumulated in the photoelectric conversion element regions PD1 to PD4. However, the present invention is not limited to the use of floating diffusion areas, but other types of sensing storage node areas can also be implemented.

Furthermore, the embodiment of FIG. 3 is intended to realize the circuit configuration of FIG. 2 . However, the invention is not limited to this consideration, but other circuit configurations can also be realized.

In addition, the active regions A1 and A2 may be combined into a single active region as long as the photoelectric conversion regions PD1 to PD4 are kept electrically isolated from each other. This can be achieved, for example, by forming impurity regions within the active region.

FIG. 5 shows the array of active area patterns shown in FIG. 4 .

Referring to FIG. 4 and FIG. 5 together, the active region patterns A1/A2 are vertically aligned in columns and horizontally aligned in rows. Here, the distance between adjacent active region patterns A1 / A2 in the same row is defined as the column interval SC. Here, the distance between adjacent active region patterns A1/A2 in the same column is defined as the row interval SR. Moreover, as previously mentioned, the interval between the active area parts A1 and A2 is defined here as the active pixel interval SAP, and the interval between the active area parts a11 and a12 (and a21 and a22) is defined as the local interval SL.

The third active area pattern A3 is located at the intersection of the active pixel interval SAP and the column interval SC. In addition, the third active area pattern A3 extends lengthwise in the direction of the column spacing SC. As described above, as shown in FIG. 5 , corners of the first and second active area patterns A1 and A2 are notched or indented so as to leave enough space for placing the third active area pattern A3 .

The fourth active region pattern A4 is located at the intersection of the row interval SR and the column interval SC. In addition, the fourth active region pattern A4 extends lengthwise in the direction of the column spacing SC. Again, as shown in FIG. 5, the corners of the first and second active area patterns A1 and A2 are notched or indented so as to leave enough space for placing the fourth active area pattern A4.

The column spacing SC, row spacing SR, active pixel spacing SAP and local spacing SL are preferably all the same. Also, the width of each third and fourth active pattern area A3 and A4 is preferably the same and consistent with the width of each column space SC.

In each row, the active area extension portion b of each active area pattern A1 extends beyond the column interval SC and is located between the active area portions a11 and a12 of adjacent active area patterns A1. Again, the corners of the active area portions a11 and a12 of the active area pattern A1 are notched or indented so as to leave enough space for placing the active area extension portion b of the adjacent active area pattern A1.

The construction of the example shown in Figures 4 and 5 has many advantages. For example, the column pitch P1 and the row pitch P2 between the centers PC of the photoelectric conversion region PD can be easily balanced by proper design of the column spacing SC, row spacing SR, active pixel spacing SAP and local spacing SL. In addition, by extending the portion b of each active area pattern A1 between the portions a11 and a12 of adjacent active area patterns A1 within the same row, the pixel density is increased (ie, pitch is reduced). Also, the pixel density is further improved by disposing the active area pattern A2 longitudinally along the column interval SC.

The present invention is not limited to the specific examples of FIGS. 4 and 5 . As just one example, the reset gate RG may be placed in the third active area pattern A3 instead of the first active area pattern A1. Also, the outer boundaries of the active region patterns A1 and A2 are not necessarily the same as those shown in the examples of FIGS. 4 and 5 . As can be understood by those skilled in the art, various changes can be made without departing from the spirit and scope of the invention.

Attention is now drawn to FIG. 6, which shows a barrier layer M positioned over the array shown in FIG. 4 to 6 collectively, the blocking layer M defines a plurality of optical apertures 165 aligned over portions a11 to a22 of the first and second active area patterns A1 and A2. The blocking layer M may be formed of, for example, an aluminum or copper layer, and functions to prevent light from being incident on the floating diffusion FD and the readout circuits (TG1, TG2, RG, RSG, and SFG).

In a preferred instance of this embodiment, the column spacing SC, row spacing SR, active pixel spacing SAP and local spacing SL are all equal. In this case, the barrier layer M has substantially the same horizontal widths WR_odd and WR_even, and vertical widths WC_odd and WC_even.

In FIG. 6, letters R, G, and B denote red, green, and blue color filter regions, respectively. As can be understood by those skilled in the art, in the example of FIG. 6, the R, G and B color filters are arranged in a so-called Bayer pattern.

FIG. 7 shows an example of the location of microlenses of an APS array according to an embodiment of the present invention. As shown in this figure, a plurality of microlenses 200 are respectively located on the photoelectric conversion region of the APS array such as described above in conjunction with FIGS. 4-6 . The function of the microlens 200 is to focus and filter the incident light and make it incident on the lower photoelectric conversion region.

In FIG. 7, reference symbol F denotes the focus of each lens 200, and reference symbol PC denotes the center of gravity of each lower photoelectric conversion region. As shown, the focal point F and center PC can be intentionally shifted within selected regions of the APS array to compensate for different angles of light incident across the surface of the APS array. For example, as shown in FIG. 7, the focal point F and center PC can be offset in the left and right portions of the APS array, while the focal point F and center PC can be aligned in the central portion of the APS array.

FIG. 8 is a diagram illustrating an example of a schematic cross-sectional view taken along line A-A' of FIG. 7 .

Referring to FIG. 8 , a photoelectric conversion element 110 including a pinning layer 114 and a photodiode region 112 is formed in an n-type doped semiconductor substrate 101 having a p-type epitaxial layer 107 . In this example, a gathering layer 103 (functioning to reduce dark current and reduce white defects) is also formed by implanting group IV atoms such as carbon, germanium or a combination thereof.

Isolation regions 109 are formed within the substrate surface to define active region patterns (eg, A1 and A2 in FIG. 4 ). Afterwards, a gate dielectric layer 134 is formed on the substrate 101 with a thickness of approximately 5 to 100 Ȧ. For example, _the gate dielectric layer 134 may be formed of _the following materials: SiO ₂ , SiON, SiN, Al ₂ O ₃ , Si ₃ N ₄ , _{GexOyNz , GexSiyOz , HfO2} , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ or a combination of two or more thereof.

Gate electrodes 136 and gate spacers 138 are then formed to define pass transistors, drive (source follower) transistors (not shown) and row select transistors (not shown). For example, the gate electrode 136 can be made of the following materials: polysilicon, W, Pt, Al, TiN, Co, Ni, Ti, Hf, Pt or a combination of two or more of these materials, and the gate spacer 138 can be made of Formed from SiO ₂ , SiN or a combination thereof. As shown in FIG. 8, a floating diffusion region 120 doped with n-type impurities and a pin connection layer 114 doped with p-type impurities are also formed.

Reference numeral 170 of FIG. 8 denotes one or more interlayer dielectric (ILD) layers formed over the substrate 101 , and reference numerals 145 and 155 denote conductive lines formed within the ILD layer 170 . The conductive plug 140 connecting the floating diffusion region 120 and the conductive line 145 is formed, and the conductive plug 150 electrically connecting the transfer gate 130 to the second conductive line 155 is formed. The conductive plugs 140 and 150, and the conductive lines 145 and 155 may be formed of, for example, polysilicon and/or a metal such as aluminum or copper.

Also formed in the ILD 170 is a barrier layer 160 made of, for example, aluminum, copper, or other metallic material. The barrier layer 160 corresponds to the barrier layer M shown in FIG. 6 . A first planarization layer 180, a color filter pattern 190, and a second planarization layer 195 are sequentially formed over the ILD 170, and then, a microlens 200 is formed over the second planarization layer 195. As described above in connection with FIG. 7, the focal point of the microlens 200 can be intentionally shifted to compensate for different incident angles of light incident across the surface of the APS array.

FIG. 9 is a timing diagram explaining an example of operation of a shared two-pixel APS array according to an embodiment of the present invention. Specifically, the example given here is the "charge summation" process, in which the charges from two photoelectric conversion regions are summed to obtain a single light intensity value. In this embodiment, the color filters of the APS array are arranged in a Bayer configuration as shown in FIG. 5 . Charge summation is particularly useful in active image mode, where the APS array provides a large amount of data, which may exceed the processing capabilities of the image signal processor.

Referring to FIGS. 2 , 5 , and 9 in common, the photoelectric conversion elements 11 in each row of the APS array simultaneously accumulate charges depending on the light incident thereon. The following explanations relate to the pixel P(i, j+1) in FIG. 2 . It is assumed here that the pixel P(i, j+1) corresponds to the second column of photoelectric conversion regions shown in FIG. 5 . These photoelectric conversion regions respectively have green G, blue B, green G and blue B color filters from top to bottom in FIG. 5 .

At time t0, the select line SEL(i) is driven HIGH, thereby activating (turning on) the select transistor 19 . Next, a clock pulse is applied to the reset line RX(i), and the reset transistor 18 resets the floating diffusion region 13 to the power supply voltage (for example, Vdd) in response to the clock pulse.

Between times t1 and t2 , a signal pulse is applied to the first transfer line TX(i)a, thereby activating the first transfer transistor 15 a to transfer electrons in the photoelectric conversion element 11 a (green G) to the floating diffusion region 13 . The charge in the floating diffusion region 13 is applied to the gate of the driving transistor 17, thereby generating a corresponding output voltage on the output line Vout. The output line Vout is connected to a correlated subsampler CDS 50 (FIG. 1), which maintains the voltage level of the output Vout and compares it with the previous voltage level of the output Vout.

Thereafter, between times t2 and t3, a signal pulse is applied to the third transfer line TX(i)c, thereby activating the third transfer transistor 15c, and transferring electrons in the photoelectric conversion element 11c (green G) to the floating diffusion region 13 . The charge in the floating diffusion region 13 is applied to the gate of the driving transistor 17, thereby generating a corresponding output voltage on the output line Vout.

Then, the charges thus obtained from the photoelectric conversion elements 11a and 11c are summed, and the green G light intensity of the active unit pixel is obtained.

After that, at time t4, a clock pulse is applied to the reset line RX(i) again, and the reset transistor 18 resets the floating diffusion region 13 to the power supply voltage (for example, Vdd) again in response to the clock pulse.

Between times t5 and t6, a signal pulse is applied to the second transfer line TX(i)b, thereby activating the second transfer transistor 15b to transfer electrons in the photoelectric conversion element 11b (blue B) to the floating diffusion region 13 . The charge in the floating diffusion region 13 is applied to the gate of the driving transistor again, thereby generating a corresponding output voltage on the output line Vout.

Next, between times t6 and t7, a signal pulse is applied to the fourth transfer line TX(i)d, thereby activating the fourth transfer transistor 15d, and transferring electrons in the photoelectric conversion element 11d (blue B) to the floating diffusion region 13. The charge in the floating diffusion region 13 is applied to the gate of the driving transistor 17, thereby generating a corresponding output voltage on the output line Vout.

Then, the charges thus obtained from the photoelectric conversion elements 11b and 11d are summed to obtain the blue B light intensity of the active unit pixel.

Thereafter, the above process is repeated for every other row of the APS array.

As previously stated, the present invention is not limited to the specific examples given above in connection with FIGS. 2-9. For example, attention is paid to FIG. 10 in which an alternative active area pattern layout according to another embodiment of the present invention is shown.

The active area pattern layout shown in FIG. 10 is similar to the layout shown in FIG. 4 in that it includes four (4) active area patterns A5 , A6 , A7 and A8 . However, the extension b in FIG. 4 is omitted in the layout shown in FIG. 10 . In addition, in FIG. 10 , the reset gate RG is located over the active area pattern A7 , and, in FIG. 10 , both the source follower gate SFG and the selection gate RSG are located over the active area pattern A8 .

Fig. 11 shows another alternative active area pattern layout according to another embodiment of the present invention. This embodiment also includes four (4) active area patterns A9, A10, A11 and A12. The first active area pattern A9 includes an active area part c at the center of four equally spaced active area parts a11 , a12 , a21 , and a22 arranged in a matrix shown in FIG. 11 . The active region portions a11, a12, a21, and a22 contain photoelectric conversion regions PD1 to PD4, respectively. The active area portion c contains a common floating diffusion area FD, and transfer gates TG1 to TG4 located between the floating diffusion area FD and the corresponding active area portions a11 to a22.

As shown in FIG. 11 , the horizontal interval between the active region parts a11 , a12 , a21 and a22 is defined as an active pixel row interval SAPR, and the vertical interval is defined as an active pixel column interval SAPC. The widths of the row interval SR, the column interval SC, the active pixel row interval SAPR and the active pixel column interval SAPC are preferably substantially equal.

The active area patterns A10, A11, and A12 are all elongated and extend longitudinally in a vertical (column) direction. Also, as shown in FIG. 11 , the active region pattern A10 is located at the intersection of the row interval SR and the active pixel column interval SAPC. The active region pattern A11 is located at the intersection of the column interval SC and the active pixel row interval SAPR. Finally, the active region pattern A12 is located at the intersection of the row interval SR and the column interval SC.

Also, in this example of an embodiment, the reset gate RG is located over the active area A10, the source follower gate SFG is located over the active area A11, and the select gate RSG is located over the active area A12.

FIG. 12 shows an exemplary processor-based system with a CMOS imaging device 542 comprising an image sensor according to the above-described embodiments of the invention. The processor-based system is an exemplary system that receives the output of a CMOS imaging device. Such systems may include, without limitation, computer systems, camera systems, scanners, machine vision systems, vehicle navigation systems, video phones, surveillance systems, autofocus systems, celestial tracker systems, motion detection systems, Image stabilization systems, mobile phones, they can all employ embodiments of the present invention.

Referring to FIG. 12 , the processor-based system in this example generally includes a central processing unit (CPU) 544 , eg, a microprocessor, in communication with input-output (I/O) devices 546 via a bus 552 . CMOS imaging device 542 generates an output image from signals provided by the active pixel array of the image sensor and communicates with the system via bus 552 or other communication lines. The system may also include random access memory (RAM) 548 and, in the case of a computer system, peripheral devices such as a floppy disk drive 554 and a display 556 which also communicate with CPU 544 via bus 552. It may also include other peripheral devices, such as a flash memory card slot and the like. It is also desirable to integrate processor 544, CMOS imaging device 542 and memory 548 onto a single integrated circuit (IC) chip.

Although the invention has been described above in conjunction with its preferred embodiments, the invention is not limited thereto. On the contrary, various changes and modifications to the preferred embodiment will become apparent to those skilled in the art. Naturally, the invention is not limited to the preferred embodiments described above. Rather, the true spirit and scope of the invention is defined by the claims.

This application claims priority to Korean Patent Application No. 10-2005-0061968 and No. 10-2005-0068102 filed on Jul. 9, 2005 and Jul. 26, 2005, respectively, which are hereby incorporated by reference in their entirety. refer to.

Claims (34)

1. imageing sensor, comprise active pixel array, described active pixel array comprises a plurality of unit picture elements that are positioned on the substrate, wherein, each described unit picture element comprises at least one first active area of described substrate, and be spaced from each other and the second and the 3rd active area of the described substrate that separates with described at least one first active area, wherein, described at least one first active area comprises four photoelectric conversion regions.

2. imageing sensor as claimed in claim 1, wherein, described at least one first active area comprises two active areas, each described active area all comprises two in described four photoelectric conversion regions.

3. imageing sensor as claimed in claim 1 wherein, separates described first to the 3rd active area by the isolated area in the described substrate.

4. imageing sensor as claimed in claim 3 wherein, forms described isolated area by at least one insulation layer in the described substrate or eliminant isolated area.

5. imageing sensor as claimed in claim 1, wherein, described photoelectric conversion region is optical gate type imageing sensor district or photodiode region.

6. imageing sensor as claimed in claim 1 also comprises first and second transistor gates on the second and the 3rd active area that lays respectively at the per unit active pixel.

7. imageing sensor as claimed in claim 6, wherein, described the first transistor grid is to select one of grid, driving grid and reset gate, described transistor seconds grid is one different in described selection grid, driving grid and the reset gate.

8. imageing sensor as claimed in claim 6, wherein, described the first transistor grid is to select one of grid and driving grid, described transistor seconds grid is another in described selection grid and the driving grid.

9. imageing sensor as claimed in claim 1, wherein, four photoelectric conversion regions of each described unit active pixel are aimed at along first direction.

10. imageing sensor as claimed in claim 1, wherein, four photoelectric conversion regions of each described unit active pixel are by arranged.

11. imageing sensor as claimed in claim 1, wherein, four photoelectric conversion regions of each described unit active pixel are shared at least one and are read the memory node district.

12. imageing sensor as claimed in claim 11 also comprises laying respectively at the described a plurality of transmission grids between memory node district and described four photoelectric conversion regions of reading.

13. imageing sensor as claimed in claim 9, wherein, described at least one first active area also comprises: be connected to first of preceding two photoelectric conversion regions in described four photoelectric conversion regions and read the memory node district and be connected to second of latter two photoelectric conversion region in described four photoelectric conversion regions and read the memory node district.

14. imageing sensor as claimed in claim 9, wherein, the described second and the 3rd active area is elongated and along being parallel to the direction longitudinal extension of described first direction.

15. imageing sensor as claimed in claim 1, wherein, the external boundary of each in described four photoelectric conversion regions is a polygon.

16. an imageing sensor comprises active pixel array, described active pixel array is included in a plurality of units active pixel that forms on the substrate, and wherein, described a plurality of units active pixel comprises:

First unit picture element, at least one first active area that comprises described substrate, and be spaced from each other and the second and the 3rd active area of the described substrate that separates with described at least one first active area, wherein, described at least one first active area comprises four photoelectric conversion regions of aiming at along first direction;

Second unit picture element, at least one the having ideals, morality, culture, and discipline source region that comprises described substrate, and be spaced from each other and the 5th and the 6th active area of the described substrate that separates with described at least one having ideals, morality, culture, and discipline source region, wherein, described at least one having ideals, morality, culture, and discipline source region comprise four be parallel to described first direction aim at, and respectively with four photoelectric conversion regions that photoelectric conversion region is adjacent of described first unit picture element.

17. imageing sensor as claimed in claim 16, wherein, the spacing between the center of gravity of the adjacent photoelectric conversion region of the described first and second unit active pixels is identical.

18. imageing sensor as claimed in claim 16, wherein, aim at the second and the 3rd active area of described first unit picture element in the interval between four photoelectric conversion regions of four photoelectric conversion regions of the described first unit active pixel and described second unit picture element.

19. imageing sensor as claimed in claim 18, wherein, described second active area with described four photoelectric conversion regions of aiming at of described first and second unit picture elements in two photoelectric conversion regions in centre between the border position adjacent, described the 3rd active area is adjacent with the end of described four photoelectric conversion regions of aiming at of described first and second unit picture elements.

20. imageing sensor, comprise active pixel array, described active pixel array comprises the array of unit active pixel, each described unit active pixel comprises at least one first active area in the substrate and the second and the 3rd elongated active area, described at least one first active area comprises four photoelectric conversion regions aiming at along first direction, described the second and the 3rd elongated active area and described first active area separate, and extend along described first direction lengthwise.

21. imageing sensor as claimed in claim 20, wherein, each described at least one first active area also comprises first reads the memory node district between adjacent described first and second photoelectric conversion regions, and second reads the memory node district between adjacent described third and fourth photoelectric conversion region.

22. imageing sensor as claimed in claim 21, wherein, described first and second read the memory node district is electrically connected mutually.

23. imageing sensor as claimed in claim 21, wherein, each external boundary in described a plurality of photoelectric conversion regions is defined as polygon, wherein, described first reads the memory node district is positioned between the relative bight of described first and second photoelectric conversion regions, and described second reads the memory node district is positioned between the relative bight of described third and fourth photoelectric conversion region.

24. imageing sensor as claimed in claim 23, wherein, described at least one first active area also comprises from described first reads the elongated expansion area of edge, memory node district perpendicular to the second direction lengthwise extension of described first direction.

25. imageing sensor as claimed in claim 24, wherein, extend between adjacent first and second photoelectric conversion regions of the first adjacent active area the elongated expansion area of described at least one first active area.

26. imageing sensor as claimed in claim 20, wherein, arrange described four photoelectric conversion regions of described unit active pixel array by row and column, thereby the row extension of defining is therebetween extended the interval with row at interval, and wherein, the row that defines between described four photoelectric conversion regions of the described second and the 3rd active area of described unit active pixel array extends at interval and row extend corresponding infall at interval.

27. imageing sensor as claimed in claim 22, wherein, in described at least one first active area each also comprises at described first photoelectric conversion region and described first reads the transmission of first between memory node district grid, read the transmission of second between memory node district grid at described second photoelectric conversion region and described first, read the transmission of the 3rd between memory node district grid at described the 3rd photoelectric conversion region and described second, and read the transmission of the 4th between memory node district grid at described the 4th photoelectric conversion region and described second.

28. imageing sensor as claimed in claim 27, wherein, each in described at least one first active area also comprises reset gate.

29. imageing sensor as claimed in claim 28, wherein, each in described second active area comprises source follower gate and selects one of grid that each in described the 3rd active area comprises another in source follower gate and the selection grid.

30. imageing sensor as claimed in claim 27, wherein, each in described at least one second active area comprises reset gate.

31. imageing sensor as claimed in claim 30, wherein, each in described the 3rd active area comprises source follower gate and selects grid.

32. system, comprise the processor, memory and the imageing sensor that are connected to data/address bus, described imageing sensor comprises active pixel array, in described active pixel array, for the per unit active pixel of described active pixel array, reading circuit is shared by at least four photoelectric conversion regions, and at the row and the line direction of described active pixel array, the spacing between the adjacent photoelectric conversion region is basic identical.

33. system as claimed in claim 32, wherein, each described unit active pixel comprises that at least one contains first active area of four photoelectric conversion regions, and the second and the 3rd active area that separates each other and separate with described first active area.

34. system as claimed in claim 32, wherein, arrange described four photoelectric conversion regions of described unit active pixel array by row and column, thereby the row extension of defining is therebetween extended the interval with row at interval, and wherein, the row that defines between described four photoelectric conversion regions of the described second and the 3rd active area of described unit active pixel array extends at interval and row extend corresponding infall at interval.

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