CN1890784A - Strained semiconductor substrate and processes therefor - Google Patents

Abstract

A method of manufacturing an integrated circuit utilizing a strained silicon (SMOS) substrate (20). The substrate (20) utilizes trenches (36) in the base layer to induce stress in the layer. The substrate can include silicon. A plurality of columnar bodies (35) are formed in the groove (36) on the rear side of the main substrate or on the semiconductor wafer overlying the insulating layer.

Description

Strained semiconductor substrate and method for making the same

technical field

The present invention relates to integrated circuit substrates or wafers and methods of manufacturing such integrated circuit substrates or wafers. More particularly, the present invention relates to a method of forming a strained semiconductor structure on a substrate and a strained semiconductor structure or layer.

Background technique

Using the strained metal oxide semiconductor (SMOS) method to increase the performance of the transistor (MOSFET) by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current , frequency response (frequency response) and working speed. Strained silicon is typically formed by growing a silicon layer on a silicon germanium substrate or layer.

The silicon germanium lattice combined with the silicon germanium substrate is usually wider than the pure silicon grid, and the grid spacing is wider as the percentage of germanium is higher. Since the silicon grid is aligned with the silicon germanium grid with larger intervals, a tensile strain will be generated on the silicon layer. Essentially the silicon atoms are ripped apart from each other.

Solosil has a conductive energy band including six equal valence bands. Tensile strain applied to the silicon causes the energy of four electron valence bands to increase and the energy of the other two electron valence bands to decrease. Due to quantum effects, the effective estimated number of electrons decreases by thirty percent when passing through this lower energy band. Therefore, this lower energy band provides lower resistance to electron flow. In addition, electrons encountering lower vibrational energies from the nuclei of the silicon atoms cause electrons to diffuse at a rate 500 to 1000 times slower than in relaxed silicon. Accordingly, the carrier mobility in strained silicon increases more sharply than that in relaxed silicon, increasing electron mobility by 80 percent or more and holes by 20 percent. or higher mobility. Increased mobility has been found to consistently increase the electric field up to 1.5 million volts/cm. These factors are believed to result in a thirty-five percent increase in device speed without further reduction in device size, or a twenty-five percent reduction in power consumption without a reduction in performance.

Conventional semiconductor-on-insulator (SOI) substrates have included strained silicon layers formed on top of a buried oxide layer that formed on the base layer. The buried oxide layer can be formed by different processes including depositing oxygen on the base layer or doping the base layer with oxygen. The strained semiconductor layer can provide a silicon germanium layer having the composition (Si _{(1-x) Gex} ), where x is about 0.2, more generally in the range of 0.1 to 0.3. The SiGe layer can be deposited by chemical vapor deposition using silane and germane. The concentration of germane can be reduced when deposition begins such that the uppermost major portion of the silicon germanium layer is mostly or entirely silicon.

The use of germanium in the SMOS process can lead to germanium contamination of the integrated circuit substrate, layers and devices. In particular, outgassing or outdiffusion of germanium can contaminate various components associated with the fabrication equipment and integrated circuit structures associated with the processed wafer. Furthermore, the outgassing effect of germanium will adversely affect the formation of the film. Furthermore, the out-diffusion of germanium may cause germanium accumulation or accumulation at the interface of the liner, thereby causing reliability problems of the shallow trench isolation structure.

The problem of germanium outgassing is particularly pronounced in the very high temperature and HCI (hydrochloric acid) surroundings associated with the lining of the STI structure. For example, a conventional STILO process utilizes a temperature of about 1000 degrees Celsius thereby increasing germanium outgassing.

Therefore, there is a need for a strained semiconductor structure that can be formed without utilizing germanium. Second, there is also a need for a method for forming high-quality SMOS substrates. Furthermore, there is a need for a SMOS wafer formation method that does not require strained layer deposition. Additionally, there is a need for a substrate that is less susceptible to the outgassing effects of germanium. Additionally, there is a need for a novel method of forming strained semiconductor layers. Furthermore, there is a need for a wafer fabrication process that enhances and/or increases the lifetime of layer strain characteristics.

Contents of the invention

One of the following embodiments relates to a method of manufacturing an integrated circuit substrate. The integrated circuit substrate includes a strained layer. The method includes providing a base layer, providing an insulating layer on the base layer, and providing a semiconductor layer on the insulating layer. The method further includes forming a plurality of pillars in the base layer.

Another embodiment relates to a method of forming a strained semiconductor layer on the base layer. The method includes etching a trench in the base layer and providing a compressive material in the trench.

Yet another embodiment relates to a substrate. The substrate includes a strained layer and a base layer formed under the strained layer. The base layer has grooves on a side opposite to the strained layer. The trench reduces stress in the strained layer.

Description of drawings

A more complete understanding of these embodiments will be obtained from the foregoing detailed description accompanying the accompanying drawings, in which like reference numerals refer to like components, including:

1 is a schematic cross-sectional view of a portion of a substrate including a strained semiconductor layer, an oxide layer, and a base layer according to an embodiment;

Figure 2 is a cross-sectional view of the part shown in Figure 1 to illustrate the etching step;

Figure 3 is a cross-sectional view of the portion shown in Figure 2 to illustrate the deposition steps;

Figure 4 is a bottom view of the part shown in Figure 1;

5 is a schematic diagram of the bottom surface of another part of the substrate according to another embodiment of the present invention;

6 is a schematic bottom view of another part of a substrate according to another embodiment of the present invention;

Figure 7 is a basic flow diagram of the method used to manufacture the part shown in Figure 1; and

Figure 8 is a cross-sectional view of the portion shown in Figure 1 to show the mechanical compression system attached to the substrate.

Detailed ways

1 to 8 show substrates and methods for providing a strained semiconductor layer, such as a strained silicon layer. The structure and fabrication can be utilized without or with germanium doping.

Referring to FIG. 1, a portion 20 of an integrated circuit may be a portion of a wafer or a substrate such as a semiconductor-on-insulator substrate. The portion 20 may be formed in manufacturing method 100 (FIG. 7) and is preferably used for Applications in strained metal-oxide-semiconductor (SMOS).

Portion 20 includes a substrate consisting of strained layer 50 , buried oxide layer 40 and base layer 30 . Layer 50 may include germanium or be provided in a multilayer structure including germanium. Furthermore, a support substrate may be provided below this layer 30 .

In one embodiment, the base layer 30 is a single crystal silicon layer. The thickness of layer 30 may be between 400 and 1000 micrometers (μm). The buried oxide layer 40 may be a silicon dioxide layer. Layer 40 may have a thickness between 500 and 2000 Angstroms (A). The strained layer 50 is preferably silicon or silicon/germanium (where germanium can account for ten to thirty percent). Layer 50 may have a thickness of 500 Angstroms.

Layer 50 is preferably below tensile stress due to the fact that collection 32 of grooves 36 (shown in FIG. 2 ) includes material 34 having a compressive force. In one embodiment, set 32 of trenches 36 may be empty and have less tensile stress than in layer 50 due to the absence of material associated with the trenches. Preferably, the set 32 of trenches 36 can be filled with a compressive material 34, such as plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD) silicon nitride (SiN) material, metal, or other The material becomes compressed when or after being deposited in the set 32 of trenches 36 . If tensile stress is required in the trench 36, a thermally formed silicon nitride material or a low stress chemical vapor deposition (LPCVD) silicon nitride material may be used instead of the plasma enhanced chemical vapor deposition (LPCVD) silicon nitride material which would cause compressive stress.

The compressive stress on layer 30 is converted to tensile stress in layer 50 through layer 40 . Compression layer 30 of portion 20 has tensile layers 40 and 50 . In an alternative embodiment, layer 40 is absent and layer 50 is formed directly on layer 30 . In another embodiment, layer 30 may serve as the entire main substrate, and the upper surface of the main substrate is used as the active region. The upper surface is under tensile stress due to the compressive tension developed by the lower surface associated with the set 32 of grooves 36 .

In one embodiment, set 32 of trenches 36 corresponds to the size of the active area in layer 50 . In one embodiment, the same mask used to define the active area on layer 50 may be used to define set 32 of trenches 36 . Some grooves 36 may be larger than other grooves. For example, small trenches at specific locations are necessary to maintain the integrity of the overall wafer.

Compressive material 34 preferably extends about 700 Angstroms from the lower surface of layer 30 toward layer 40 . In one embodiment, set 32 of trenches 36 extends all the way to layer 40 (ie, trenches 36 reach the lower surface of layer 40). In another embodiment, trench 36 extends to a depth of seventy-five percent of layer 30 . Preferably, the trench 36 has a depth of 500 to 700 microns. Preferably, layer 40 , layer 50 , and layer 30 are present in portion 20 prior to formation of set 32 of trenches 36 .

Preferably, the trench 36 has a width of 500 to 2000 angstroms and a length of several micrometers (μm). The set 32 of grooves 36 has a tapered profile. For example, the trench 36 has a trapezoidal cross-sectional profile and the narrower portion is closer to the layer 40 . A collection 33 of pillars 35 is formed between the grooves 32 , and the pillars 35 preferably have a width slightly greater than the width of the grooves 36 . The columnar body 35 may have a length slightly longer than or equal to the length of the groove 36 .

Please refer to FIG. 7 together with FIG. 1 to FIG. 3 , the formation of the portion 20 is disclosed below. In FIG. 2, set 32 of trenches 36 are etched using a photolithographic process. A pad oxide and silicon nitride hard mask can be used to form the trench 36 .

Trenches 36 may be defined using an active layer photolithography mask. The area of the active layer photolithographic mask corresponding to the isolation trench on layer 50 corresponds to the portion of trench 36 on the backside of the integrated circuit wafer.

Trench 36 preferably selectively etches layer 30 (silicon) relative to the material of layer 40 (silicon dioxide) in a dry etch process. A set 32 of trenches 36 is etched in the rear side of layer 30 of the integrated circuit wafer. Additionally, the etch process can reach layer 40 and stop at layer 40 . Other alternative trench formation procedures may also be utilized to form trench 36 .

The formation of the collection 32 of trenches 36 leaves a collection 33 of columns 35 in the layer 30 . Columnar structures 35 are formed after layers 50 and 40 are formed on layer 30 . The material of the columnar structure 35 is preferably the same as that of the layer 30 (ie, silicon).

Referring to FIG. 3 , in step 104 of the method 100 , the compressive material 38 is filled in the trench 36 (shown in FIG. 2 ). Preferably, a material with compressive force, such as a material with compressive force including silicon nitride, is filled in the groove 36 and then shrinks to pull out the columnar body 35 oppositely connected to the groove 36 . The compressive material creates compressive stress in layer 40 and provides tensile stress to layers 40 and 50 thereon.

Material 38 may be a compressive material or a nitride material. In one embodiment, material 38 is a plasma enhanced chemical vapor deposition silicon nitride material.

Material 38 may be formed in a conformal layer deposition process such as plasma enhanced chemical vapor deposition or sputter deposition. Material 38 preferably has a thickness greater than or equal to 1/2 of trench 36 or 250 to 1000 Angstroms, or in a preferred embodiment is thicker. In the case of silicon nitride, the deposition parameters for material 38 are silane (SiH4) + ammonia using a pressure of 10 to 1000 milliTorr, an RF power of 10 to 1000 and a temperature of 100 to 500 degrees Celsius (NH3) + Nitrogen (N2). Preferably, the material 38 is naturally compressed after deposition.

Referring to FIG. 1 , material 38 (shown in FIG. 3 ) is planarized in step 106 of process 100 to leave material interposed between sets 33 of columnar structures 35 associated with sets 32 of trenches 36 34. Material 38 may be planarized in a chemical mechanical polishing process or other etching process.

Referring to FIG. 4 , the set 32 of grooves 36 may have a rectangular shape. According to another embodiment in FIG. 5 , trench 36 comprising material 34 has a square or rectangular shape with an aspect ratio relatively close to unity. In another embodiment, the pattern of the material 34 as provided in FIG. 6 is such that the sides of the layer 30 form an angle with the top surface.

In one embodiment, the collection of grooves 36 comprising material 34 exhibits a waffle pattern. As previously described in connection with FIG. 1 , set 32 of grooves 36 may include grooves of different sizes. Some trenches and pillars in layer 30 may be smaller or larger than other trenches and pillars according to design criteria. For example, integrated circuit wafers may require higher strength in certain portions of the wafer and smaller trenches in specific areas for integrity. Furthermore, the pattern shown in FIGS. 4-6 for the locations reserved for trenches 36 (material 34 ) will vary depending on the location of pillars 35 .

Referring to Fig. 8, a mechanical system is provided to part 20 for additional compressive stress. In this embodiment, trench 36 may be formed empty or filled with material 34 . System 38 may be a spring or clip. In one embodiment, system 58 is provided as part of an integrated circuit package and is used to enclose portion 20 .

In another embodiment, the material 38 can be a material with low thermal resistance to increase heat convection generated by the portion 20 . The low thermal resistance material may include silicon and/or metal.

It should be understood that the detailed diagrams, specific embodiments and specific numerical values disclosed to illustrate the embodiments of the present invention are only for illustration purposes. The pattern, shape and size of the trenches and column structures are not limited to specific aspects. The methods and apparatus of the invention are not limited to the precise details and conditions disclosed. Changes may be made in the details disclosed without departing from the spirit of the claims which follow the invention.

Claims (10)

1. A method of manufacturing an integrated circuit substrate comprising a strained layer, the method comprising: provide the base providing an insulating layer on the base layer; providing a semiconductor layer on the insulating layer; and A plurality of columnar bodies are formed in the base layer. 2. The method of claim 1, further comprising providing a compressive material in a hole associated with the column. 3. The method of claim 2, further comprising smoothing the compressive material until reaching the base layer. 4. The method of claim 1, 2 or 3, wherein the pillars have a width between 2000 and 3000 angstroms. 5. The method of claim 1, 2 or 3, wherein the compressive material comprises nitride. 6. A substrate comprising: strained layer; and A base layer below the strained layer and on a side opposite the strained layer has a groove that induces stress in the strained layer. 7. The substrate of claim 6, wherein the strained layer is strained silicon. 8. The substrate according to claim 6 or 7, further comprising a compressive material in the trench. 9. The substrate of claim 6 or 8, further comprising a buried oxide layer between the base layer and the strained layer. 10. An alternative method comprising a strained semiconductor layer on a base layer, the substrate being fabricated by a method comprising: etching trenches in the base layer; and A compressive material is provided in the groove.

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