CN1883117A - Method for performing dual phase pulse modulation - Google Patents

Abstract

A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses (Fig. 2B) whose widths represent groups of M data bits (00, 01, 10, 11), with both the high and low pulses representing successive M-bit groups. Each of the 2<M> possible data values for a group of M data bits uniquely corresponds to one of 2<M> distinct pulse widths (e.g., 4, 6, 8 and 10 ns). This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.

Description

Method for performing biphase pulse modulation

technical field

The present invention relates to digital data modulation for signal transmission and corresponding demodulation of received signals to recover the digital data transmitted thereby, and in particular to specific types of modulation used to encode data, such as pulse duration (width) modulation (PDM or PWM), on/off keying, non-return-to-zero (NRZ) schemes, differential phase-shift keying (DPSK), multi-frequency shift keying (MFSK), and various forms of multi-bit/N-ary encoding.

Background technique

Different types of communication signals are often distinguished according to certain basic characteristics, such as whether the signal carrier is amplitude modulated, angle modulated, pulse modulated, or some combination of these modulation types. In a pulse modulated signal, the pulses may likewise be modulated in amplitude, duration (width), position (phase), repetition rate (spacing), or any combination thereof. There may be analog, quantized or digital information of a single or multi-channel modulated carrier, and the multiplexed information may be in various forms. Information may represent audio sounds, video images, measurements, alphanumeric characters and symbols, other kinds of data, or combinations thereof.

Pulse duration modulation (PDM) (also known as pulse width modulation) is the modulation of a pulse carrier in which the value of the information signal modulating the carrier produces a proportional duration of pulse. Typically in PDM, the pulse spacing or interval is kept constant. Pulse pitch (or spacing) modulation is a form of frequency modulation in which the spacing or spacing between pulses is modulated according to an information value. Typically, the pulse duration or width is held constant in this modulation. Pulse position modulation (PPM) is the phase modulation of a pulse carrier in which the information value changes the time position of the pulse relative to the time at which the modulation does not occur. This differs from pulse-space modulation in that PPM typically requires a reference clock pulse to accurately determine the relative phase or position of the pulses.

"Keying" is any form of digital modulation in which a signal is formed by modulating any characteristic of a carrier between discrete values. On/off keying is a binary form of amplitude shift keying with two separate states, one in which energy is present during the keying interval and one in which energy is not present. Information can be represented by the duration of one of the states (eg dots and dashes in Morse code telecommunications). Often, however, the amplitude states themselves or transitions from one state to another represent encoded information. There are various possible encoding schemes (eg, unipolar, polar, bipolar, return to zero, normal to one, non-return to zero). For example, non-return-to-zero (NRZ) is a modulation mode that does not necessarily return the signal to zero after encoding each data element in the signal, while return-to-zero and normalize is a modulation mode that returns the signal to zero (or normalizes) after encoding each data element .

Frequency Shift Keying (FSK) is a form of frequency modulation in which the modulated output signal is shifted between two or more separate predetermined frequencies according to the value of the information. In Multiple Frequency Shift Keying (MFSK), groups of n data bits are encoded by 2 ⁿ separate frequencies. Phase Shift Keying (PSK) is a form of phase modulation in which the modulation information shifts the instantaneous phase of the modulated signal between predetermined discrete phase values. Differential Phase Shift Keying (DPSK) is a form of PSK in which the reference phase for a given keying interval is the phase of the signal during the previous keying interval. FSK and PSK modulation generally involve a continuous wave carrier rather than pulses.

Multi-bit or N-ary (ternary, quaternary, octal, etc.) encoding schemes have modulated signals where each signal condition (amplitude, frequency, phase) represents more than one bit of information. MFSK is an example, but PSK or DPSK can equally have more than two separate phases, eg 4 phases representing a two-bit binary number.

Each form of modulation has its own advantages and disadvantages relative to its particular application. Factors to consider when choosing a particular form of modulation include: bandwidth, power requirements, and the likelihood of signal transmission errors and recovery of the original information. For digital data, it may be important whether a separate clock signal is required or the modulated signal is self-synchronizing. The relative simplicity or complexity of the modulation and demodulation equipment or circuits is also a determining factor. Capacitively loaded transmission lines are especially sought for low power consumption.

Contents of the invention

The present invention (hereafter referred to as Dual Phase Modulation (DPPM)) is a method of encoding data into a series of high and low pulses, the width of which represents an M-bit symbol. Each of the ^2M possible data values for a symbol (a set of M data bits transmitted as a single unit) corresponds to one of ^2M different pulse widths. A sequence of N bits can be divided into approximately P=N/M symbols, where M is the symbol size in bits. High signal pulses and low signal pulses represent consecutive symbols, respectively. Therefore, P symbols can be sent in P/2 pulse periods (high pulse and low pulse). If a return-to-zero scheme is desired, the number of symbols P is preferably an odd number for simplicity of implementation. Encoding involves converting data into signal pulses, while decoding involves converting a series of signal pulses back into an ordered sequence of data bits.

DPPM is originally irregular. Data is decoded by detecting the width of the pulse relative to the last transition. This means that the clock pulses do not need to be sent with the data, nor do the clock pulses have to be encoded or recovered from the data. However, the start of the sequence of M symbols can be started to coincide with a clock pulse, facilitating clock recovery when required.

DPPM reduces power consumption by reducing the number of transitions when transferring data at high speeds on capacitively loaded transmission lines. Because the positive-going transition consumes most of the power charging the capacitive load (and some additional internal/crossover energy during the positive-going and negative-going transitions), using high and low pulses to transmit data saves electricity. Likewise, DPPM encodes multiple bits with each high or low pulse, sending more data per transition than traditional pulse-width modulation systems.

DPPM also benefits from not requiring synchronized clocks or "long" clock recovery cycles. Other phase modulation schemes require synchronous clock pulses to be sent or recovered from the data. In implementations where short data pulses are sent intermittently, significant power savings can be achieved because no clock pulses need to be sent or recovered.

Description of drawings

1 is a diagram (signal value versus time) of a set of DPPM pulses of various pulse durations used to represent a corresponding set of binary data symbols in accordance with the present invention.

2A and 2B are diagrams of a DPPM pulse sequence according to the present invention for an example set of data showing the delivery of a set of 9 high and low pulses in a single 100 ns system clock cycle.

3 and 4 are schematic circuit diagrams of various DPPM encoder and decoder circuits for implementing the DPPM method of the present invention.

Detailed ways

DPPM is a method of encoding data residing in a digital circuit in the form of binary circuit states (1s and 0s) into a train of alternating high and low signal pulses, the individual durations or widths of which represent 2 bit (or more) of data. The example embodiment shown in Figure 1 is coded with 2 bits. Encode bit pairs with a set of different pulse widths representing each possible 2-bit binary digit value, for example:

00＝4ns pulse

01＝6ns pulse

10＝8ns pulse

11 = 10ns pulse

If the decoding circuit at the receiving end of DPPM signal transmission can correctly distinguish different pulse widths, the selection of 4, 6, 8 and 10ns pulse widths is arbitrary and can also be 4, 5, 6 and 7ns or some other Pulse Width. The decoding circuitry (and process variations, noise and signal attenuation, and temperature/voltage variations in the propagation environment) also establish a practical limit to the number of bits that can be encoded per pulse, with 3 bits per pulse requiring 8 (= 2 ³ ) possible 16 (=2 ⁴ ) possible pulse widths need to be correctly analyzed for each pulse width of 4 bits. The data rate can be considered as the number of encoded bits per second (or the number of symbols per second), which depends on the number of pulses per system clock cycle and the system clock frequency.

"Biphasic" refers to the fact that information is sent as pulses that go high and pulses that go low. Most pulse width modulation schemes simply vary the width of the going high pulses, thus actually modulating the duty cycle. DPPM independently modulates the width of the going high and low pulses, encoding different groups of bits in the high and low portions of each "cycle". Therefore, clock period and duty cycle are not valid concepts for the resulting pulse train. DPPM itself is "untimed", meaning that data can be decoded by simply detecting the width of the pulses relative to each transition. This means that the clock pulses do not have to be sent with the data, nor does it have to encode the clock pulses and recover the clock pulses from the data. This is a major advantage when transferring time-critical pulses between different chips because it does not have to operate clocks that introduce timing variations and errors. The only clock consideration is the fact that several pulse "cycles" will be sent in each system clock cycle. For example, Figures 2a and 2b show a DPPM with alternating high and low pulses (5 high pulses and 4 low pulses) delivering 18 bits (here encoded as 9 binary digits) of data within one 100 ns system clock cycle Examples of pulse trains. These 18 bits can form, for example, a 16-bit data word with two error correction code bits appended to the word. Therefore, one data word can be transferred per system clock cycle.

Because information is sent on both positive and negative phases of the pulse train, DPPM is inherently a non-return-to-zero (or non-return-to-unity) modulation scheme. However, it is generally desired that the pulse sequences contained in a system clock cycle be zeroed (or normalized) at the end of each such sequence. This hope is easy to implement when the number of multi-bit symbols to be represented as pulses in a word is odd, as in the example of Figures 2a and 2b, since the last symbol in a row or column requires zeroing (or normalization) As the tail conversion of the last pulse. However, this rule does not have to be followed if the encoder inserts extra pulses that are omitted by the decoder to force a return.

Therefore, the DPPM method represents a group of M data bits such as a two-bit binary number (M=2) as a signal pulse of a specified width. Each of the ^2M possible data values corresponds to one of ^2M different pulse widths, and consecutive groups of M data bits are represented by alternating high and low signal pulses. Signal encoding and decoding circuits perform conversion between data bits and signal pulse representations of information content.

To encode data bits into signal pulses, a received data word is first divided into an ordered sequence of groups of M data bits, and then each group in the sequence is converted into its corresponding signal pulse representation, resulting in a train of representations The data high and low signal pulses. One way to convert data words into signal pulses is to specify signal pulse transition times, each corresponding to the previous transition time incremented by the specified pulse width corresponding to the current group of M data bits, and then, after those specified The transition time of the generated signal pulse transitions. The example encoder hardware described below with reference to FIG. 3 performs conversion in this way.

To decode the DPPM signal back to data, the pulse width of each of the high and low signal pulses is determined, which is then converted back into an ordered sequence of groups of M data bits, and reassembled into a data word. One method of performing this transition is performed by the example decoder hardware described below with reference to FIG. 4 .

Example encoder and decoder hardware implementing the DPPM approach is as follows:

Referring to Figure 3, an example DPPM encoder circuit receives a data word (18 bits divided into 9 two-bit binary numbers) on a parallel data input bus 11 (here divided into two parts 11A and 11B). A load signal (not shown) indicates when data is available. If no data is available, the DPPM encoder remains idle. Sys_Clock 12 is also the system clock generated externally to the DPPM encoder.

The circuit takes received data on odd and even buses 11A and 11B synchronously with the system clock and loads it into parallel-in, serial-out shift registers 13A and 13B. The odd bits (ie, bits 1, 3, 5, 7, 9, 11, 13, 15 and 17) are loaded from the bus 11A into another shift register 13A (odd shift register). Even bits (ie 0, 2, 4, 6, 8, 10, 12, 14 and 16 bits) are loaded from bus 11B into a shift register 13B (even shift register).

The contents of the registers are then sequentially shifted out in pair 15A and 15B. The shift clock pulse fed from the multiplexer output 29 ensures that the data sequentially shifted out of registers 13A and 13B is synchronized with the end of each DPPM signal pulse. In this way, the data word is divided into an ordered sequence of groups of M (where M=2) data bits each. If the data is divided into groups of three or four bits each, the input bus 11 will typically be divided into three or four sections loaded into three or four shift registers, each in its serial One bit of each group of bits is provided on the output.

Register outputs 15A and 15B are connected to input 17 of a state machine 19 whose N-bit output 21 is a function of its current value and the 2-bit pair to be encoded. In particular, state machine 19 repeatedly increments its state by an amount corresponding to the pulse width of consecutive 2-bit pairs received at state machine input 17 . The N-bit output 21 has only one valid bit and is used as an input 23 to control a multiplexer 25 for selecting successive branches from a current-controlled delay chain 27 . A multiplexer 29 is used to synchronize the flip-flop 31, thereby encoding the data on its output 33 into a series of high and low pulses, the width of the pulses representing the value of the 2-bit pair.

Edge detector circuit 14 (which may be any known edge detector) issues a start pulse of 2-3 ns width on each rising edge of the system clock (Sys_Clock). The start pulse resets the state machine 19 to the first tap select state (tap_select[44:1]=0 and tap_select[0]=1). The start pulse also sets the toggle flip-flop 31 to its 'set' state (output high). A 1 ns pulse synchronous to the system clock is presented on input 12 at the start of the 92 element delay chain 27 . First delay unit 26 , shown separately, takes into account the time it takes to load shift registers 13A and 13B and presents the first pair of data bits to state machine 19 .

Each unit in the delay chain 27 is calibrated to have a delay of 1 ns. Therefore, the pulse takes 92ns to pass through the delay chain. Assuming that the first DPPM signal transition occurs with a time delay of 2 ns (corresponding to tap_select[0]), when using the set of pulse widths described with reference to Figure 1, the size of the delay chain corresponds to representing an entire 18-bit word as a succession of DPPM signals The maximum total time required for a pulse, i.e. a duration of 90ns is required to transmit 9 "11" bit pairs as 9 high and low signal pulses of 10ns pulse width. If other word sizes and pulse widths are selected, the number of delay cells and even the amount of time delay for each element may change accordingly. When all pulses have the maximum pulse width, the period of the system clock must exceed the total duration of the signal pulse train. If the delay chain is calibrated to the system clock with a delay-locked loop (DLL), the pulse width will be automatically matched to a different system clock.

The least significant bit in the two shift registers 13A and 13B represents the current bit pair to be encoded and is input on line 17 to branch selector state machine 19 . State machine 19 selects branch points for delay chain 27 of 92 elements. The pulse width can be 4, 6, 8 or 10 ns for the four possible bit pairs, in which case the valid branch points are only on even delay elements, so there are 46 valid branch points in this embodiment. (However, the choice of pulse width is arbitrary, and another set of pulse widths could be chosen. The choice of pulse width is based on providing enough separation for the decoder to accurately distinguish them. "Sufficient" is defined by factors including process variation, switching speed and setup/hold requirements, such as the desired noise/error margin, the amount of noise in the system, and the characteristics of the technology used to implement the system.)

Branch point selection is incremented by 21 based on the current branch point (STATE(i)) and the next 2-bit data to be encoded (DATA[1:0]). The branch point selection preferably constitutes a single-step state machine 19 (actually a shift register capable of multiple shifts per cycle) in which a single active state is incremented every clock according to the 2-bit data value input from data line 17 2, 3, 4 or 5 positions. Although each state requires registers to be area-inefficient, this implementation allows very fast switching of states, allowing fast control of the multiplexer 25 . There is a one-to-one correspondence between the branch selection 21 (output from the state machine 19 ) and the delay chain branches T2 - T92 selected by the multiplexer 25 . Timing is such that the branch point must increment to the next value before the rising edge propagates through the delay chain to the next branch point.

The branch point selection 21 is a selector control 23 for a multiplexer 25 . The output 29 of the multiplexer 25 is a 1 ns pulse occurring once at each selected branch point. This multiplexer output 29 clocks toggle flip flop 31 and also forms the shift clock pulses that shift data in shift registers 13A and 13B and clock state machine 19 from one state to the next. The output 33 of the flip-flop 31 is the DPPM output of the entire encoder circuit in FIG. 3 .

Referring to FIG. 4 , an example DPRM decoder circuit processes the serial DPPM signal received on input 43 to obtain a parallel data output from output register 78 . Sys_Clock is the system clock generated outside the DPPM decoder. Deskew blocks 45 and 46 allow independent delay trimming of the DPPM signal used to clock D flip-flops 51A-51D and 52A-52D and provide data sampled by those same flip-flops. The amount of de-skewing can be controlled, for example, by tuning the registers of the Venier circuits in each of blocks 45 and 46 . High and low pulses are decoded separately. Inverter 48 coupled to DPPM signal input 43 via deskew blocks 45 and 46 inverts the DPPM signal pulses so that substantially the same subcircuitry can be used to decode high and low pulses, as described below.

Typically, the value of the data is determined by detecting the pulse width relative to the leading edge of each pulse. A modulated signal representing this data is passed through a short delay chain, and the output is used to time and sample the non-delayed signal. As a result, decoding does not require an independent or unrecovered clock. More specifically, the serial-parallel DPPM data decoder includes two delay chains 49 and 50, each having k-1 outputs representing different stages of the delay chain, where k is the number of different delay values representing encoded data. For 2-bit encoding, k=4 (for 3-bit encoding, k=8, etc.).

Returning to Figure 1, for an implementation using 2-bit encoding, data can be represented as, for example, 4, 6, 8 and 10 ns pulse widths. By sampling the pulse at times T5, T7 and T9 between the various possible trailing porch times for different encoded pulse width values, the width of the pulse can be determined and then decoded back into its constituent pairs of data bits. Thus, at time T5 (i.e., 5 ns after the leading edge of the pulse), the 4 ns pulse encoding the 2-bit binary data value of 00 will have ended, while the pulses encoding the other 2-bit binary data values will have not yet transitioned to opposite signals on their trailing edges state. Likewise, at time T7, the 6 ns pulse of encoded data value 01 will have ended, then at time T9, the 8 ns pulse of encoded data value 10 will have ended, but the 10 ns pulse of encoded data value 11 will still last another nanosecond .

As shown in FIG. 4, the rising edge of the data pulse is sent through the first delay chain 49 and occurs at T5, T7 and T9 for timing a set of flip-flops 51B-51D to sample the data pulse presented on line 55. For the going low pulse, the incoming DPPM signal is first inverted and then sent through a second delay chain used with another set of flip-flops 52B-52D to sample the inverted data pulse presented on line 56 . Thus high and low pulses are decoded independently. Also, by using two delay chains and an inverted low pulse before sampling, it is possible to decode the DPPM signal with only the rising edge passed through the delay chains. This yields the added advantage of avoiding spreading of the rising/falling data pulses in the delay chain.

Logic AND gates 63-66 convert the sample pulse values output from flip-flops 51B-51D and 52B-52D on lines 57B-57D and 58B-58D into their corresponding data values.

It can be seen that the DPPM method allows the pulse width to be decoded relative to the leading edge of the pulse and thus does not require a clock. This means that no additional clock lines, clock encoding or clock recovery circuitry are required at the receiver. In fact, because the delayed version of the data pulse is actually used to time (or sample) the incoming non-delayed data pulse, this decoding technique has the added advantage of eliminating the possibility of introducing errors when manipulating or recovering the clock.

Claims (8)

1. A dual phase modulation (DPPM) method comprising: Represent groups of M data bits residing in a digital circuit in the form of circuit states as transmitted high and low signal pulses of specified width, each of the 2 ^M data values possible for the M data bits corresponds to 2 one of ^M different pulse widths, successive groups of M data bits are represented by alternating high and low signal pulses; and Convert between data bits and signal pulse representations by using a signal encoder or decoder circuit. 2. DPPM method as claimed in claim 1 is characterized in that, described conversion comprises between data bit and signal pulse representation: Data is encoded into a DPPM signal by using a signal encoder circuit to convert groups of data bits into a series of corresponding signal pulses representing the groups of data bits. 3. DPPM method as claimed in claim 2 is characterized in that, described encoding comprises: (a) receiving the data word into the signal encoder circuit; (b) dividing the received data word into an ordered sequence of groups of M data bits; (c) converting each group of M data bits into a series of signal pulses having a specified width, each width corresponding to one of the M groups of data bits; and (d) outputting the train of signal pulses from the signal encoder circuit. 4. DPPM method as claimed in claim 3 is characterized in that, described conversion step (c) comprises designation signal pulse conversion time, and signal pulse conversion time corresponds to the designated pulse width corresponding to the current group of M data bits Incrementing the previous transition time, then generating a signal pulse transition at said specified signal pulse transition time, and repeating the transition time increment and transition generation for each successive group of M data bits. 5. DPPM method as claimed in claim 1 is characterized in that, the conversion between described data bit and signal pulse representation comprises: The DPPM signal is decoded into digital data by using a signal decoder circuit to convert a series of signal pulses into their corresponding groups of data bits. 6. DPPM method as claimed in claim 5 is characterized in that, described decoding comprises: (a) receiving a series of alternating high and low signal pulses into the signal decoder circuit; (b) determining the pulse width of each signal pulse; (c) converting said train of signal pulses into an ordered sequence of sets of M data bits whose data values correspond to the specified pulse width of the signal pulses; and (d) Combine consecutive groups of M data bits into a data word. 7. DPPM method as claimed in claim 6 is characterized in that, described decoding also comprises: (a) after receiving a string, direct the string to the in-phase and anti-phase paths such that high signal pulses are decoded from the in-phase path and low signal pulses are decoded from the anti-phase path, and (b) The conversion of the signal pulse train includes independently converting the high signal pulse from the in-phase path and the low signal pulse from the anti-phase path into two ordered sequences of groups of data bits representing the decoded high pulse and Decoded low pulse. 8. The DPPM method according to claim 1, characterized in that, the group of M data bits is a two-bit binary number (M=2) represented by 4 signal pulses with different pulse widths.

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