CN1881858B - A Chip-Level Realization Method for Synchronous Channel Transmission of Wideband Code Division Multiple Access System - Google Patents

Abstract

The present invention proposes a chip-level implementation method for synchronous channel transmission of wideband code division multiple access system. First, the primary synchronous channel transmission sequence C _pNew and the secondary synchronous channel transmission sequence C _sNew ^i,k are obtained. Then complete the mapping of the primary sync channel transmission sequence C _pNew and the secondary sync channel transmission sequence C _sNew ^i,k . Then complete the spreading, scrambling and weighting processing of the synchronization channel according to the processing process of other downlink physical channels. By adopting the method of the present invention, other downlink physical channel sending chip-level processing resources are used to complete the synchronous channel sending chip-level processing, thereby improving resource utilization and resource utilization in the downlink physical channel sending ASIC of the baseband processor of the WCDMA system base station integration and reduce single-channel cost.

Description

A Chip-Level Realization Method for Synchronous Channel Transmission of Wideband Code Division Multiple Access System

technical field

The invention relates to the field of baseband processors of wideband code division multiple access (WCDMA) base stations, in particular to a method for realizing synchronous channel transmission chip-level processing.

Background technique

The synchronization channel is a downlink physical channel necessary to support cell search in a wideband code division multiple access system, and includes two sub-channels: a primary synchronization channel (P-SCH) and a secondary synchronization channel (S-SCH). The third generation partnership (3GPP) stipulates that the transmission frame structure of the synchronization channel is 10 milliseconds per frame, each frame includes 15 time slots, each time slot is 2560 chips (chip), and the chip rate is 3.84 MHz. Each time slot number in a frame starts from the first time slot number 0, and each time slot number is 1 greater than the previous time slot number, until the last time slot number is 14. 3GPP specifies the primary synchronization channel and secondary synchronization channel There is data transmission only in the first 256 chips of each time slot, and the symbol sequence sent by the first 256 chips of each time slot of the main synchronization channel is sequence ac _p , and the auxiliary synchronization channel is in the time slot number k The symbol sequence transmitted in the first 256 chips of the slot is the sequence ac _s ^{i, k} , where: c _p , c _s ^{i, k} are specific non-zero values with a length of 256 chips specified by 3GPP and real and imaginary parts Equal complex sequence; a is a real number, the value is +1 or -1; i is the primary scrambling code group number of the sector where the auxiliary synchronization channel of the transmission sequence c _s ^i,k is located, and can be 0, 1,..., One of 64 integers such as 63; k is the time slot number of the synchronization channel time slot where the auxiliary synchronization channel is located when the sequence ac _s ^{i, k} is sent, and can be 0, 1, ..., 14 and other 15 integers one.

The main synchronization channel transmission sequence ac _p and the auxiliary synchronization channel transmission sequence ac _s ^{i, k} are sequences of the chip rate. According to the 3GPP regulations, the chip-level implementation method of the main synchronization channel and the auxiliary synchronization channel is as follows:

First, obtain the real number a, the primary scrambling code group number i of the sector where the secondary synchronization channel is located, and the value of the synchronization channel time slot number k, and generate the primary synchronization channel sequence ac _p and the secondary synchronization channel sequence ac _s ^i,k .

Then in the first 256 chips of the main sync channel time slot with the time slot number k, each chip will be the main sync channel sequence ac _p corresponding to the I, Q path of the sequence value of the chip with the weighting of the main sync channel respectively The factors are multiplied to obtain the I and Q chip-level weighted data of the primary synchronization channel of the chip respectively. At the same time, in the first 256 chips of the auxiliary synchronization channel time slot whose time slot number is k, each chip will use the auxiliary synchronization channel sequence ac _s ^{i, k} corresponding to the I and Q paths of the sequence value of the chip to be the same as the auxiliary synchronization channel respectively. The weighting factors of the channels are multiplied to obtain the I and Q chip-level weighted data of the chip-assisted synchronization channel respectively.

Then add the I chip-level weighted data of the main sync channel obtained and the I chip-level weighted data of the auxiliary sync channel to obtain the I chip-level weighted data of the sync channel; The Q chip-level weighted data and the Q chip-level weighted data of the auxiliary synchronization channel are added to obtain the Q chip-level weighted data of the synchronization channel.

Finally, the I and Q chip-level weighted data of the synchronization channel are respectively added to the I and Q chip-level weighted data of the same chip of other downlink physical channels to obtain the I and Q chip-level weights of all downlink physical channels For data, the chip-level processing of I and Q channels of all downlink physical channels is completed.

According to 3GPP, the chip-level processing method for sending downlink physical channels other than the synchronization channel is as follows: firstly, the symbol-level data of the downlink physical channel is serial-to-parallel converted and mapped into I and Q two-way data, and then mapped to get The I, Q two-way data of the channel are respectively multiplied by the spreading code sequence of the channel to obtain the channel chip-level I, Q two-way data; then the channel chip-level I, Q two-way data are taken as the real part according to the I way, The channel is used as the rule of the imaginary part to form a channel chip-level complex data, and then the obtained channel chip-level complex data is multiplied by the channel scrambling code sequence and the channel weighting factor in turn to obtain the I and Q channel chip-level weights of the channel data.

In the baseband processor design of the base station of the WCDMA system, when implementing the chip-level processing of the downlink physical channel transmission, if it is completely implemented in accordance with the method specified by 3GPP, because the chip-level processing of the synchronization channel transmission and the chip-level processing of other downlink physical channels The methods are different and each requires independent processing resources. In multi-channel integration, the resources required for chip-level processing of other downlink physical channels except the synchronization channel are the same. In the baseband processor of the WCDMA system base station, the downlink physical channel transmission ASIC can be used to increase the operating frequency of processing resources. In this way, the same processing resource is time-division multiplexed to complete the chip-level processing of multiple downlink physical channels. The processing resources needed to complete the chip-level processing of the synchronization channel transmission are different from other downlink physical channels. The baseband processor of the WCDMA system base station must use processing resources to complete the processing of the synchronization channel in the ASIC for downlink physical channel transmission. A sector of a WCDMA system base station only needs one primary synchronization channel and one auxiliary synchronization channel. Different sectors have different relative delays, so that each sector needs its own synchronization channel processing resources. Therefore, the synchronization channel transmits chip-level processing resources. The utilization rate is low, resulting in a great waste of resources.

Contents of the invention

The purpose of the present invention is to overcome the disadvantages of low resource reuse rate and waste caused by the low resource reuse rate and waste caused by the chip-level processing of synchronous channel transmission in the ASIC for transmitting the downlink physical channel of the baseband processor of the WCDMA system base station, and propose a synchronous channel transmission chip The level implementation method enables the transmission chip level processing of the synchronization channel to be completed by using other downlink physical channel transmission chip level processing resources.

A method for implementing chip-level transmission of a wideband code division multiple access system synchronous channel transmission chip level proposed by the present invention, comprising

Step 1. Obtain the transmission sequence C _pNew of the primary synchronization channel and the transmission sequence C _sNew ^{i, k} of the secondary synchronization channel: the primary synchronization channel only transmits ac _p in the first 256 chips of each time slot, and realizes that the sequence C is uniformly transmitted in each time slot _pNew , the sequence C _pNew has a length of 2560 chips, and its first 256 chip values are the 256 values of ac _p , and the sequence values of other chips are complex numbers (0+0j); the auxiliary synchronization channel is only in the front of each time slot Sending ac _s ^{i, k} with 256 chips is realized by sending the sequence C _sNew ^{i, k evenly in the synchronous channel time slot with the time slot number k} , the length of the sequence C _sNew ^{i, k} is 2560 chips, and the value of the first 256 chips 256 values of ac _s ^{i and k} in turn, and the sequence values of other chips are complex numbers (0+0j);

Among them ^, c _p , c _s ^{i, k} are all _complex number sequences with a specific non-zero value of 256 chips in length and the real and imaginary parts are equal; The scrambling code group number can be one of 64 integers such as 0, 1, ..., 63; k is the time slot number of the synchronization channel time slot where the auxiliary synchronization channel is located when the sequence ac _s ^{i, k} is sent, and can be 0 , 1,..., 14 and other 15 integers, a is a real number, the value is +1 or -1;

Step 2, C _pNew and C _sNew ^{i, k} are respectively mapped to obtain the I and Q road data of the main synchronization channel and the auxiliary synchronization channel, and the Q road data of the main synchronization channel after mapping and the auxiliary synchronization channel are all zero, and the I road is respectively is the real part of sequence C _pNew and sequence C _sNew ^{i, k} ;

Step 3, obtaining the synchronization channel spreading code sequence as a sequence of all 1s, and completing the spreading process;

Step 4, select the synchronization channel scrambling code sequence as a full (1+j) sequence, and complete the scrambling process;

Step 5, completing the weighting of the primary synchronization channel and simultaneously completing the weighting of the secondary synchronization channel;

Step 6: The chip-level processing of the synchronous channel transmission is completed, and the weighted data of the I and Q channels of the synchronous channel are output.

The synchronization channel transmission chip-level implementation method provided by the present invention, like other downlink physical channel transmission chip-level processing, has undergone processing steps such as mapping, spectrum spreading, scrambling, and weighting, so that other downlink physical channel transmission codes can be used. Chip-level processing resources complete the chip-level processing of synchronization channel transmission. In the baseband processor of the WCDMA system base station in the downlink physical channel transmission ASIC, no independent resources are needed to process the synchronization channel, thereby improving the downlink performance of the baseband processor of the WCDMA system base station. The physical channel transmits resource utilization in ASICs, improves integration, and reduces single-channel costs. At the same time, because the application range of channel processing resources has been expanded, the configurable flexibility of channel processing resources in ASICs has been increased.

Description of drawings

FIG. 1 is a flow chart of a chip-level processing method for transmitting a synchronization channel provided by the present invention.

Detailed ways

FIG. 1 shows a flow chart of chip-level processing for sending a synchronization channel provided by the present invention. The chip-level processing method for transmitting the synchronization channel provided by the present invention will be described in detail below in conjunction with this figure.

First obtain the primary synchronization channel transmission sequence C _pNew and the auxiliary synchronization channel transmission sequence C _sNew ^{i, k} : the primary synchronization channel only transmits ac _p in the first 256 chips of each time slot, and realizes that the sequence C _pNew is uniformly transmitted in each time slot, The sequence C _pNew has a length of 2560 chips, and its first 256 chip values are the 256 values of ac _p , and the sequence values of other chips are complex numbers (0+0j); the auxiliary synchronization channel is only in the first 256 codes of each time slot Slice transmission ac _s ^{i, k} is realized as sending sequence C _sNew ^{i, k in the synchronous channel time slot k with time slot number k} , the length of sequence C _sNew ^{i, k} is 2560 chips, and the value of the first 256 chips is sequentially ac _s ^{i, 256 values of k} , and the sequence values of other chips are complex numbers (0+0j). These two sequences can be generated within the ASIC or provided from outside the ASIC.

Then C _pNew and C _sNew ^{i, k} are respectively mapped to obtain I and Q channel data of the primary synchronization channel and the secondary synchronization channel. The I-way data of the main sync channel is the real part of _CpNew , the I-way data of the auxiliary sync channel is _CsNew ^{i, the real part of k} , the Q-way data of the main sync channel and the Q-way data of the auxiliary sync channel are both 0.

Then complete the spread spectrum processing of the synchronization channel. Select the synchronization channel spreading code sequence as all 1 sequences, and multiply the I and Q two-way data of the main synchronization channel obtained by mapping with the synchronization channel spreading code sequence respectively, and obtain the chip-level I and Q two-way data of the main synchronization channel ; Multiply the I and Q two-way data of the auxiliary synchronization channel obtained by mapping with the synchronization channel spreading code sequence to obtain the auxiliary synchronization channel chip-level I and Q two-way data.

Then, the scrambling processing of the synchronization channel is completed. Selecting the synchronization channel scrambling code sequence as a full (1+j) sequence, the obtained main synchronization channel chip level I, Q two-way data and the auxiliary synchronization channel chip level I, Q two-way data, according to the I way as the real part , the Q channel is used as the rule of the imaginary part to form the chip-level complex data of the primary synchronization channel and the chip-level complex data of the auxiliary synchronization channel respectively, and multiply them with the scrambling code sequence of the synchronization channel respectively to obtain the scrambled data of the primary synchronization channel and the auxiliary synchronization channel Synchronous channel scrambled data.

Finally, the obtained primary sync channel scrambled data and the secondary sync channel scrambled data are multiplied with respective weighting factors respectively, and the real part of the product result of the primary sync channel is used as the I-way chip-level weighted data of the primary sync channel, The imaginary part is used as the chip-level weighted data of the Q channel of the main synchronization channel; the real part of the product result of the auxiliary synchronization channel is used as the chip-level weighted data of the I channel of the auxiliary synchronization channel, and the imaginary part is used as the chip-level weighted data of the Q channel of the auxiliary synchronization channel data. So far, the synchronization channel transmission chip-level processing ends.

Claims (6)

1. A wideband code division multiple access system synchronous channel transmission chip level implementation method, comprising Step 1. Obtain the transmission sequence C _pNew of the primary synchronization channel and the transmission sequence C _sNew ^{i, k} of the secondary synchronization channel: the primary synchronization channel only transmits ac _p in the first 256 chips of each time slot, and realizes that the sequence C is uniformly transmitted in each time slot _pNew , the sequence C _pNew has a length of 2560 chips, and its first 256 chip values are the 256 values of ac _p , and the sequence values of other chips are complex numbers (0+0j); the auxiliary synchronization channel is only in the front of each time slot Sending ac _s ^{i, k} with 256 chips is realized by sending the sequence C _sNew ^{i, k evenly in the synchronous channel time slot with the time slot number k} , the length of the sequence C _sNew ^{i, k} is 2560 chips, and the value of the first 256 chips 256 values of ac _s ^{i and k} in turn, and the sequence values of other chips are complex numbers (0+0j); Among them ^, c _p , c _s ^{i, k} are all _complex number sequences with a specific non-zero value of 256 chips in length and the real and imaginary parts are equal; The scrambling code group number can be one of 64 integers such as 0, 1, ..., 63; k is the time slot number of the synchronization channel time slot where the auxiliary synchronization channel is located when the sequence ac _s ^{i, k} is sent, and can be 0 , 1,..., 14 and other 15 integers, a is a real number, the value is +1 or -1; Step 2, C _pNew and C _sNew ^{i, k} are respectively mapped to obtain the I and Q road data of the main synchronization channel and the auxiliary synchronization channel, and the Q road data of the main synchronization channel after mapping and the auxiliary synchronization channel are all zero, and the I road is respectively is the real part of sequence C _pNew and sequence C _sNew ^{i, k} ; Step 3, obtaining the synchronization channel spreading code sequence as a sequence of all 1s, and completing the spreading process; Step 4, select the synchronization channel scrambling code sequence as a full (1+j) sequence, and complete the scrambling process; Step 5, completing the weighting of the primary synchronization channel and simultaneously completing the weighting of the secondary synchronization channel; Step 6: The chip-level processing of the synchronous channel transmission is completed, and the weighted data of the I and Q channels of the synchronous channel are output. 2. The method according to claim 1, characterized in that the primary synchronization channel transmission sequence C _pNew and the secondary synchronization channel transmission sequence C _sNew ^{i, k} in the step 1 can be formed in an ASIC. 3. The method according to claim 1, characterized in that, the primary synchronization channel transmission sequence C _pNew and the secondary synchronization channel transmission sequence C _sNew ^i,k in the step 1 can be provided by or outside the ASIC. 4. The method according to any one of claims 1 to 3, wherein the spectrum spreading in the step 3 is to spread the I and Q two-way data of the master synchronization channel obtained by mapping with the synchronization channel respectively The code sequence is multiplied to obtain the chip-level I and Q data of the main synchronization channel; the I and Q data of the auxiliary synchronization channel obtained by mapping are multiplied by the spreading code sequence of the synchronization channel to obtain the auxiliary synchronization channel chip Level I, Q two-way data. 5. method according to claim 4, it is characterized in that, scrambling in the described step 4, is to obtain main synchronous channel chip level I, Q two-way data and auxiliary synchronous channel chip level I, Q two-way data According to the rule that the I channel is used as the real part and the Q channel is used as the imaginary part, the chip-level complex data of the primary synchronization channel and the chip-level complex data of the auxiliary synchronization channel are respectively multiplied by the scrambling code sequence of the synchronization channel to obtain The scrambled data of the primary sync channel and the scrambled data of the secondary sync channel. 6. The method according to claim 5, characterized in that, in the step 5, the data after scrambling of the primary synchronization channel obtained and the data after the auxiliary synchronization channel scrambling are multiplied with respective weighting factors respectively, and the primary synchronization channel The real part of the product result is used as the I-way chip-level weighted data of the main synchronization channel, and the imaginary part is used as the Q-way chip-level weighted data of the main synchronization channel; the real part of the product result of the auxiliary synchronization channel is used as the I-way of the auxiliary synchronization channel Chip-level weighted data, and the imaginary part is used as the chip-level weighted data of the Q channel of the auxiliary synchronization channel.

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