CN1879283A - Space vector PWM modulator for permanent magnet motor drive - Google Patents

Abstract

A space vector pulse-width modulator (SVPWM) and a method implemented by the modulator. A precalculation module accepts Ua and Ub modulation indexes and in response thereto, outputs modified Ua and Ub information; a sector finder has a U module which receives the modified Ua information and outputs a U sector; and a Z module which receives the U sector and the modified Ub information and outputs a Z sector. The U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation. For 3-phase modulation, the SVPWM and method further possess an active vectors calculation module and an assign vectors module which receive the modified Ua and Ub information and the U sector, and which calculate active vectors for 3-phase modulation; a zero vector selector which receives the Z sector and calculates zero vectors for 3-phase modulation; and a PWM counter block which receives the active vectors and zero vectors and outputs 3-phase control signals for implementing 3-phase modulation. The SVPWM and method may have a symmetrical PWM mode, an asymmetrical PWM mode, or both. Advantageously there may also be a rescale and overmodulation module which receives duration information corresponding to the vectors and in response thereto, detects the occurrence of overmodulation. Overmodulation may be detected in response to a negative zero vector time. The module may respond to overmodulation by clamping the zero vector time to zero and rescaling the active vector times to fit within the PWM cycle. The rescaling may restrict a voltage vector to stay within hexagonal boundaries on the space vector plane, while preserving voltage phase.

Description

Space Vector PWM Modulators for Permanent Magnet Motor Drives

cross reference

This application is based on and claims priority from US Provisional Application Serial No. 60/418,733, filed October 15, 2002. The aforementioned US Provisional Application is incorporated into this application by reference.

Background technique

1. Field of invention

The present invention relates to a motor driving device, and more particularly to a driving method and system for a permanent magnet surface mount (PMSM) motor using a space vector PWM modulation scheme.

2. Description of related technologies

Three-phase motor drives employing inverters are well known in the industry. The DC bus typically supplies switching power to different phases of the AC motor. To supply switching commands and sequences to inverters, sensorless vector control is attracting widespread attention. Sensorless control eliminates the speed sensor, flux sensor, and torque sensor and replaces them with DSP-based estimation from measured terminal voltage and current. Thus, it reduces the cost of the drive and increases its reliability. BACKGROUND DSP-based motor drives of interest are described in the inventor's U.S. application serial number 60/465,890, filed April 25, 2003, and U.S. application serial number 10/294,201, filed November 12, 2002. described in the application and they are incorporated herein by reference. However, estimation algorithms are complex, especially at low frequencies.

Space vector pulse width modulation (SVM) has become a popular form of pulse width modulation (PWM) for voltage-fed inverter drives because of its excellent harmonic quality and extended linear operating range. BACKGROUND OF THE INVENTION The SVM device of interest is described in application Serial No. 10/402,107, filed March 27, 2003, which is incorporated herein by reference.

One problem with SVM, however, is that it requires complex online calculations, typically limiting its operation to switching frequencies of at most a few kilohertz (eg, around 10 kHz). Switching frequency can be extended by utilizing high-speed DSP and simplified algorithms including look-up tables (LUT). The switching speed of power semiconductors, especially in IGBTs, has been significantly increased. However, the use of LUT's (unless they are very large) tends to reduce pulse width resolution.

Contents of the invention

The present invention can avoid complicated calculations and look-up tables in traditional space vector PWM modulation schemes such as arctangent and square root functions. It presents an algorithmic structure for implementing a versatile space vector PWM scheme capable of generating 3-phase and 2-phase SVPWM without sophisticated mathematical functions or look-up tables. The structure supports overmodulation, symmetric PWM and asymmetric PWM modes.

The present invention realizes a multi-purpose 2-level space vector PWM (SVPWM) modulation device, which can realize 3-phase and 2-phase modulation algorithms in a common algorithm structure. This implementation primarily utilizes decision logic and does not require any sophisticated mathematical functions such as arctangent, sine, cosine and/or square root functions. The algorithm provides overmodulation, symmetric and asymmetric mode capabilities.

The invention provides a space vector pulse width modulation device and a method realized by the modulation device.

According to an aspect of the present invention, a space vector pulse width modulation device (SVPWM) may include a pre-calculation module that receives Ua and Ub modulation indices and outputs modified Ua and Ub information in response to the indices.

According to another aspect of the present invention, a SVPWM may include a sector detector, which has a U module and a Z module, the U module receives Ua or modified Ua information and outputs U sector, and the Z module receives the Ua information The U sector and Ub or the modified Ub information and output the Z sector; the U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation.

According to another aspect of the present invention, for 3-phase modulation, SVPWM may include: an active vector calculation module and an allocation vector module, which receive Ua and Ub or modified Ua and Ub information and the U sector, and calculate an active vector for 3-phase modulation; a zero vector selector that receives the Z sector and calculates a zero vector for 3-phase modulation; and a PWM counter unit that receives the active vector and zero vector and outputs 3-phase control signal used to implement 3-phase modulation.

The PWM counter unit preferably has a symmetric PWM mode, an asymmetric PWM mode or both.

The SVPWM may further include a rescaling and overmodulation module for receiving persistence information corresponding to the vector, and detecting the occurrence of overmodulation in response to the persistence information. Overmodulation is preferably detected in response to a negative zero vector time. The module may respond to overmodulation by clamping the zero vector time to zero and rescaling the active vector period to within a PWM period.

The rescaling can restrict the voltage vector to stay within the hexagonal boundaries in the space vector plane while maintaining the voltage phase.

According to another aspect of the invention, the invention provides a method of performing at least the steps outlined above.

Other features and advantageous effects of the present invention will become apparent after the following embodiments are described in detail with reference to the corresponding drawings.

Brief description of the drawings

Figure 1 is a diagram describing 3-phase and 2-phase modulation schemes.

Fig. 2 is the structural block diagram of multi-purpose space vector PWM modulator;

Figure 3 shows the precomputation and sector detector unit of Figure 2 in more detail;

Fig. 4 shows the active vector calculation unit in Fig. 2 in more detail;

Figure 5 shows the rescaling and overmodulation unit in Figure 2 in more detail;

Figure 6 is a diagram describing overmodulation;

Figure 7 shows the zero vector selector unit in Figure 2 in more detail;

Figure 8 shows the sequence of states.

Detailed Description of Embodiments of the Invention

The following is a description of an embodiment of a PWM scheme.

The 3-phase and 2-phase PWM modulation schemes are shown in Figure 1. The volt-seconds (Volt-sec) produced by these two PWM strategies are consistent. However, when using 2-phase modulation, its switching losses can be significantly reduced, especially when high switching frequencies (greater than 10kHz) are used.

Figure 2 shows a block diagram of a multipurpose space vector PWM modulator. The design of the individual units is described in more detail below. The characteristics of this SVPWM are:

No need for arctangent, sine, cosine or square root functions at runtime;

Accepts rectangular inputs Ua and Ub (can easily interface with most vector controllers);

Ability to select zero vectors as desired;

Simplify overmodulation schemes with zero-vector time clamping;

Symmetrical and asymmetrical modes are automatically generated with updates of half the PWM period.

FIG. 3 shows details of the pre-calculations of FIG. 2 and the calculations in the sector detector unit. The input of this SVPWM receives modulation indices Ua and Ub (in quadrature), and its outputs are U_Sector (U sector) and Z_Sector (Z sector) (which are only used for 2-phase modulation). The area of a sector is defined in FIG. 3 . The sector detector is completely based on decision logic, which facilitates the realization of digital hardware platforms such as FPGA.

The above outputs are U_Sector and Z_Sector, which are defined as follows:

U_Sector:

0<=theta(θ)<60

60<=theta<120

120<=theta<180

180<=theta<240

240<=theta<300

300<=theta<360

Z_Sector:

A-30<=theta<30

B 30<=theta<90

C 90<=theta<150

D 150<=theta<210

E 210<=theta<270

F 270<=theta<330

FIG. 4 shows details of the active vector calculation unit in FIG. 2 . These calculations are mostly allocations. No sophisticated calculations are required.

Figure 5 shows the rescaling and overmodulation unit. Overmodulation is detected by negative values in the zero vector time (T0_Cnt_Scl) calculation. Overmodulation is easily handled by clamping this zero vector time to zero (if negative) and rescaling the active vector period to be within the PWM period. This rescaling constrains the voltage vector to stay within the bounds of the hexagon lying on the space vector plane (as shown in Figure 6). The magnitude of the required voltage is limited to the maximum possible voltage bound (hexagon in Figure 6). However, the voltage phase is always maintained.

Figure 7 shows the details of the zero vector selector unit. In Figure 1, for the first half of the PWM period (PWM_CNT_MAX), there are two zero-vector states for 3-phase modulation and one zero-vector state for 2-phase PWM. For 3-phase PWM, the first zero-vector state above is always V7 and the second zero-vector state is V8. However, for 2-phase PWM, one of the above zero-vector states can be V7 or V8, depending on where the voltage vector is (Z_Sector). Therefore, a zero-vector selector is used to handle various zero-vector possibilities.

The PWM counter unit in Figure 2 implements the PWM gating commands (Phase U, Phase V, Phase W). The cell has a state sequencer that steps through different states (VEC1 to VEC4, as shown in Figure 1). Both VEC1 and VEC4 states implement zero vectors, and VEC2 and VEC3 implement active vectors. The input to the PWM counter unit is sampled once for every half PWM period, which allows asymmetrical PWM mode operation without any reconfiguration.

For 3-phase modulation, the above state sequencer executes VEC1-VEC2-VEC3-VEC4-VEC4-VEC3-VEC2-VEC1, as shown in Figure 8. In the VEC1 state, the above-mentioned first zero vector will be realized based on T0_Vec_1 and T0_Cnt. There are three PWM counters, two for the active vector and the third for the two aforementioned zero vectors. For a 2-phase PWM modulation scheme, the state sequencer described above does not enter state VEC4 (VEC1-VEC2-VEC3-VEC3-VEC2-VEC1).

Two active vectors occur every half PWM period. An "allocate vector" unit (shown in Figure 2) determines which of the above two vectors will be used to achieve states VEC2 and VEC3. When 3-phase PWM is selected, the above zero vector time (T0_Cnt) is half.

definition

Ua-Alpha axis modulation

Ub-Beta axis modulation

U_Sector-The sector numbers shown in Figure 3 are 1 to 6 (each sector is 60°)

Z_Sector-The sector numbers shown in Figure 3 are A to F (each sector is 60°)

Ta_Cnt_R - normalized duration for activity vector A

Tb_Cnt_R - normalized duration for activity vector B

Ta_Vec_R - Active vector A (V1 to V6) used to form the command modulation vector

Tb_Vec_R - Active Vector B (V1 to V6) used to form the command modulation vector

T0_Vec_1 - Zero vector (V7 or V8) used in state VEC1

T0_Vec_2 - Zero vector (V7 or V8) used in state VEC4

Rescaled form of Ta_Cnt_Scl-Ta_Cnt_R

Rescaled form of Tb_Cnt_Scl-Tb_Cnt_R

T0_Cnt_Scl - Rescaled form of zero vector normalized time

Ta_Cnt - counter duration for state VEC2

Tb_Cnt - counter duration for state VEC3

T0_Cnt - counter duration for states VEC1 and VEC4

Ta_Vec - Vector used in state VEC2

Tb_Vec - vector used in state VEC3

Two_Phs_Pwm - select between 2-phase or 3-phase modulation

Z_Mode-2 phase modulation zero vector selection mode

Although the invention has been described with respect to specific embodiments thereof, many variations and modifications, as well as other uses, will be apparent to those skilled in the art. Accordingly, the invention is not limited to the specific disclosure herein.

Claims (17)

1. A space vector pulse width modulation device (SVPWM), comprising: a pre-calculation module that receives Ua and Ub modulation indices and outputs modified Ua and Ub information in response to said modulation indices; A sector detector, which has a U module and a Z module, the U module receives the modified Ua information and outputs a U sector, and the Z module receives the U sector and the modified Ub information and Output Z sector; The U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation; and For 3-phase modulation, the SVPWM also includes: an activity vector component that receives said modified Ua and Ub information and said U sector, and calculates an activity vector for 3-phase modulation; a zero vector selector that receives said Z sector and calculates a zero vector for 3-phase modulation; and A PWM counter unit that receives the active vector and zero vector and outputs a 3-phase control signal for realizing 3-phase modulation. 2. The SVPWM of claim 1, wherein the active vector component comprises an active vector calculation module and an allocation vector module. 3. The SVPWM of claim 1, wherein the PWM counter unit has a symmetrical PWM pattern. 4. The SVPWM of claim 3, wherein the PWM counter unit has an asymmetrical PWM pattern. 5. The SVPWM of claim 1, wherein the PWM counter unit has an asymmetrical PWM pattern. 6. The SVPWM of claim 1, further comprising a rescaling and overmodulation module for receiving persistence information corresponding to the vector and detecting the occurrence of overmodulation in response to the persistence information. 7. The SVPWM of claim 6, wherein overmodulation is detected in response to a negative zero vector time. 8. The SVPWM of claim 7, wherein the rescaling and overmodulation module rescales the active vector period to be in the PWM period by clamping the zero vector time to zero and rescaling the active vector period within, thus responding to overmodulation. 9. The SVPWM of claim 8, wherein the rescaling confines the voltage vector to stay within the bounds of a hexagon in the space vector plane while maintaining the voltage phase. 10. A method for realizing Space Vector Pulse Width Modulation (SVPWM), comprising the steps of: a pre-calculation step in which Ua and Ub modulation indices are received and in response to said modulation indices output modified Ua and Ub information; A sector detector step, which includes the step of receiving the modified Ua information and outputting the U sector, and receiving the U sector and the modified Ub information and outputting the Z sector; Wherein, the U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation; and For 3-phase modulation, the SVPWM also includes the following steps: An activity vector calculation step, which includes the step of receiving said modified Ua and Ub information and said U sector, and calculating an activity vector for 3-phase modulation; A zero vector selection step comprising the step of receiving said Z sector and calculating a zero vector for 3-phase modulation; and A PWM counting step, which includes the step of receiving said active vector and zero vector and outputting a 3-phase control signal for realizing 3-phase modulation. 11. The method of claim 10, wherein the PWM counting step implements a symmetrical PWM pattern. 12. The method of claim 11, wherein the PWM counting step implements an asymmetric PWM mode. 13. The method of claim 10, wherein the PWM counting step implements an asymmetric PWM mode. 14. The method of claim 10, further comprising an overmodulation detecting step of receiving persistence information corresponding to said vector and responding to said persistence information to detect the occurrence of overmodulation. 15. The method of claim 14, wherein overmodulation is detected in response to a negative zero vector time. 16. The method of claim 15, wherein the method responds by the steps of clamping the zero vector time to zero and rescaling the active vector period to be within the PWM period overmodulation. 17. The method of claim 16, wherein the step of rescaling confines the voltage vector to stay within the bounds of a hexagon in the space vector plane while maintaining the voltage phase.

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