CN1878155A - For full duplex multilevel pulse amplitude modulation systems and blind activation receivers - Google Patents

Abstract

The present invention providesA novel receiver for full-duplex multi-level PAM systems using analog-to-digital converters (ADCs) with flexible settings of (N)_s+1)/N_sWherein the sampling rate of N_sIs an integer equal to or greater than 1; the fractional interval echo canceller is used for eliminating the echo output by the ADC; the use of a fractional sampling rate higher than the transmission rate also enables the timing recovery function to be implemented in the digital domain and avoids the need to use complex analog phase unselected circuits; the receiver achieves fast and blind activation by using a decision feedback equalizer with a single main valve and a soft-stage slicer. The derivative channel estimate may be used to optimally locate the timing phase. Once the "open-eye" state is achieved, the channel equalization switches to linear equalization using an error feedback equalizer to mitigate the error propagation problem associated with decision feedback equalizers.

Description

For full duplex multilevel pulse amplitude modulation systems and blind activation receivers

technical field

The present invention relates to equipment and methods used in full-duplex multi-level pulse amplitude modulation (PAM) systems, in particular to solutions for full-duplex full-duplex Gigabit Ethernet (Gigabit Ethernet) transceivers. Apparatus and method for a multi-level PAM system.

Background technique

Various receiver structures for full-duplex multi-level Pulse Amplitude Modulation (full-duplex multi-level Pulse Amplitude Modulation) have been proposed for implementation in Gigabit (later referred to as Ultra High Speed) Ethernet transceivers In eg US Pat. Nos. 6,771,752 and 6,731,692 and publication by Agere Systems in 2003 titled "IntelliRate Architecture". These structures all utilize a sampling rate that is exactly equal to the transmission rate (f _b ) or twice the transmission rate (2f _b ). Using transmission rate sampling requires sampling the received signal at the optimal timing phase position of the analog-to-digital converter (ADC) output, thus requiring complex phase selection in the analog domain. In the "IntelliRate Architecture" publication mentioned above, the analog phase selection circuit can be removed by doubling the ADC speed and using a digital equalizer to compensate for timing phase misalignment and channel distortion. Although removing the phase selection circuit reduces the complexity of the analog circuit, using doubled ADC speed inevitably increases the complexity of the ADC. For example, the transmission rate of the ultra-high-speed Ethernet network is 125MHz, and it is very difficult to realize a 250MHz ADC with high bit resolution. Therefore, there is a need for a receiver architecture with a flexible sampling rate that can eliminate the use of complex analog phase selection circuits without doubling the speed of the ADC.

Furthermore, for a full-duplex PAM system, a part of the transmitted signal will be echoed from the hybrid circuit to the front end of the receiver. This echo must be eliminated before demodulation of the received signal. This problem was published by Werner, J.-J. Modems" article suggests a solution. In view of the structure of the existing transmission rate receiver in this paper, a transmission rate digital echo canceller is used to eliminate the echo after the ADC. This will be replaced by a fractional transmission rate digital echo canceller in the receiver architecture described in detail later in the present invention. Fractional transmission rate echo cancellers have the ability to remove out-of-band noise that couples to the echo and therefore provide better noise performance than transmission rate echo cancellers.

Usually after echo cancellation, and before channel equalization can be implemented, the received signal must be sampled at the correct timing phase to obtain the best signal-to-noise performance at the output of the equalizer. During the receiver active phase, the receiver is fully "blind", meaning it cannot sample the signal at the correct timing and does not have the correct equalizer coefficients to equalize the channel distortion. Existing approaches use a Decision Feedback Equalizer (DFE) with a soft-level slicer to effectively achieve "blind" activation, but this structure is difficult for the receiver to operate in a more noisy environment In the lower case, there is an error propagation problem due to decision errors. It has been proposed to reduce this error effect by combining DFE and Viterbi (Viterbi) decoder. For example, in 2001, it was published by Erich F. Haratsch in the IEEE Journal of Solid-State Circuits under the title "Use for 1000BASE-T Ultra-high-speed Ethernet 1 Gb/s Splice Equalizer and Interleaver Decoder" and the above two US Patent Nos. 6,771,752 and 6,731,692. But the implementation of this combination of DFE and Viterbi decoder is still complicated. Therefore, there is a further need in the receiver for an equalization method capable of fast blind activation and at the same time solving the error propagation problem of traditional DFE.

Contents of the invention

In order to overcome the above-mentioned shortcoming of the prior art, the present invention provides a kind of receiver suitable for full-duplex multi-level pulse amplitude modulation transceiver comprising: analog-to-digital converter (ADC), converts the received analog signal into a Digital sampling at a fractional transmission rate; digital resampler that converts samples at a fractional transmission rate with an arbitrary timing phase into data samples at the transmission rate and derivative samples at the transmission rate, both samples at the optimal timing phase; equalization a unit receiving the transmission rate data samples to adaptively perform channel equalization at the transmission rate; and a timing recovery feedback unit receiving the transmission rate data samples by receiving the transmission rate derivative samples and an output from the equalization unit , adaptively locates the optimal timing phase and outputs an estimate of the timing phase back to the digital resampler.

In addition, the equalization unit of the present invention includes a decision feedback equalizer fixed on a mainline valve, and a soft-level cutter controlled by an adaptive level, according to the distribution of the cutter output points and the relative Deductive information from this distribution is used to update the fitness level.

The present invention proposes a receiver structure that utilizes an ADC with a rate of ( _Ns +1)/ _Ns · _fb to sample an analog received signal plus an echo at the receiving end of a hybrid circuit. (N _s +1)/N _s fractionally spaced digital echo cancellers are used to cancel echoes at the ADC output. The echo canceller is driven by locally transmitted symbols from the transmitter operating at the transmission rate sampling clock. The coefficients of the echo canceller are adaptively adjusted using a least mean square (LMS) adaptive algorithm to minimize echo residuals.

After removing echoes from the received signal, a digital resampler is used to adjust the timing phase to maximize the signal-to-noise ratio at the equalizer output, where the optimal timing phase is fed back from a timing recovery phase-locked (PLL) The loop is computed recursively. By properly adjusting the phase in the feedback loop of the timing recovery PLL, the digital resampler can also efficiently convert the sampling rate from (N _s +1)/N _s f _b to f _b , so that the channel equalization can be performed in the transmission operate at the speed. The use of the transmission rate equalizer is relatively simple, and as long as the optimal timing phase can be recovered from the timing recovery PLL feedback loop, its performance is close to that of the more complex fractionally spaced equalizer. Since both the timing recovery PLL loop and the resampler are implemented in bits, the samples at the transmission rate with the optimal timing phase can be correctly regenerated, thus ensuring the performance of the transmission rate equalizer.

The digital resampler includes a finite impulse response (FIR) polynomial structure capable of simultaneously computing corresponding derivative samples at the same timing. The sequence of derivative samples includes timing information which can be extracted by estimating the sequence in least mean squares by a derivative channel estimator linearly combined with a slicer. The timing phase error is then derived from the coefficients of the derivative channel estimator, where statistically zero timing error is defined when the first derivative of the channel response at the main cursor position drives to zero. The timing phase error is provided to a timing recovery PLL circuit to generate an estimate of the optimal timing phase position. The loop of the timing recovery PLL circuit is completed by feeding the new timing phase estimate back to the digital resampler, thus generating the transmission rate samples and derivative samples corresponding to this new timing phase, which are used for equalization and derivative respectively in the next iteration channel estimator.

The channel equalizer of the receiver of the present invention has two modes of operation. The first mode, which will be called Blind Equalization (BEQ), uses a decision-feedback equalizer with a soft-level slicer to ensure fast blind activation. The convergence of decision feedback equalizers and derivative channel estimators depends largely on the probability of correct decisions at the slicer output. Fast blind activation can be achieved by using a single weight coefficient for the mainline valve and a soft-level slicer utilizing a priori information about the probabilities of the PAM levels sent at the remote sender. This probability information is used to adaptively adjust the decision range of the soft grade cutter to ensure that the probability of correct decision is maintained at an acceptable level. Consistent fast blinding was observed for both short and long cable lengths for the three-stage PAM used in the training mode of Ultrafast Ethernet. In order to alleviate the error propagation problem of DFE, the channel equalization is switched to the second mode, which is called linear equalization after eye opening (Linear EQualization After Eye Open; LEQ), using a linear equalizer in series with an error feedback equalizer (EFE) . Once the convergence of the DFE and the sequential loop is observed, the LEQ branch becomes active and the LEQ and EFE coefficients are trained. Hard levels in the LEQ branch will not produce correct decisions within an acceptable probability at the beginning of training. Therefore, the BEQ remains active and the soft-level cutter output is used to calculate the cutter error of the LEQ branch for equalizer coefficient update. Once it is detected that the hard-level scriber output produces a correct decision with an acceptable probability, the BEQ branch can be stopped and the LEQ branch can be put into decision-directed operation, using the hard-level scriber output to calculate the scriber error. The role of the EFE is to compensate for the noise enhancement produced by the linear equalizer. While incorrect scriber decisions can also affect EFE performance, the error propagation problem is greatly reduced relative to DFE approaches where the EFE length is typically short and the scriber can be limited with a hard limiter when presented to the EFE error.

Description of drawings

FIG. 1 shows a block diagram of a receiving architecture in a Super Fast Ethernet transceiver according to an embodiment of the present invention;

FIG. 2 shows a block diagram of a (N _s +1)/N _s transmission rate fractional spaced echo canceller according to an embodiment of the present invention;

Figure 3 shows an embodiment of a digital resampler according to the present invention;

Figure 4 shows a blind equalization (BEQ) branch according to an embodiment of the invention;

Figure 5 shows a linear equalization (BEQ) branch according to an embodiment of the invention;

Figure 6 shows a 2-to-1 multiplexer, selecting one of the soft scriber output or the hard scriber output as the receiver symbol decision;

Figure 7 shows a derivative channel estimator according to an embodiment of the invention;

FIG. 8 shows a timing recovery PLL circuit according to an embodiment of the present invention;

Figure 9 shows a block diagram of a frequency synthesizer that generates both the transfer rate and the (Ns+1)/Ns transfer rate to drive the DAC and ADC respectively;

Figure 10 shows a typical training sequence for master and slave modes;

Figure 11 illustrates a flow chart of the detailed training sequence of timing phases and equalizer coefficients for master and slave modes; and

FIG. 12 shows the difference between the error signal definition of the known noise estimation method and the error feedback equalizer method of the present invention.

Detailed ways

Example

As shown in FIG. 1, the receiver structure 1 of the present invention includes a mixer 10, an analog-to-digital converter (ADC) 11, a fractionally spaced echo canceller 12, a digital resampler 13, a local/remote clock generator 14, Timing recovery PLL circuit 15 , blind equalization (BEQ) branch 16 , linear equalization (LEQ) branch 17 , 2-to-1 multiplexer (Mux) 18 and derivative inverting estimator 19 .

The BEQ branch 16 includes a decision feedback equalizer 161 and a soft level slicer 162 , wherein the LEQ branch 17 includes a linear equalizer 171 , an error feedback equalizer 172 , a hard level slicer 173 and an error level hard limiter 174 . See below for descriptions of these two branches.

The sampling rate of the ADC 11 is elastically set as (N _s +1)/N _s multiplied by the transmission rate, where N _s is an integer equal to or greater than 1. Therefore, when N _s is selected as 1, the sampling rate is equal to 2 times the transmission rate, and when N _s becomes positive and infinite, the sampling rate is equal to the transmission rate. By choosing N _s in the range (1, ∞), the architecture employs fractional transmission rate sampling between f _b and 2f _b . The use of fractional transfer rates provides an oversampling factor that allows timing phase selection to be performed in the digital domain, thus eliminating the need for analog phase selection circuitry and without doubling the ADC speed. Because of the flexibility of setting N _s as a parameter, an appropriate ADC rate can be set between the transmission rate and twice the transmission rate to achieve the best design trade-off and reduce the complexity of the analog circuit. For example, if N _s is chosen to be 5, the architecture of the present invention requires an ADC speed of 150 MHz for ultra-high-speed Ethernet, which is significantly lower than the 250 MHz required in a receiver with a 2f _b sampling rate, while having no complex analog phase Advantages of choosing a circuit.

In SuperSpeed Ethernet, the transceiver itself can be divided into master and slave modes. The local clock of the master mode transceiver is used as the timing reference for the full-duplex system. A slave mode transceiver must use this timing reference to transmit and receive symbols. Due to this difference, the difference between the training sequences of the master and slave modes lies in the different training sequences of the echo canceller, equalizer and timing recovery PLL circuit, as shown in FIG. 10 . First full-duplex systems operate in a semi-multitasking mode, where only the master transmits and the slaves remain silent. The master trains its echo canceller in its semi-multitasking mode, while the slave trains its equalizer and timing synchronization at the same time. The slave starts sending signals once the master has converged its echo canceller and the slave has converged its equalizer and timing is synchronized. The master then starts its equalizer and timing training while the slave trains its echo canceller. As shown in Figure 10, when both sides have finished training, both the master and the slave enter into full-duplex data mode.

Figure 2 shows in detail the (N _s +1)/N _s transmission rate fractional spaced echo canceller 12 structure. Moves the transmit symbol shift in the echo canceller valve delay line during echo canceller training mode. Since the symbols are sent at the transmission rate while the echo canceller 12 is operating at the ( _Ns +1)/ _Ns transmission rate, this movement is paused every ( _Ns +1) clock cycles to match both rates. (N _s +1) sets of echo canceller weight coefficients are used to linearly combine with data samples in the valve delay line in a round-robin fashion. Each set of weight coefficients corresponds to an echo path estimate for one of the (N _s +1) time-series phases. The existing LMS algorithm is used to adjust the weight coefficient, as shown in the lower right corner of Figure 2. The coefficient update of each linear combiner basic circuit can be expressed as follows:

h _ec (m+1)＝h _ec (m)+α _ec x(m)b(m)

Among them, α _ec is the step size. The signal x(m) is given by:

x(m)=r(m)-ec(m)

It is the ADC output, r(m), minus the estimated echo from the echo canceller output, ec(m), and supplied to the digital resampler 13 for further processing. The fractional transmission rate echo canceller's ability to remove out-of-band noise coupled with the echo, therefore provides better noise performance than transmission rate echo cancellers.

Figure 11 shows the training state diagrams for the equalizer and timing phase/frequency offset in master and slave modes. At the beginning of this training, CLK_SEL is set to local, and SLICER_SEL is set to SOFT (soft) whether the transceiver is in master or slave mode. The blind activation sequence and equalization (BEQ) procedure then begins. Echo has little or no effect in this training because the master mode transceiver cancels echo at the ADC output, and the transmitter of the slave mode transceiver is quiet (not transmitting).

In this BEQ training mode, the digital resampler 13, the decision feedback equalizer 171, the soft level slicer 172, the derivative channel estimator 19, and the timing recovery PLL circuit 15 work together to converge to "open eyes" during the BEQ training phase status. As shown in FIG. 3 , the echo-free received signal x(m) is input to the digital resampler 13 . The digital resampler 13 includes a rate adjuster 131 , a FIR filter bank 132 and a polynomial combiner 133 . The simple rate adjustment circuit 131 is used to shift one or two x(m) samples into the valve delay line of the FIR filter bank 132 . The 1-bit index I(n) generated by the timing recovery PLL circuit 15 is used to indicate this movement, wherein when I(N)=0, it corresponds to a movement of one sample, and when I(n)=1, it corresponds to a movement of two samples. sampling. Note that all circuits before the rate adjustment circuit 131 operate at the (N _s +1)/N _s transmission rate and after the rate adjustment circuit 131 operate at the transmission rate. The FIR filter library 132 has a polynomial structure form, as described by Farrow, CW 1988 in the article titled "Continuously Variable Variable Bit Delay Components" in IEEE International Symposium on Circuit Systems, wherein the FIR filters with the same timing phase can be calculated simultaneously The corresponding derivative is sampled without adding many additional circuits, as shown in Figure 3. If x _b (n) is an Lx1 vector, its i-th element corresponds to the i-th element in the valve delay line of the FIR filter bank 132, and the L output of the FIR filter bank 132 is represented by the following:

${\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; T</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0,1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; KL</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}$

in

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\left[\begin{array}{c}{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}\\ {\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\\ \mathrm{<span\; class="notranslate">\; m</span>}\\ {\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\end{array}\right]$

is an Lx1 vector, including the fixed weight coefficient of the i-th filter in the FIR filter bank 132 and the superscript T represents a vector/matrix transpose operation. The polynomial combiner 133 obtains the L output from the FIR filter library 132, and the phase position represented by (n) generated by the timing recovery PLL circuit 15 at each transmission rate clock, and calculates data samples and derivative samples as follows:

$\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; the\; y</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; i</span>}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}^{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>$

The data samples y(n) are then provided to an equalizer zone, and the derivative samples y&apos;(n) are provided to a derivative channel estimator 19.

As shown in FIG. 4, the decision feedback equalizer 16 includes both feedforward and feedback valves. The main valve position is assumed to be at D delay, and the dynamic response weight factor is fixed at one. The input to the soft level cutter is then given by:

$\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; ffe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; dfe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>$

接着提供给2至1多任务器18，并且在此训练阶段期间，SLICER_SEL＝SOFT，其意味着 $a\left(n\right)=\tilde{a}\left(n\right).$ 此切划器误差，由s(n)-a(n)计算，是用于更新前馈以及回馈系数如下列所示：The determination range of the soft grade cutter is set to {0, ±A(n), ±2A(n), K}. The setting of A(n) can be easily understood by assuming a three-level PAM, and the induction of more levels is not repeated here. In the initial case, A(n) is set to a nominal value such that the decision level is equal to the hard level cutter. Counts the number of scriber output points that fall within the range [-A(n)A(n)] and also counts the number of scriber output points that fall outside the range [-A(n)A(n)]. Deductive (a priori) information about the probability of the remotely transmitted symbol falling within or outside this range is used to decide whether A(n) should be increased or decreased so that the cutter output points fall within or outside this range The number very closely matches the probability distribution at the remote location. The increase or decrease of A(n) is controlled by a simple step size ΔA(n), which can be set small to ensure stability. Note that this decision level adjustment is only used to determine the mapping of the cutter output to one of the remote send symbol levels. cutter output Nominal values are still set for each level to ensure proper cutter error is calculated. cutter output

This is then provided to the 2 to 1 multiplexer 18, and during this training phase, SLICER_SEL=SOFT, which means $a\left(\mathrm{no}\right)=\tilde{a}\left(\mathrm{no}\right).$ The cutter error, calculated by s(n)-a(n), is used to update the feedforward and feedback coefficients as follows:

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; ffe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; ffe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}_{\mathrm{<span\; class="notranslate">\; ffe</span>}}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0,1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; KD</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}$

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; dfe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; dfe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}_{\mathrm{<span\; class="notranslate">\; dfe</span>}}\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1,2</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; KN</span>}$

where α _ffe and α _dfe step size.

The slicer output a(n) is also used to estimate the channel derivative, as shown in Fig. 7, where the sequential linear combination of the slicer output is adaptively adjusted in the derivative channel estimator 9 to estimate the derivative sample y'( n). The estimation is achieved by least squares of the mean, where the weight coefficients are updated as follows:

dch _i (n+1)=dch _i (n)+α _dch a(ni)e ^dch (n), i=0, 1, K J

where α _dch is the step size, and

${\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; dch</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; the\; y</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; J</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; dch</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>$

is the real-time estimation error at time n. The resulting weight coefficient is the derivative channel response valve estimate, and the negative value of the estimated derivative at the mainline position, -dch _Δ (n), is used as the timing error to drive the timing recovery PLL circuit 15, as shown in FIG. 8 . Note that Δ corresponds to the desired pre-cursor amount in the derivative channel estimator. When dch _Δ (n) becomes zero, this state means that the main line is sampled at the highest point corresponding to the channel response, so the signal-to-noise ratio can be maximized.

As shown in FIG. 8 , the timing recovery PLL circuit 15 includes a second-order loop filter 151 , a phase integrator 152 and a phase warper 153 to generate phase estimates represented by I(n) and μ(n). The second stage loop filter 151 acts to filter out timing error jitter before the phase integrator 152 to flatten the timing phase estimate. The transition from the transmission rate sampling phase to the (N _s +1)/N _s transmission rate phase is performed by using a correction factor consisting of multiplying the phase error Δφ(n) by (N _s +1)/N 1/N _s is subtracted from _s , as shown in Fig. 8 . A simple phase warper 153 is used to perform phase warping at the phase integrator 152 output and has the following function:

I(n)=1, μ(n)=θ(n)+1, if θ(n)<-0.5

I(n)=0, μ(n)=θ(n), otherwise

Note that both θ(n) and μ(n) are constrained in the range -0.5 to 0.5 after the phase warper 153 . The resulting 1-bit index I(n) and normalized phase value μ(n) are fed back to the digital resampler 13, which completes a "blind" equalization and timing recovery loop for the newly estimated timing phase. The unadjusted phase error, Δφ(n), is also provided to the local/remote clock generator 14, as shown in FIG. 9 . Note that during the blind activation phase, CLK_SEL is set to LOC (local), so the (N _s +1)/N _s transfer rate clock used to drive the ADC is synchronized with the local transfer rate clock fb_loc, regardless of whether the transmitter is in master or slave mode.

After blind equalization and timing convergence to the "eye-open" state, where the slicer primarily regenerates the delayed version of the remotely transmitted symbol sequence, the master mode receiver can switch directly to training the linear equalizer and error feedback coefficients. For slave mode receivers, the timing loop needs to continue to be trained to learn the frequency shift (the difference in transmission rate between the remote transmitter and the local receiver, up to ±100PPM for SuperSpeed Ethernet) to within acceptable limits. Practically, this frequency shift can be observed from the delay cells in the lower branch of the second-order loop filter 151 in the timing recovery PLL circuit 15 as shown in FIG. 8 . Once this frequency shift is achieved, CLK_SEL can be changed to REM to switch the ADC clock frequency to synchronize with the remote transmitter clock frequency. As shown in FIG. 9, the unadjusted phase error, Δφ(n), is used to drive the integrator 141, the phase limiter 142 and the frequency synthesizer 143 in the local/remote clock generator circuit 14 to synthesize Remote transfer rate clock f _b _rem. A simple frequency multiplier 144 is readily used to generate a corresponding (N _s +1)/N _s ·f _b fractional transfer rate clock. Once the frequency shift is obtained, the clock actually converges to synchronize with the remote transmit transmission rate. Because the frequency shift can be quickly corrected by this local/remote clock generator circuit 14, the delay elements in the lower branch of the second-stage loop filter 151 in the timing recovery PLL circuit 15 should be set to zero to avoid " Repeat Compensation". During clock switching operations in this slave mode, the coefficients of the frozen decision feedback equalizer are more stable, avoiding any transient effects that would cause the equalizer to drift. It is also necessary to re-converge the timing phase position because the synthesized fb_rem only tracks the frequency of the remote clock and not the optimal phase position. A direct consequence of not tracking the phase in the analog domain is the absence of any complex analog phase unselection circuitry, and through the use of digital resamplers, the job of phase adjustment is performed in the digital domain, even when the ADC clock is out of sync with the remote clock. Synchronize on the pulse frequency.

Referring again to FIG. 11 , after the timing phase re-converges to the optimal setting, the "eye-open" state can be reached again. Slave receivers can now switch to training linear EQ and error feedback EQ as in master mode. At the beginning of training, SLICER_SEL is set to SOFT so that the decision from BEQ 16 can be used to calculate the slicer error to update the linear and error feedback equalizers 171 and 172 . SLICER_SEL should be set to HARD only when the LEQ branch 17 converges to the "eye open" state to activate the decision oriented mode. As shown in FIG. 5, the updating of the linear equalizer 171 and the error feedback equalizer 172 is given by:

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; leq</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; leq</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}_{\mathrm{<span\; class="notranslate">\; leq</span>}}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; [</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0,1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; KK</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}$

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; efe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; efe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}_{\mathrm{<span\; class="notranslate">\; ffe</span>}}{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; efe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; [</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1,2</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; I</span>}$

where α _leq and α _ffe are the step size, and

e ^efe (ni)=s(ni)-a(ni), i=1, 2,..., I

is the delayed form of the cutter error. The cutter input is the combination of the linear equalizer output and the error feedback equalizer output as follows:

$\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; leq</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; I</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; efe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; efe</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>$

After the LEQ has converged, the receiver will enter data mode. A hard limiter 174 may also be used to limit the error of the scriber before being provided to the error feedback equalizer 172 . It should be noted that Error Feedback Equalizer (EFE) 172 differs from existing approaches to estimating noise in US Pat. No. 5,784,415 and in publications by Eybuoglu, M.V. As shown in FIG. 12 , in the traditional noise estimation method, the generated error signal is the difference between the output of the cutter and the output of the linear equalizer. This error is then estimated using a linear estimation filter and used to remove "colored" noise at the output of the linear equalizer. In the EFE method of the present invention, the generated error signal is the difference between the output of the scriber and the input of the scriber. Because the slicer output includes both the linear equalizer 171 output and the EFE 172 output, the error signal is not "colored" noise as in the linear estimation method. In a converged state, the error signal defined here has less noise and represents the combination of all uncancelled noise at the scriber input. The EFE 172 thus plays a role of adaptively tracking these noise components and removing them in a time-varying manner.

Claims (15)

1. receiver that is applicable to full-duplex multi-level pulse amplitude modulation transceiver, receive and modulation by teletransmitter with the analog signal that transmission rate sends, it is characterized in that this receiver comprises:

Analog-digital converter (ADC), this analog signal that conversion receives is to the digital sampling with mark transmission rate;

Digital resampler, the sampling that will have the mark transmission rate of arbitrary sequence phase place converts the data sampling of transmission rate and the derivative sampling of transmission rate to, and these two samplings all are positioned at best sequential phase place;

Deng changing the unit, receive this transmission rate data sampling to carry out change such as channel adaptively with transmission rate; And

The timing recovery feedback unit receives the data sampling of this transmission rate, by receiving this transmission rate derivative sampling and change the output of unit from these, adaptive positioning should the best sequential phase place and the estimation of exporting this sequential phase place return this digital resampler.

2. receiver as claimed in claim 1 is characterized in that, this mark transmission rate is by with (N _S+ 1) divided by N _SAnd multiply by this transmission rate, wherein N _SBe to be equal to or greater than 1 integer.

3. receiver as claimed in claim 2 is characterized in that this receiver also comprises fractional spaced echo eliminator, is driven by the transmission symbol from the local transmitter of operating with transmission rate sampling clock pulse in the transceiver.

4. receiver as claimed in claim 3 is characterized in that, this fractional spaced echo eliminator comprises the valve delay line that is used for moving this transmission symbol, every (N _S+ 1) the clock pulse cycle is suspended once and should move.

5. as each described receiver in the claim 1 to 3, it is characterized in that this digital resampler comprises that speed adjusts circuit, filtering storehouse and multinomial colligator, this speed adjuster is used for coupling (N _S+ 1)/N _SSpeed between transmission rate and the transmission rate, this data sampling and derivative are taken a sample, and both are all produced by the multinomial colligator according to the identical output from the filtering storehouse.

6. receiver as claimed in claim 5, it is characterized in that, this speed is adjusted circuit the sample of signal of importing is moved in the valve delay line in filtering storehouse according to 1 index from this timing recovery feedback unit, and wherein this multinomial colligator is obtained the phase position that produces at every transmission rate clock pulse from the output in filtering storehouse and this timing recovery feedback unit, and calculate the data sampling of this transmission rate and the derivative sampling of this transmission rate.

7. as claim 1 or 3 described receivers, it is characterized in that, these are changed the unit and comprise having the DFF that is fixed on a main line valve, and cut by the gentle rank of adaptability rank control and to draw a device, draw the device output point and distribute and upgrade this adaptability rank about the deduction information of this distribution according to this is cut at this long-range transmitting terminal.

8. as claim 1 or 3 described receivers, it is characterized in that these are changed the unit and comprise:

Circuit is changed in blind activation etc., carries out changes such as channel in the receiver activation stage; And

Linearities etc. are changed circuit, carry out changes such as channel when the receiver steady state.

9. receiver as claimed in claim 8 is characterized in that, this BEQ circuit comprises that DFF and gentle rank are cut and draws a device.

10. receiver as claimed in claim 8 is characterized in that, this LEQ circuit comprises that linear equalizer and hard rank are cut and draws a device.

11. receiver as claimed in claim 10, it is characterized in that, this LEQ circuit also comprises error feedback equalizer, be used for linear the compensation adaptively and add very noisy by what this linear equalizer produced, wherein by this error of changes generations such as error feedback cut for this hard rank the input of drawing device with export poor.

12. receiver as claimed in claim 10 is characterized in that, this LEQ circuit also comprises hard limiter, limits this hard rank and cuts the error level of drawing device and reduce error propagation.

13. receiver as claimed in claim 1 is characterized in that, this timing recovery feedback unit comprises:

The derivative channel estimator uses the output of this change unit to produce the sequential phase error, is received from the derivative sampling of this transmission rate of this digital resampler with estimation; And

The timing recovery phase-locked loop circuit receives this sequential phase error and produces estimation that best sequential phase place do not put to offer this digital resampler.

14. receiver as claimed in claim 13 is characterized in that, when first order derivative of the channel of main line valve position in this derivative channel estimator reaction orders about when becoming zero, defines zero sequential phase error statistics on.

15. receiver as claimed in claim 13, it is characterized in that, this timing recovery PLL circuit comprises second rank loop filter and the integrator, this sequential phase error is offered before this integrator, adjust and subtract to calculate by simple size and adjust this sequential phase error, be created in the phase place in the mark transmission rate field that can offer this digital resampler, and represent the output of phase place effectively by this 1 position index.

Images