CN1862266A - Method for testing product fault-tolerant performance and fault inserting device thereof - Google Patents

Abstract

The invention provides a product fault tolerance test method and a fault insertion device thereof. The fault tolerance test is performed on the product by generating a fault simulation signal. The method sets a fault insertion device inside the product, and the fault insertion device generates different types of fault simulations. Signal, select the communication control module of the fault insertion device through the CPU control interface inside the product, control the content of the control register of the communication control module, and selectively insert different types of fault analog signals into any chip input/output pins Or directly insert the functional modules inside the chip to simulate the failure of some or all of the internal units of the product. This method can provide a simple and powerful online fault insertion method for electronic products, which can complete the simulation of various types of signal faults, comprehensively simulate various fault modes, improve the coverage and repeatability of single-board testing, and enrich fault tolerance. The test method has improved the test effect.

Description

Product Fault Tolerance Test Method and Fault Insertion Device

technical field

The invention relates to reliability testing of electronic products, in particular to a product fault tolerance testing method and a fault insertion device thereof.

Background technique

The design of modern electronic products is becoming more and more complex, and their role in people's lives is becoming more and more important. The requirements for product reliability are becoming increasingly strict. Once a product fails, such as a high-end communication product, it will bring great harm to the user. Big loss. Therefore, the reliability design of fault tolerance in electronic products has become increasingly important, and the product fault tolerance test for product reliability design has also become increasingly important.

The fault tolerance test is to simulate the failure of a certain chip inside the product, the loss of the internal clock signal, the error of the internal state signal, etc., whether the product can take correct protection and alarm measures, and whether the product can return to the correct working state after the error is recovered . On the one hand, the product fault-tolerant reliability test can verify whether the product reliability design can be implemented correctly through testing, and on the other hand, it can find problems in the product fault-tolerant design through fault insertion, so that corresponding measures can be taken at the initial stage of the product to modify the product fault-tolerant aspect problems and improve product reliability. The core of product fault tolerance testing lies in the insertion mode of the fault simulation signal.

At present, the method of inserting the fault analog signal basically adopts the method of inserting the fault signal by an external probe. For example, the method adopted in the Chinese patent No. 02108648 is to use an external electronic unit to generate error signals such as high, low, and pulse, and output to the external probe, and then attach the probe to the signal point inside the product for fault insertion.

But, there is the problem of following several methods in this prior art:

1. An additional error signal generation unit is required, and the cost is high. It is also necessary to consider how to make the probe and the signal point in close contact. The technical implementation is relatively complicated and the versatility is not strong;

2. The operability is poor, and manual operations such as placing probes are required. For complex products with many internal signal points, the test efficiency that requires manual operations is relatively low;

3. Since the external signal is superimposed on the original internal signal of the product, when the internal signal drive is strong, the insertion of the external signal can sometimes only distort the internal signal of the product. In addition, for high-frequency signals, even if There is no fault signal insertion on the external probe, which will also have a great impact on the signal quality. In these cases, the impact of the expected fault insertion signal on the product cannot be correctly judged, and the correct fault insertion test effect cannot be obtained;

4. It is impossible to simulate the failure mode of the signal disconnection (high resistance state) through the external insertion method, and it is still only possible to manually disconnect the internal path of the product for testing.

Contents of the invention

The purpose of the present invention is to overcome the defects of poor operability, low test efficiency, inaccurate test effect and inability to simulate the fault mode under signal disconnection (high impedance state) in the prior art, thereby providing a product fault-tolerant test method and It's a faulty plug-in device.

In order to solve the above technical problems, the product fault tolerance test method provided by the technical solution of the present invention generates different types of fault simulation signals inside the product, and automatically determines the insertion type and insertion position of the fault simulation signal by controlling the fault simulation signal, thereby Realize partial or complete failure of internal functional units of simulated products.

The fault simulation signal is generated by the fault insertion device, and the fault simulation signal includes: long high, long low, high impedance state, periodic pulse, single pulse or group pulse signal with adjustable number.

The fault insertion device is located between the signal interface inside the chip and the chip function module, and has a bidirectional signal path with the chip signal interface and the chip function module. Through the control of the internal communication interface of the product, the fault analog signal can be selectively inserted into the chip The signal flow between the signal interface and the chip function module.

The fault insertion device can also be located in the programmable logic device, and has a bidirectional signal path with the signal interface of the programmable logic device. Through the control of the internal communication interface of the product, the fault analog signal can be selectively inserted into the programmable logic device. signal flow between the signal interface and the chip signal interface.

The steps of fault analog signal insertion include:

(1) Determine the type of fault that needs to be inserted;

(2) Determine the fault location that needs to be inserted;

(3) Enable fault insertion, check whether the working conditions of the test object meet the expected results, and if not, carry out relevant records and analysis;

(4) Configure fault insertion to stop, check whether the working conditions of the test object meet the expected results, and if not, carry out relevant records and analysis.

The fault insertion device is a unit entity implemented in a hardware language description manner.

A fault insertion device provided by the present invention is characterized in that it includes a communication control module, a fault signal generation module and a fault insertion selection module, and the communication control module is connected to the fault signal generation module and the fault insertion selection module respectively; the communication control module controls the relevant The signal is transmitted to the fault signal generation module and the fault insertion selection module to determine the insertion type and insertion position of the fault analog signal, thereby simulating the failure of some or all of the internal functional units of the product.

Described communication control module comprises control signal interface and control register, CPU control bus carries out read and write operation to control register through control signal interface, control the fault signal type that fault signal generation module produces and the fault signal insertion enabling and fault insertion selection module of fault signal insert position.

The control registers include a fault signal generation control register and a fault insertion selection control register;

The fault signal generation control register includes:

A fault type control register for controlling the fault signal generation module to output the fault signal type;

an output pulse width control register for controlling the pulse width; and

Output pulse number control register for controlling the number of pulses;

The fault insertion selection control register controls the fault signal insertion enable and insertion position of the fault insertion selection module.

The fault signal generation module decodes the content of the fault type control register to obtain the control signal of the fault signal multiplexer, controls the multiplexer to gate the corresponding fault signal to be inserted, and sends it to the fault insertion selection module .

The fault insertion selection module decodes the content of the fault insertion selection control register to generate a selection control signal to control the insertion position of the fault signal and the insertion and recovery of the fault signal.

The fault signal generation module directly adopts the working clock of the chip, or uses the extra pins of the chip and the programmable logic device to introduce clocks from the outside to generate various types of fault analog signals.

The advantage of the present invention is that by installing a fault insertion device inside the product, comprehensive fault signal generation and insertion such as long height, long low, high impedance state, pulse signal, and periodic signal are realized inside the product, simulating partial failure of internal units of the product or all failures, the online test of product fault tolerance can be carried out, which provides a simple and convenient control interface for the control and insertion of fault signal types, improves the automation test degree of fault tolerance test, and then improves the efficiency of fault tolerance reliability test as a whole and reduce testing costs.

Description of drawings

FIG. 1 is a schematic block diagram of a fault insertion device embedded in a chip;

Fig. 2 is the schematic block diagram that realizes special-purpose chip fault insertion test by programmable logic device;

Fig. 3 is a schematic diagram of the interface of the fault insertion device;

Fig. 4 is a structural block diagram of a fault insertion device;

Fig. 5 is the type diagram of fault signal;

Fig. 6 is the structural block diagram of fault signal generation module;

Fig. 7 is the structural block diagram of fault insertion selection module;

Figure 8 is a flow chart of the fault insertion operation.

Detailed ways

As shown in Figure 1, we embed a fault signal insertion unit in the programmable chip inside the product or a dedicated chip designed by ourselves. The signal that needs to be inserted into the fault is processed by this module and then connected to the corresponding functional unit. Fault insertion processing is performed on the input and output signals of the chip interface and the signals between the internal functional modules of the chip, but it is not limited to use at the I/O pins of the chip, and can also be used for the insertion of internal signal faults of the chip, such as the internal modules of the chip The fault insertion of the interface signal between A and internal module B can also be used to simulate the failure of some functional modules of the chip, such as phase-locked loop, business processing module, CPU communication control module, etc. inside the chip.

As shown in Figure 2, for chips that cannot be directly embedded in fault insertion devices, we can introduce their interface signals into programmable logic devices, and implement fault insertion in programmable logic devices.

There is a two-way signal path between the fault insertion device and the signal interface of the chip and the chip function module. Through the control of the internal CPU control interface of the product, the fault analog signal can be selectively inserted into the signal between the signal interface of the chip and the chip function module. That is to say, the fault insertion device can arbitrarily choose to input signals to the chip pins in the direction of the chip function processing module, or output signals to the chip pins in the direction of the external interface of the chip, and between the internal function module A and the function module B of the chip. The fault signal is inserted on the internal interface signal of the Fault insertion devices are currently described in hardware languages such as VHDL and Verilog HDL, and are embedded in programmable logic chips or self-designed chips to generate unit entities.

As shown in Figure 3, the fault insertion device interface includes:

(1) Address/data input bus, CPU control bus such as chip selection and read and write control.

(2) Working clock signal input.

(3) To be inserted into the fault signal input.

(4) The signal output after being processed by the fault processing unit.

Controlled by the fault insertion device is to send out the original signal, or insert a simulated fault signal on the signal.

As shown in Figure 4, the fault insertion device includes a communication control module, a fault signal generation module, and a fault insertion selection module.

The communication control module part includes address, data bus, chip selection, read and write control and other CPU control signal interfaces, fault signal generation control registers, fault insertion selection control and other control registers. This part can be regarded as a functional component inside the product. By directly using the communication interface of the internal chip of the product, the internal control register of the fault insertion device can be read and written. By controlling the content of the internal control register of the fault insertion device, the type of fault signal generated by the fault signal generation module is controlled, and the fault signal insertion of the fault insertion selection module is enabled and the insertion position is controlled.

As shown in Figure 5, the fault signal generation module generates the following fault modes according to the content of the fault signal generation control register in the communication control module:

(1) The level is high;

(2) The level is long and low;

(3) The high-impedance state of the signal line;

(4) Periodic pulse signal with adjustable pulse width;

(5) Single pulse signal with adjustable pulse width;

(6) A group pulse signal with adjustable number and adjustable pulse width.

As shown in Figure 6 and Figure 7, the fault signal generation module can directly use the working clock of the chip, or use the redundant pins of the chip and the programmable logic device to introduce the clock from the outside, and divide it internally. The pulse width variation range can be conveniently set as required. The fault signal generation control register includes fault type control register, output pulse width and output quantity control register. The corresponding fault signal to be inserted is controlled and selected by decoding the fault type control register. When outputting a pulse signal, the output pulse width and output quantity control register controls the width of the pulse and the number of pulses. The fault signal generation module sends the generated fault signal to one end of the multiplexer (MUX) in the fault insertion selection module, and the fault insertion selection module controls whether to insert the fault signal on the interface signal.

The fault insertion selection module decodes the content of the fault insertion selection control register in the CPU communication control interface to generate a selection control signal, which is sent to the control terminal of the multiplexer on the interface to determine the insertion position of the fault signal and output on the interface signal The original signal or the fault signal, so as to realize the insertion and restoration of the fault signal.

In this way, we can easily realize the fault insertion of the chip interface by writing the internal register of the fault insertion device, as shown in Figure 8, and the operation steps are as follows:

1. Configure the test environment and prepare for the test. At this time, the product is in normal working condition and the business is normal.

2. Through the CPU control interface of the chip to be inserted into the fault, and the communication control module of the fault insertion device, the relevant setting information is written into the fault insertion selection control register of the internal fault insertion selection module of the fault insertion device, and the fault to be inserted is configured. position, that is, on which signal to perform fault insertion.

3. Through the CPU control interface of the faulty chip to be inserted and the communication control module of the fault insertion device, information is transmitted, and the relevant setting information is written into the fault signal generation control register of the internal fault signal generation module of the fault insertion device, and the fault to be inserted is configured. Type (High, Low, Hi-Z, Pulse, etc.). If a pulse fault signal is inserted, it is also necessary to configure the pulse high and low level width control register and pulse quantity control register of the fault signal generation module.

4. Through the CPU control interface of the fault chip to be inserted and the communication control module of the fault insertion device, information is transmitted, and the relevant setting information is written into the fault insertion selection control register of the internal fault insertion selection module of the fault insertion device to enable fault insertion.

5. Check whether the working condition of the test object meets the expected results, and if it does not meet the relevant records and analysis.

6. Through the CPU control interface of the faulty chip to be inserted and the communication control module of the fault insertion device, information is transmitted, and the relevant setting information is written into the fault insertion selection control register of the internal fault insertion selection module of the fault insertion device, and the fault insertion is stopped. If the pulse fault signal is inserted, the fault insertion will be stopped automatically after the pulse output is completed.

7. Check whether the working condition of the test object meets the expected results, and if it does not meet the relevant records and analysis.

8. To continue the test, repeat steps 1-7 to perform the next fault insertion test.

As can be seen from the above detailed description of the present invention, the method of the present invention can improve the testability of the single board, enrich the fault tolerance test method, and provide a simple and powerful online fault insertion means for the fault tolerance test, which can complete Simulation of various types of signal faults as follows,

(1) The length and height of the signal line;

(2) The length of the signal line is low;

(3) The signal line is disconnected (high resistance);

(4) Signal line single pulse insertion;

(5) Signal line group pulse signal insertion;

(6) The state of the signal line oscillates continuously;

In this way, the failure simulation of partial failure or complete failure of internal chips and functional units of the product is completed, and no additional error signal generation unit is required, which reduces the cost; the inserted fault is microscopically controllable and has good repeatability, which can ensure that the expected error signal is inserted every time The fault signal of the second insertion is consistent. It can well solve the problems of low control accuracy when external manual faults are inserted, poor consistency of fault signals, inconsistent signal line status and expectations (such as clock signals cannot be completely pulled down), etc. The test effect is improved; the operability is good, there is no need for manual operations such as placing probes and welding, and the test efficiency is improved; it is easy to use, and the software realizes the control of the fault insertion device module through the CPU interface of the fault insertion device. Which signal is used for fault insertion, the type of fault inserted, the duration of the fault inserted, and the packaged test items can be well integrated into automated testing; the fault insertion device module has good portability, and a core error signal generation module inside it, which generates The signal can be shared by all pins, occupies very little resources, and has nothing to do with the functions realized by the board and the logic itself. As long as the internal chip of the board has a CPU interface, this method can be used.

Claims (12)

1, a kind of product fault-tolerance method of testing, this method is at the dissimilar fault simulation signal of the inner generation of product, by control to fault simulation signal, determine the insertion type and the insertion position of fault simulation signal automatically, thus analog equipment built-in function cell mesh or all inefficacies.

2, product fault-tolerance method of testing according to claim 1, it is characterized in that: described fault simulation signal inserts device by fault and produces, and fault simulation signal comprises: grow tall, long low, high-impedance state, recurrent pulse, monopulse or the adjustable burst of pulses signal of number.

3, product fault-tolerance method of testing according to claim 2, it is characterized in that: fault is inserted device between the signaling interface and chip functions module of chip internal, and and has the two-way signaling path between chip signal interface and the chip functions module, by the control of product internal communication interface, fault simulation signal can insert the signaling interface of chip and the signal flow between the chip functions module selectively.

4, product fault-tolerance method of testing according to claim 2, it is characterized in that: fault is inserted device and is arranged in programmable logic device (PLD), and and has the two-way signaling path between the signaling interface of programmable logic device (PLD), by the control of product internal communication interface, fault simulation signal can insert the signaling interface of programmable logic device (PLD) and the signal flow between the described chip signal interface selectively.

5, product fault-tolerance method of testing according to claim 1 is characterized in that: the step that fault simulation signal inserts comprises:

(1) definite fault type that needs insertion;

(2) definite abort situation that needs insertion;

(3) enable fault and insert, whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis;

(4) config failure inserts and to stop, and whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis.

6, according to claim 3 or 4 described product fault-tolerance method of testings, it is characterized in that: it is the unit entity that adopts the describing mode realization of hardware language that described fault is inserted device.

7, a kind of fault is inserted device, it is characterized in that comprising communication control module, fault-signal generation module and fault insertion selection module, and communication control module inserts with fault-signal generation module and fault respectively selects module to link to each other; Associated control signal is passed to the fault-signal generation module to communication control module and fault is inserted the selection module, with the insertion type and the insertion position of definite fault simulation signal, thus analog equipment built-in function cell mesh or all inefficacies.

8, fault according to claim 7 is inserted device, it is characterized in that: described communication control module comprises control signal interface and control register, cpu control bus carries out read-write operation by the control signal interface to control register, and fault-signal type that the control fault signal generator module produces and fault are inserted the fault-signal insertion of selecting module and enabled and the insertion position.

9, fault according to claim 8 is inserted device, it is characterized in that: described control register comprises that fault-signal produces control register and fault is inserted the selection control register;

Described fault-signal produces control register and comprises:

The fault type control register that is used for control fault signal generator module output fault-signal type;

The output pulse width control register that is used for the gating pulse width; With

The output number of pulses control register that is used for gating pulse quantity;

Described fault is inserted the fault-signal insertion of selecting the control register control fault to insert the selection module and is enabled and the insertion position.

10, fault according to claim 9 is inserted device, it is characterized in that: described fault-signal generation module is deciphered the content of fault type control register, obtain the control signal of fault-signal traffic pilot, control traffic pilot gating is inserted into fault-signal accordingly, and sends into fault and insert in the selection module.

11, fault according to claim 9 is inserted device, it is characterized in that: described fault is inserted the content of selecting module that fault is inserted the selection control register and is deciphered, produce and select control signal, the insertion position of control fault signal and the insertion of fault-signal and recovery.

12, fault according to claim 10 is inserted device, it is characterized in that: described fault-signal generation module directly adopts the work clock of chip, or utilizes chip and the unnecessary pin of programmable logic device (PLD) to introduce the various types of fault simulation signals of clock generating from the outside.

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