CN1855880A - Data read/write device and method - Google Patents

Abstract

The invention discloses a device for reading and writing data, comprising: a write request device for generating a write request, a write address and write data; a read request device for generating a read request and a read address; two memories for storing data ; two storage controllers, used to control the read and write operations of the two memories respectively; the arbiter, used to control the storage controller to control the storage controller according to the arbitration rules, the information generated by the write request device and the information generated by the read request device The memory implements read operations and/or write operations. The capacity and type of the two memories are the same. The invention also discloses a data reading and writing method. According to the present invention, it can be ensured that read and write applications at any time can obtain their respective available memory, ensure that the read and write operations can be responded immediately, and the process of data input and data output will not be disturbed or interrupted, thereby improving the data processing capability.

Description

A data reading and writing device and reading and writing method thereof

technical field

The invention relates to a data processing technology, in particular to a data reading and writing device and a reading and writing method thereof.

Background technique

With the development of information and communication technology, the requirements for data processing capabilities are getting higher and higher. In network communication, the data processing function can be completed by the network processing chip.

The network processing chip can complete the message exchange between each port. The network processing chip includes two types, one is a chip for processing variable-length messages, such as an Ethernet switch chip, an L3 (layer 3) switch chip, and a router chip. The other is a chip that deals with fixed-length cells, such as ATM switching chips. When the chip processes fixed-length cells or variable-length cells, it needs not only large-capacity storage capacity to cope with temporary storage of packets under network congestion or uneven traffic conditions, but also high-bandwidth capabilities to support high-speed line connections between ports. Fast forwarding. This storage capability and bandwidth capability depend on the data read-write device and data read-write method on the chip.

In the prior art, there are many kinds of data reading and writing devices on the network processing chip, and their characteristics are briefly described below.

1) Built-in SRAM (Static Random Access Memory) integrated in the chip. The advantage of this memory scheme is simple operation with low overhead and high available bandwidth. However, this solution is limited by the upper limit of the built-in SRAM process frequency. In addition, the high cost of this memory makes its application range smaller.

2) Built-in DRAM (Dynamic Random Access Memory) integrated in the chip. Compared with the built-in SRAM, the built-in DRAM can provide a large-capacity low-cost storage capacity. However, this memory solution has high requirements on chip processing technology, and only a few chip manufacturers can provide it, and the on-chip capacity is still limited, so the application range of the on-chip integrated DRAM solution is also relatively small. In addition, the operation of DRAM is complex and expensive, and the available bandwidth is low, so it is difficult to meet the requirement of high bandwidth.

3) External SRAM. This solution eliminates the cost problem of on-chip storage capacity, but the external SRAM is still expensive, which limits its application range. There is an urgent need to maximize storage bandwidth.

4) External DRAM. External DRAM includes PSRAM (pseudo-static random access memory), SDRAM (synchronous random access memory), DDR SDRAM (double-rate dynamic synchronous random access memory), DDR2 SDRAM (second generation double-rate dynamic synchronous random access memory), RLDRAM (Low Latency Dynamic Synchronous Random Access Memory) and FCRAM (Fast Cycle Random Access Memory) and other varieties, among which DDR SDRAM and DDR2 SDRAM are the mainstream devices in various chips. All external DRAMs have the problem of complex operation, high overhead and low available bandwidth, and it is often difficult to meet high bandwidth requirements.

To sum up, any of the above-mentioned storage systems has a need to further increase the bandwidth, especially for DRAM storage systems with low cost, complex operation and high overhead, the need for increased bandwidth is even more urgent.

Contents of the invention

In view of the above-mentioned defects of the prior art, the object of the present invention is to provide a data reading and writing device and a reading and writing method thereof, which have lower cost, higher bandwidth and improved data reading and writing capabilities.

The present invention is achieved through the following technical solutions. The present invention provides a data reading and writing device, comprising:

Write request device, used to generate write request, write address and write data;

A read request device is used to generate a read request and a read address;

Two memories for storing data;

Two memory controllers are used to control the read and write operations of the two memories respectively;

The arbiter is used to control the storage controller to perform read or/and write operations on the memory according to the arbitration rules, the information generated by the write request device and the information generated by the read request device.

The capacity of the two memories is the same.

The two memories are of the same type.

The memory is double rate dynamic synchronous random access memory.

The said arbitration rules are:

When there is only write operation, the arbiter controls the memory controller to write data into any memory;

When there is only a read operation, the arbiter controls the storage controller to read data from the memory;

When there are both write operations and read operations, the arbiter controls the storage controller to read data from the memory and write data to another memory.

The present invention also provides a method for reading and writing data, including:

A. The arbitrator obtains write application information and/or read application information;

B. The arbitrator processes the read application information and/or read application information according to the arbitration rules.

The write application information includes data to be written and an address to be written, and the read application information includes address information and actual storage location information.

Described step B further comprises:

When there is only write operation application information, the arbiter controls the storage controller to write data into any memory according to the write application information;

When there is only read operation application information, the arbiter controls the storage controller to read data from the memory according to the read operation application information;

When there are both write operation application information and write operation application information, the arbiter controls the storage controller to read data from the memory according to the read operation application information, and writes the data to be written into another memory according to the write application information.

The clock cycle used by the storage controller for the read operation is equal to the clock cycle used for the write operation.

When the double rate dynamic synchronous random access memory is used, the clock cycle used by the memory controller for the read operation and the clock cycle used for the write operation are 11 clock cycles.

The operation process and the arbitration algorithm of the present invention are very simple and reliable, and have strong data read and write capabilities, thereby improving the bandwidth.

Description of drawings

Fig. 1 shows the embodiment utilizing the data reading and writing device of the present invention;

Fig. 2 shows the write operation timing diagram of the present invention;

Fig. 3 shows the timing diagram of the read operation of the present invention;

Fig. 4 shows the timing diagram of the DDR SDRAM of 2.5 clock cycles using the CAS parameter of the present invention;

Fig. 5 shows the flow chart of writing data operation according to the embodiment shown in Fig. 1;

FIG. 6 shows a flowchart of an operation for reading data according to the embodiment shown in FIG. 1 .

Detailed ways

In order to make it easier for those skilled in the art to understand and realize the present invention, the embodiments of the present invention are described in conjunction with the accompanying drawings.

The invention provides a device for reading and writing data, comprising: a write request device for generating a write request, a write address and write data; a read request device for generating a read request and a read address; two memories for storing data ; two storage controllers, used to control the read and write operations of the two memories respectively; an arbiter, used to control the storage controller to perform the operation according to the arbitration rules, the information generated by the write request device and the information generated by the read request device The memory implements read operations and/or write operations. Preferably, the two memories have the same capacity and type.

In the following embodiments, the current mainstream and lowest-cost off-chip DDR SDRAM memory is taken as an example, combined with an actual chip, to describe the data reading and writing device and data reading and writing method of the present invention in detail.

As shown in Figure 1, utilize the chip of data reading and writing device of the present invention to comprise: at least one RxFIFO (input buffer), at least one TxFIFO (output buffer), input end data strobe, output end data strobe, service Processors and transponders, two memories, two memory controllers and an arbiter. Wherein, at least one RxFIFO (input buffer), input data strobe, business processing and transponder constitute a write request device; at least one TxFIFO (output buffer), output data strobe, business processing and transponder constitute Read request device.

RxFIFO is used to temporarily store data received from external ports, and one RxFIFO can be configured on each input port. In the present invention, when the data frame is stored in the memory, it needs to be cut into fixed lengths, such as 128 bytes. If the network switching chip processes variable-length messages, such as Ethernet messages, the RxFIFO also temporarily stores the data. Complete the segmentation of the data frame. For example, the size of the segmentation can be divided into one block per 128 bytes, and the message or frame tail of less than 128 bytes is also divided into one piece. The segmentation process is realized by reading out data blocks . If the network switching chip processes the message of equal-length cells, such as ATM cells, the data block may not be segmented, and the read and write operations are directly performed according to the length of the cells.

TxFIFO is used to temporarily store the data to be sent, and one TxFIFO can be configured on each sending port. In the present invention, although the data frame is cut into fixed-length data blocks and stored in the memory, and the output process is also read into the TxFIFO in units of data blocks, the data blocks are stored continuously in the TxFIFO, which is equivalent to completing After splicing the data blocks, the TxMAC (media controller at the sending end) only needs to send them sequentially and continuously, and the segmentation of the data blocks will not have any impact on the sending.

Generally speaking, RxFIFO and TxFIFO need to pass through the physical layer and data link layer unit to receive and send data with the external network. The depth of RxFIFO and TxFIFO needs to be designed to prevent overflow when the network speed is high and the internal processing speed of the chip is insufficient. mistake.

The function of the data strobe at the input end is to read out the data of the selected RxFIFO and send it to the write data bus under the control of the polling controller at the input end. The input data strobe is designed as a multiplex switch.

The function of the data strobe at the output end is to connect the read data bus to the data input end of the selected TxFIFO under the control of the polling controller unit at the output end, so as to complete the writing operation of the TxFIFO.

The service processing and transponder submits write application information and read application information to the arbitrator. The service processing and transponder includes an input terminal polling control, a service processor, an output queue scheduler, and an output terminal polling controller.

The function of the polling controller at the input end is to poll the status of data reception in all RxFIFOs, and apply for an available memory space block to the memory manager for each new data frame, and when each block is a fixed length, the memory The space block can be represented by the starting address of the memory. After applying for the available memory space, the input terminal polling controller sends a write operation request to the arbitrator, and at the same time controls the input terminal data strobe to send the data of RxFIFO to the write data On the bus, the arbiter completes the data write operation, and each write operation completes a data block, such as 128 bytes. After the write operation is completed, the arbiter will return an actual storage location information, and the actual storage location information is the serial number of the memory. The actual storage location information will be used when the message is read. After one or more data block writing operations, the writing of a complete data message can be completed. The input terminal polling controller combines the memory address information and actual storage location information of the data frame into data frame control information, and sends it to The business processor performs business processing.

The service processor is used to complete the service processing of data.

The function of the output queue scheduler is to provide multiple output queues for the output port and provide priority scheduling services among the queues.

The service processor and the output queue scheduler are the business units of data processing. After these two parts are processed, the output port control information of each data frame can be obtained, which is consistent with the memory address of the data frame provided by the polling controller at the input end. , the actual storage location information, etc. constitute the control information of the data frame to be sent, which is used for sending the message. In addition, when a message enters the output buffer, data frames may need to be discarded due to congestion and other reasons, and the output queue scheduler needs to use the control information of the discarded message to submit a storage release application to the storage manager so that the block storage can be used for new Data frame storage.

The function of the polling controller at the output terminal is to poll the status of the TxFIFO. When it is found that there is at least one free storage block in the TxFIFO, it will apply to the output queue scheduler for the data frame information of the port to be sent, so as to obtain the output message control Block information, and then, according to the memory address and actual storage location information therein, submit a read data application to the arbiter, and control the output data strobe to read and write the data on the read data bus into the TxFIFO, each operation 1 data block, such as 128 bytes. If the length of the data frame to be sent exceeds the size of 1 data block, it is necessary to poll the port multiple times and perform multiple operations. When all the data blocks of a data frame have been read out, an application for releasing the cache is sent to the storage manager, so that the cache can be used for storing new data frames.

The function of the memory manager is to maintain the message cache, that is, to maintain the use of the memory. Message maintenance is operated through the "memory usage table": all available memory is divided into the smallest granularity that can be allocated, and each granularity unit is assigned an address identifier and configured with a mark whether to use it. When the input terminal polls the controller to apply for a new data frame storage space, the storage manager returns the address identifier of an unused cache block and marks the relevant address control information as "used", when the output queue scheduler and the output terminal When the polling controller returns the freed address ID, the storage manager modifies the control information about the address to "unused" for re-allocation. Although the external storage manager does not directly deal with the storage, all the allocation and use of the storage space are controlled by the storage manager.

The core apparatus and method of the present invention are set forth below.

The two memories are called memory group A and memory group B respectively, and are used to store data.

Memory group A and memory group B are two sets of DDR SDRAM device groups with the same configuration. The same configuration means that the bit width, speed and capacity are the same, such as two groups of 64bit@133MHz DDR SDRAM devices with the same configuration. In order to obtain a memory bit width exceeding the standard bit width (8bit, 16bit, 32bit), multiple DDR SDRAMs with a standard bit width can be configured in parallel. The parallel configuration needs to connect the instruction bus and data bus of the DDR SDRAM in parallel, so that on the controller side Unified control. For example, the 64bit bit width can be implemented in parallel with four 16bit bit wide DDR SDRAMs or two 32bit bit wide DDR SDRAMs.

The two external memory controllers are called memory group A controller and memory group B controller respectively. The memory group A controller controls the memory group A to read and write, and the memory group B controller controls the memory group B to read and write. The memory group A controller and the memory group B controller are two sets of DDR SDRAM read and write controllers with identical functions, but they are completely independent in operation, that is, each controller can complete the read and write operations independently without any interference between them. Influence and pinning, the coordination between the two controllers is controlled by the arbiter. DDR SDRAM controller completes standard DDR SDRAM read and write operations, including Bank (block) activation before read and write operations, Bank read and write command sending, Bank pre-charging, Bank refreshing, etc.

The arbiter can simultaneously or separately receive the write data request from the input end and the read data request from the output end. When receiving the write data application from the input terminal and the read data application from the output terminal at the same time, it can control one DDR SDRAM controller to complete the operation of writing data on the write data bus to the memory, and control the other DDR SDRAM controller to complete the memory read operation. And put the read data on the read data bus. When only receiving the write data application from the input end, it can control any DDR SDRAM controller to complete the operation of writing the data on the write data bus into the memory; The corresponding DDR SDRAM controller completes the memory read operation and puts the read data on the read data bus.

Based on the above, for the present invention, the features of the present invention are as follows.

1. The present invention not only supports external storage of fixed-length data blocks, but also supports external storage of variable-length data blocks. If the variable-length message is to be processed, the fixed-length segmentation is completed in the input buffer, and the splicing operation is completed in the output buffer. If the fixed-length message is to be processed, the length of the read and write operation can be set to be the same as The length corresponding to the length of the fixed-length message does not require segmentation.

2. After passing through the data processing process of the present invention, multiple external network ports of the data reading and writing device can be multiplexed into a sequence of write memory operations and a sequence of read memory operations. Each operation in the sequence completes a fixed-length data block read or write operation.

3. Use two completely independent DDR SDRAMs to support data read memory sequence and write memory sequence operation applications. The two DDR SDRAMs have exactly the same storage space and address space allocation.

4. The addresses of the two channels of DDR SDRAM are uniformly maintained, and the same address unit is allocated, used and recycled at the same time, so that each data to be stored is allocated twice the memory space of the capacity, but each data to be stored is only written into one channel of DDR SDRAM Among them, the utilization rate of the memory is up to 50%, and which way to write DDR SDRAM is determined by the arbitration rules.

Unified address maintenance means that the same address unit in two DDR SDRAMs is regarded as a management unit in the storage manager, and only one address identifier is assigned. The storage manager does not know that there are two identical DDR SDRAMs. , so each time an address identifier is allocated to a new data frame, the address units in the memory groups A and B are actually allocated at the same time, which is equivalent to obtaining twice the storage space for each new data frame. When the data frame uses the storage space, it can only use 50% of it, and which part is used is controlled by the arbitration rules. When address recovery is performed, this single address identifier is also used, which is equivalent to the simultaneous recovery of address units in groups A and B.

The arbitration rule refers to: if there is a read request and a write request at the same time, the read request is allocated to the required DDR SDRAM, and the write request is allocated to another DDR SDRAM; if there is only a read request, the The read request is allocated to the required DDR SDRAM; if there is only a write request, it can be allocated to any DDR SDRAM. After the response to the write request operation is completed, the actual storage location information of the data must be returned to the input terminal polling controller for use when the output side reads the request. The actual storage location information refers to the number of the DDR SDRAM, indicating that the data is stored Information in which group of DDR SDRAM.

In order to ensure that the arbitration rule of the present invention is realized, the access timing of the DDR SDRAM will also be structured, so that the read operation instruction cycle and the write operation instruction cycle are equal in length under the condition that the bandwidth of the DDR SDRAM is fully utilized in both the read and write operations, thereby constructing Pipeline DDR SDRAM access operation access mode ensures the synchronization of read and write operations.

The operation timing of DDR SDRAM is described in detail below.

An embodiment of the present invention reads and writes a data block of 128 bytes at a time. In two groups of DDR SDRAMs, each group's bit width is 64 bits, and each data block uses all 4 Banks of each DDR SDRAM.

As shown in Figure 2, 4 Banks of 128 bytes written into 64bit DDR SDRAM are designed to use 11 clock cycles. In Figure 2, clk is the main clock of DDR SDRAM, cmd is the command sent to DDR SDRAM, ba is the Bank number sent to DDR SDRAM, and dq[63:0] is the data sent to DDR SDRAM.

The instructions sent to DDR SDRAM include NOP empty operation, N empty operation, A activation Bank operation, W write Bank operation, the Bank number when the Bank operation is involved is provided at the same time as the instruction is sent, and the Bank number is 0, 1, 2, 3, Corresponding to 4 banks of DDR SDRAM. When the data line dq is marked as 0, 1, 2, 3, it means the data sent to Bank No. 0, 1, 2, 3.

The write operation uses 11 clock cycles and is measured from cmd. According to the present invention, no matter whether it is a read operation or a write operation before the write operation, after the start of the write operation, it needs to consume 11 cycles before the next read operation can be initiated. or write cycle. If the written data is less than 128 bytes, the 11 clock cycles will not all be used up, but to keep the pipeline cycles equal, the remaining clock cycles remain idle.

According to the speed of DDR SDRAM devices, as shown in Figure 3, reading 128 bytes from 4 Banks of 64bit DDR SDRAM will consume 10 to 11 clock cycles. In Figure 3, clk is the main clock of DDR SDRAM, cmd It is the command sent to DDR SDRAM, ba is the Bank number sent to DDR SDRAM, and dq[63:0] is the data sent to DDR SDRAM.

The instructions sent to DDR SDRAM include NOP empty operation, N empty operation, A activate Bank operation, R read Bank operation, and the Bank number when the Bank operation is involved is provided at the same time as the instruction is sent, and the Bank number is 0, 1, 2, 3, Corresponding to 4 banks of DDR SDRAM. When the data line dq is marked as 0, 1, 2, 3, it means the data of Bank No. 0, 1, 2, 3 returned by DDR SDRAM.

The above read operation process consumes 10 clock cycles, because the DDR SDRAM whose CAS (Chinese?) parameter is 2 clock cycles is used, that is, the response of dq data is delayed by 2 clock cycles compared with the R operation command. Like the write operation, the consumption of 10 clock cycles is measured from the cmd. No matter whether the read operation is a read operation or a write operation before this read operation, after the start of this write operation, it takes 10 cycles to initiate the next read or write operation. write cycle.

As shown in Figure 4, if it is a DDR SDRAM device with a CAS parameter of 2.5 clock cycles, it needs to consume 11 clock cycles. In Figure 4, clk is the main clock of DDR SDRAM, and cmd is the command sent to DDR SDRAM. ba is the Bank number sent to DDR SDRAM, and dq[63:0] is the data sent to DDR SDRAM.

The instructions sent to DDR SDRAM include NOP empty operation, N empty operation, A activate Bank operation, R read Bank operation, and the Bank number when the Bank operation is involved is provided at the same time as the instruction is sent, and the Bank number is 0, 1, 2, 3, Corresponding to 4 banks of DDR SDRAM. When the data line dq is marked as 0, 1, 2, 3, it means the data of Bank No. 0, 1, 2, 3 returned by DDR SDRAM.

Using a DDR SDRAM device with a CAS parameter of 2.5 clock cycles, the dq data appears 2.5 clock cycles later than the R operation command, so the entire read command consumes 11 clock cycles in total, and these 11 clock cycles are measured from cmd. Regardless of whether it is a read operation or a write operation before this read operation, after the start of this write operation, it takes 11 cycles before the next read or write operation cycle can be initiated.

Similarly, if you use a DDR SDRAM with a CAS parameter of 3 clock cycles, you can still get 11 clock read cycles.

In order to construct a DDR SDRAM access pipeline, the clock cycle used for the write operation must be equal to the clock cycle used for the read operation. Since the write cycle is 11 clock cycles, DDR with a read cycle less than or equal to 11 clock cycles can be used SDRAM, but the read cycle must be unified into 11 clock cycles, which is the same as the write cycle, so that DDR SDRAM can be operated with a pipeline of 11 clock cycles. If the original read operation is 10 clock cycles, it needs 1 clock cycle in the pipeline operation time. If the data read out is less than 128 bytes, the 11 clock cycles will not be completely used up, but in order to keep the pipeline cycles equal, the remaining clock cycles remain idle.

The arbiter receives the read and write requests from the input and output terminals, and after performing operation arbitration and DDR SDRAM allocation, it starts the DDR SDRAM in an 11-clock cycle pipeline mode, so that the two pipeline cycles are completely synchronized, and any one pipeline has no instructions. Idle, and start the next operation cycle after the next pipeline cycle arrives.

It should be noted that the above timing definition refers to the timing between the DDR SDRAM controller and the DDR SDRAM device. In order to achieve the pipeline timing and bandwidth on this interface, the arbiter and the DDR SDRAM controller need to consider their respective circuit processing delays, such as read Write application arrival time, arbitration operation time, start command time, etc. The specific delay and control sequence are considered in the circuit design, which are not the key content of the present invention, and will not be discussed in this paper.

The above is a DDR SDRAM operation pipeline design with high bandwidth utilization rate, and the bandwidth utilization rate reaches 8/11. If the required bandwidth is not high, you can also consider increasing the pipeline cycle to 12 or 13 clock cycles, so that you can use DDR SDRAM devices with slightly lower performance indicators to reduce costs. In addition, it is also possible to change the amount of data written into each Bank, such as increasing from 4 sets of data written in each Bank to 8 sets of data, etc., so that the entire pipeline is extended to 19 cycles but the utilization rate is increased to 16/19 . Only the number of pipeline cycles and the length of data reading and writing do not constitute a substantive improvement to the present invention.

The data reading and writing device of the present invention has been discussed in detail above, and the data reading and writing method of the present invention will be described below.

The general idea of the data reading and writing method of the present invention is: the arbitrator obtains the write application information and/or the read application information; the arbitrator processes the read application information and/or the read application information according to arbitration rules. The write application information includes data to be written and an address to be written, and the read application information includes address information and actual storage location information. The clock cycle used by the storage controller for the read operation is equal to the clock cycle used for the write operation.

FIG. 5 shows a flowchart of an operation for writing data according to the embodiment shown in FIG. 1 . As shown in FIG. 5, the write operation flow is described below.

In step 51, the input end polling controller polls the status of all input buffers; in step 52, if the input end polling controller finds that there is newly received data in the input buffer, then execute step 53, otherwise execute Step 51, continue to poll the status of the input buffer.

In step 53, the input terminal polling controller applies for the storage manager for the available storage space of the storage device for the received data.

In step 54, the input polling controller controls the input data strobe to place the data in the input buffer on the write data bus.

In step 55, the arbiter controls the storage controller to write the data on the write data bus into the available space of the storage according to the arbitration rules.

The arbitration rules refer to: when the arbitrator finds that there is only a write operation application, the arbiter controls the storage controller to write data into any memory according to the write application information; The information controls the storage controller to read data from the memory; when there are both write operation requests and write operation requests, the arbiter controls the storage controller to read data from the memory according to the read application information, and controls the storage controller to read data from the memory according to the write application information. Data is written to another memory.

In step 56, the arbiter returns the actual storage location information to the input polling controller.

In step 57, the input polling controller sends the actual storage location information to the service processor.

FIG. 6 shows a flowchart of an operation for reading data according to the embodiment shown in FIG. 1 . As shown in FIG. 6 , the flow of reading data will be described in detail below.

In step 61, the output polling controller polls the status of all output buffers.

In step 62, if the polling controller at the output end finds that there is a free storage space block in the output buffer, it executes step 63; otherwise, it executes step 61 to continue polling the status of the output buffer.

In step 63, the output polling controller applies to the output queue scheduler for the data frame information of the output buffer to be sent.

In step 64, the polling controller at the output end obtains the external storage address and actual storage location information of the data according to the data frame information to be sent, and sends the external storage address and actual storage location information to the arbitrator.

In step 65, the arbiter controls the storage controller to read data according to the above arbitration rules, external storage address and actual storage location information, and puts the data on the read data bus.

In step 66 , the polling controller at the output terminal controls the data strobe at the output terminal to read and write the data on the read data bus into the output buffer.

In step 67, the output terminal polling controller sends an application for releasing storage space to the storage manager.

The present invention uses 2-way parallel DDR SDRAM, which can make the total bit width reach the same situation as the bit width of 1-way DDR SDRAM, and the bit width of each way is only half of the total bit width, so the bandwidth utilization rate of small messages is very high, The bandwidth performance requirements for small packets are guaranteed, thereby reducing the difficulty of system design.

In addition, the operation process and arbitration algorithm of 2-way DDR SDRAM are simple and reliable.

Through the arbitration process of the present invention, it can be guaranteed that the read and write applications at any time can obtain the respective available DDR SDRAM, and the read and write operations can be responded immediately, and the data input and data output processes will not be disturbed or interrupted.

Since the input process and the output process can always have their own available DDR SDRAM resources, it is logically equivalent to configuring independent DDR SDRAM for the input and output processes. In this way, when calculating whether the bandwidth provided by DDR SDRAM can meet the needs of the respective process bandwidth, the uncertainty of available resources is completely removed, the calculation process is simplified, and the calculation results can be completely trusted.

It should also be noted that between the input and output end data strobes and the arbitrator and between the input and output end polling controllers and the arbitrator can be connected in a FIFO manner, which will make the arbiter and the business processing and transponder The coordination relationship between them is more flexible, and the control timing is easier to design. Using FIFO to replace the direct connection relationship does not change the core design structure of the storage control system, and does not constitute a substantial improvement to the present invention.

In addition, several FIFOs can also be multiplexed between the input and output data gates and the arbiter, and the arbiter can obtain read and write data by polling multiple FIFOs, thereby enhancing the service and data reading and writing device. Design flexibility. Replace direct connection relationship or single FIFO connection with a plurality of FIFOs, do not change the core design structure of 2-way DDR SDRAM, do not constitute substantial improvement to the present invention.

The present invention takes DDR SDRAM as an example to describe the basic idea of the present invention in detail. The present invention can be applied to all types of memory, including built-in SRAM, built-in PSRAM, built-in DRAM, external SRAM, external PSRAM, external SDRAM, external DDR SDRAM, external DDR2 SDRAM, external RLDRAM (low-latency dynamic synchronous random access memory), external FCRAM (fast cycle random access memory), etc., and any type of memory that may appear in the future, changing the memory type only needs to adjust the pipeline The operation sequence is sufficient, and does not constitute a substantive improvement to the present invention.

Although the present invention has been described by the embodiments, those of ordinary skill in the art know that, without departing from the spirit and essence of the present invention, the present invention can have many modifications and variations, and the scope of the present invention is defined by the appended rights Requirements to limit.

Claims (10)

1. data read-write equipment comprises:

The write request device is used to produce write request, write address and write data;

The read request device is used to produce read request and reads the address;

It is characterized in that described data read-write equipment also comprises:

Two memories are used to store data;

Two storage controls are used for controlling respectively the read-write operation of two memories;

Moderator is used for according to arbitration rules, writes and please install the information Control storage control that the information that produced and read request device produced described memory is implemented read operation or/and write operation.

2. data read-write equipment according to claim 1 is characterized in that, described two its capacity of memory are identical.

3. data read-write equipment according to claim 1 is characterized in that, described two its types of memory are identical.

4. according to claim 1,2 or 3 described data read-write equipments, it is characterized in that described memory is a Double Data Rate dynamic synchronous random reference to storage.

5. data read-write equipment according to claim 1 is characterized in that, described arbitration rules are:

When only write operation being arranged, moderator control store controller writes data in arbitrary memory;

When only read operation being arranged, moderator control store controller sense data from memory;

When existing write operation also has read operation, moderator control store controller sense data from memory, and data are write in another memory.

6. a data read-write method is characterized in that, comprising:

A, moderator obtain to write application information and/or read application information;

B, moderator are handled according to arbitration rules and are read application information and/or read application information.

7. data read-write method according to claim 6 is characterized in that, the described application information of writing comprises and treat write data and treat write address that the described application information of reading comprises address information and actual storage locations information.

8. according to claim 6 or 7 described data read-write methods, it is characterized in that described step B further comprises:

When the write operation application information was only arranged, moderator write data in arbitrary memory according to write operation application information control store controller;

When the read operation application information was only arranged, moderator was according to read operation application information control store controller sense data from memory;

When existing write operation application information also had the write operation application information, moderator was according to read operation application information control store controller sense data from memory, and will treat that according to the write operation application information write data writes in another memory.

9. data read-write method according to claim 8 is characterized in that, the described employed clock cycle of storage control read operation equated with the clock cycle that write operation uses.

10. data read-write method according to claim 9 is characterized in that, when using Double Data Rate dynamic synchronous random reference to storage, described employed clock cycle of storage control read operation and clock cycle that write operation uses are 11 clock cycle.

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