CN1855786B - A branch signal recovery method and device based on non-integer leakage rate - Google Patents

Abstract

The invention discloses a method and device for processing non-integer leakage rate when branch signal recovers. The demapped branch signal is buffered by a buffer, and then uniformly read by an address signal generated by a signal smoothing module. The signal smoothing module first calculates the bit number T of the branch signal that is actually demapped in the selected unit time relative to the standard rate branch signal, and determines the bit number T to be leaked; the value of the corresponding leak rate is obtained from the T value The integer part M0 and the initial remainder part N0 calculate the bit leakage interval, and leak all the bits T evenly in unit time; every time a bit leakage interval passes, a leakage pulse signal is generated, and it is compared with the standard rate uniform pulse signal The signals are superimposed and the pulses of the superimposed signals are counted, thereby generating evenly changing read addresses to read out the buffered branch signals. By adopting the method of the present invention, the processed branch signal can have better smoothness after being accurately leaked once.

Description

A branch signal recovery method and device based on non-integer leakage rate

technical field

The present invention relates to the technique of recovering PDH (quasi-synchronous digital hierarchy) signal from VC (virtual container) of SDH (synchronous digital hierarchy), especially relates to the branch signal recovery method and its realization based on the non-integer leakage rate when smoothing the signal device.

Background technique

When transmitting PDH tributary signals (hereinafter referred to as tributary signals) in the SDH system, according to the standard, it is first necessary to adapt the PDH signal (considered as the payload) to the SDH virtual container VC through mapping according to a certain mapping structure , the difference between the tributary signal and the standard VC rate is eliminated through the control of the mapping adjustment bit. When the adjustment bit indicates that the adjustment position is valid, the effective adjustment position can be loaded into the payload, otherwise, the stuffing bit is loaded. After such adaptation, the tributary signal is encapsulated in VC, and the VC signal can be independently transmitted, multiplexed and cross-connected in the SDH network system, and the tributary signal is sent to the place where it needs to reach. After arriving at the destination, the branch signal needs to be extracted from the VC. This process is called demapping. In order to recover a uniform branch signal from the VC, it is necessary to restore the original uniform clock of the branch signal. Signal. Since the tributary signal has lost its clock information when it is encapsulated into the VC, it is necessary to recover the clock of the tributary signal from the demapped data stream. However, after removing the stuffed bits and overhead bits and demapping according to the mapping frame structure, we get The outgoing data stream is an irregular data stream with gaps.

Moreover, when the tributary signal is transmitted in the SDH system, due to the function of pointer adjustment, when the VC that encapsulates the tributary signal is in the process of transmitting the SDH system due to the asynchronous or out-of-synchronization of the network itself, the pointer adjustment occurs, the position of the VC is in the SDH A change of 3 bytes or 1 byte in the frame structure results in a change of up to 8 or 24 bits in the actual VC content in this frame, so the recovered data stream is an irregular data stream, and The tributary signal clock recovered from the data flow has a relatively large jitter value. Therefore, during demapping, reducing the excessive jitter of the recovered signal due to the phase jump of the signal flow is a key issue in this process.

Therefore, in order to reduce the jitter of the recovered clock, it is necessary to smooth the recovered signal. For the change value of information bits brought about by a pointer adjustment, it can be considered to save the number of bits changed by these pointer adjustments first (possibly multiple more or less), and then release them evenly, one bit at a time. The whole process is equivalent to "dispersing" the concentrated phase change into multiple smaller changes. It is equivalent to storing a torrent first like a reservoir, and then gradually leaking out, so it is called "leakage". The unit time required to leak one bit each time is called the leak rate. After the branch signal is processed by leakage, the signal will become uniform, so that a clock signal with less jitter can be obtained.

However, the prior art has the following disadvantages in the process of leaking branch signals:

1. Take the integer part of the calculated leak rate to perform leak smoothing, but in fact the leak rate is mostly a non-integer value, so that when only the integer part of the leak rate is used to leak the accumulated bits, the number of leaks is more than The number of bits that need to be leaked cannot be leaked precisely.

2. Due to the existence of the above problem, an additional circuit is required in the prior art to eliminate the influence of over-leakage bits, which increases the complexity of the circuit.

3. The calculation of the leakage rate requires an external processor to complete.

Contents of the invention

The technical problem to be solved by the present invention is to provide a branch signal recovery method based on a non-integer leakage rate, so that the processed branch signal has better smoothness after a precise leak. The present invention also provides a branch signal recovery device capable of realizing the method.

In order to solve the above technical problems, the present invention provides a branch signal recovery method based on a non-integer leakage rate, comprising the following steps:

(a) demap branch signals from the virtual container and cache them;

(b) Calculate the number of bits T increased or decreased by the actual demapped tributary signal relative to its standard rate tributary signal for each selected unit time, and determine the next unit time according to the T value The number of bits T to be leaked;

(c) According to the number of bits T to be leaked and the minimum number of leak intervals included in the unit time, the leak rate corresponding to T is obtained, including the integer part M0 and the initial remainder part N0. The minimum leakage interval number divided by the bit number T that needs to be leaked can obtain the leakage rate corresponding to this T, wherein the unit time refers to each selected unit time in step (b), and the minimum leakage interval is Refers to the time corresponding to the signal structure segment that can appear repeatedly in the signal flow;

(d) In each unit time, calculate the bit leakage interval that is an integer multiple of the minimum leakage interval according to the integer part M0 of the leakage rate and the initial remainder part N0 and make it change uniformly, the number of bits T to be leaked in this unit time Leak out one by one according to the current bit leakage interval, specifically, use N0 as the increment and initial value, accumulate the remainder once every time a bit leakage interval passes, and when the accumulated value<T, use M0 as the next bit release The bit leakage interval, and when the accumulated value ≥ T, take M0+1 as the bit leakage interval of the next bit release and subtract T from the accumulated remainder value;

(e) Generate a leakage pulse signal consistent with the positive and negative values of T every time a bit leakage interval passes, superimpose the leakage pulse signal with the uniform pulse signal having the standard rate of the branch signal, and accumulate the pulses of the superimposed signal Counting to obtain a uniformly changing address signal, using the address signal to read out the cached branch signal;

(f) Utilize the uniform address signal generated by the counting to write the read branch signal into another register for secondary buffering, and use the address signal as a phase detection signal to recover a uniform clock, and then use the uniform clock Read the secondary cached branch signals to recover the final required uniform branch signals.

Further, the above branch signal recovery method may also have the following characteristics: in the step (e), the minimum leakage interval is counted, and when the count value is equal to the bit leakage interval value, a positive or negative Leak the pulse signal and start counting again.

Further, the above-mentioned branch signal recovery method may also have the following characteristics: in the step (b), the average value of all T values of the current unit time and previous several consecutive unit times is taken to determine the number of bits to be leaked T.

Further, the above-mentioned branch signal recovery method may also have the following characteristics: in the step (c), the leakage rate is directly taken out from the storage unit according to the T value, and the storage unit pre-stores all possible T values The corresponding leakage rate.

Further, the above branch signal recovery method may also have the following characteristics: when the step (e) superimposes the leakage pulse signal and the uniform pulse signal of the standard rate, it is necessary to stagger the pulse signals of the two to avoid pulse , and when counting the superimposed signals of the two, each time a standard rate signal pulse and a positive leakage pulse appear, the count increases by 1, and each time a negative leakage pulse occurs, the count decreases by 1.

Further, the above-mentioned branch signal recovery method can also have the following characteristics: in order to realize that the pulse count of each negative leakage is reduced by 1, when the high-speed clock is frequency-divided to obtain the pulse signal of the standard rate, the pulse signal is made at the minimum leakage The actual number of pulses in the interval is one less than its standard number. If there are no negative leakage pulses in the superimposed signal within a minimum leakage interval, add 1 to the read address generated by the count. If there is a negative leakage pulse, the count generated by the The read address remains unchanged.

In order to realize the above method, the present invention provides a branch signal restoration device based on a non-integer leak rate, including a first-level buffer module for buffering the irregular branch signal after demapping and a buffer module for providing an address signal to buffer The signal smoothing module of the branch signal readout also includes a secondary buffer module connected with the first-level buffer module, it is characterized in that, the signal smoothing module further includes adjusting the influence bit counting unit, leakage interval A calculation unit and a leakage realization unit, the secondary buffer module is used to buffer the branch signal read from the first level buffer module, and read it through the uniform branch clock signal recovered by address phase detection out, of which:

The adjustment-affected bit counting unit is used to calculate the number of bits T increased or decreased by the branch signal actually demapped in the selected unit time relative to the standard rate branch signal, and determine and output the next unit time according to the T value The number of bits T to be leaked;

The leakage interval calculation unit is used to calculate the bit leakage interval according to the integer part M0 of the leakage rate and the initial remainder part N0 in each unit time and make it change uniformly, and the number T of bits to be leaked in the unit time is calculated according to the current The bit leakage interval of is leaked one by one;

The leakage realization unit is used to generate a leakage pulse signal consistent with the positive and negative values of T every time a bit leakage interval passes, superimpose the leakage signal with a uniform pulse signal having the standard rate of the branch signal, and perform the superimposed signal The pulses are accumulated and counted to obtain a uniformly changing address signal, and the buffered branch signal is read out using the address.

Further, the above-mentioned branch signal recovery device may also have the following characteristics: the adjustment affected bit counting unit further includes a sliding average subunit, which is used to calculate the current unit time and all T values of the previous n-1 consecutive unit times The mean value gives the number T of bits to be leaked.

Further, the above-mentioned branch signal recovery device may also have the following characteristics: the leakage interval calculation unit includes a leakage rate acquisition subunit, a logic operation subunit and a selector, wherein:

The leakage rate obtaining subunit is used to obtain the leakage rate including the integer part M0 and the initial remainder part N0 according to the number of bits T to be leaked, specifically, divide the minimum number of leaking intervals that can be transmitted per unit time by the number of bits that need to be leaked The number of bits T can obtain the leakage rate corresponding to this T, wherein the unit time refers to the selected unit time, and the minimum leakage interval refers to the time corresponding to the signal structure segment that can reappear in the signal stream;

The logic operation subunit is used to use N0 as an increment and an initial value to accumulate the remainder once after a bit leakage interval, and when the accumulated value<T, instruct the selector to strobe the M0 value output, And when the accumulated value ≥ T, instruct the selector to strobe the M0+1 value output and subtract T from the accumulated remainder part value;

The selector is configured to select one of M0 and M0+1 according to the indication signal of the logical operation subunit to output as the bit leakage interval value for the next bit release.

Further, the above-mentioned branch signal recovery device may also have the following characteristics: the leakage realization unit includes: a minimum leakage interval counter, which is used to count the elapsed minimum leakage intervals and reset to zero after outputting a leakage pulse signal, the minimum leakage The interval refers to the time corresponding to the signal structure segment that can appear repeatedly in the signal stream; the comparator is used to compare the count value of the minimum leakage interval counter and the bit leakage interval value, and generate a T value when the two are equal A leakage pulse signal with consistent positive and negative; a frequency divider, used to divide the frequency of the high-speed clock to obtain a uniform pulse signal with the standard rate of the branch signal; a pulse counter, used to superimpose the uniform pulse signal and the leakage pulse signal and Count the pulses of the superimposed signal, and the counting result is output as the read address signal of the first-level buffer module.

Further, the above-mentioned branch signal recovery device may also have the following characteristics: the leakage rate acquisition subunit includes a memory for storing the integer part M0 and the initial remainder part value N0 of the leakage rate corresponding to all possible T values For take out.

Further, the above-mentioned branch signal recovery device can also have the following characteristics: each module of the branch signal recovery device is connected with a high-speed clock whose rate is higher than that of the branch signal as a means for each module to perform smooth processing of the branch signal base clock.

As can be seen from the above, by using the device and method of the present invention to process the remainder of the leakage rate, not only can all the bits increased or decreased relative to the standard rate signal after the pointer adjustment and mapping adjustment within the selected time period be leaked, so that the leakage is more accurate , and also ensures the smoothness of the bit leakage interval, so that the generated read and write addresses are more uniform, and the recovered branch clock signal has a smaller jitter value. Furthermore, the device of the present invention uses pure hardware circuits to realize the calculation and leakage of non-integer leakage rates, without the participation of external processors, and without the need for circuits to eliminate the influence of over-leakage bits.

Description of drawings

表示比较器。Fig. 1 is a schematic structural diagram of a device according to an embodiment of the present invention. in the picture Indicates the summing device,

Indicates a comparator.

Fig. 2 is a flow chart of the method of the embodiment of the present invention.

Detailed ways

As shown in FIG. 1 , the leakage smoothing device of this embodiment includes a first-level FIFO1 module, a second-level FIFO2 module and a signal smoothing module. At the same time, a high-speed clock whose frequency is higher than that of the recovered branch signal clock is provided as the basic clock of the above-mentioned modules for realizing the smooth processing of the branch signal.

The first-level first-in-first-out buffer module is used to buffer the demapped irregular branch signals, and read them evenly through the address generated by the signal smoothing unit to achieve signal smoothing.

The second-level FIFO buffer module is used for buffering the tributary signals read from the first-level FIFO buffer, and reading them out through the recovered uniform tributary clock signal. As shown in Figure 1, the uniform branch clock signal is phase-identified by the highest bit of the uniform address generated by the signal smoothing module and the highest bit of the address signal generated by the recovered clock, and then controlled by the pressure cavity oscillator of the external circuit after low-pass filtering (VCXO) and recovered.

The signal smoothing module further includes: an adjustment influence bit counting unit, a leakage interval calculation unit and a leakage realization unit. in:

Adjusting the affected bit counting unit is used to calculate the number of bits T increased or decreased by the tributary signal actually demapped in the selected unit of time relative to the standard rate tributary signal, and output the bit to be leaked in the next unit of time after its sliding average Count T. As shown in Figure 1, the actual signal counter and the standard rate signal counter in this unit are used to calculate the actual effective signal bit number and the bit number of the standard rate branch signal respectively. After subtracting the difference, the moving average calculator The unit takes the mean value of all T values of the current unit time and the previous n-1 consecutive unit times to obtain T.

The leakage interval calculation unit is used to take the number of bits to be leaked T as the address to take out the leakage rate corresponding to the integer part M0 and the initial remainder part N0 in the memory, and take N0 as the initial value and increment, and every time a bit leakage interval passes through the remainder Partially accumulate once, when the accumulated remainder value ≥ T, output M0+1 as the bit leakage interval of the next bit release and subtract T from the accumulated remainder value, and when the accumulated remainder value <T, set M0 is output as the bit leakage interval of the next bit release. The bit leakage interval here is represented by the number of minimum leakage intervals between two leaks.

As shown in Figure 1, there is a ROM in the unit, which stores the index relationship table corresponding to T, its leakage rate integer M0 and the initial remainder N0. According to the value of T, M0 and N0 can be directly taken out, and a simple method is used to avoid The division problem is directly calculated by the circuit, and no external processor is needed to calculate the leakage rate. Of course, it is also possible to use an external processor to participate in the calculation of the above-mentioned T value and the bit leakage interval, but the requirement for the computing speed of the processor is very high.

The logic operation sub-unit composed of the summation device (∑), comparator (∑>=T) and subtractor (∑-T) in the figure is respectively used to complete the accumulation of the above-mentioned remainder part, and the accumulated remainder part value and T comparison, and subtraction of the accumulated value from T. In this embodiment, the comparator of the leakage implementation unit outputs an indication signal to start the above accumulation, comparison and subtraction operations (not shown in the figure) when the minimum leakage interval count is equal to the value of the bit leakage interval. The one-of-two selector selects one of M0 and M0+1 according to the comparison result of the accumulated value and T, and outputs it as the bit leakage interval value for the next bit release.

The leakage realization unit is used to output a leakage pulse signal consistent with the positive and negative values of the T value when the bit leakage interval value and the count value of the minimum leakage interval are equal, and superimposed with the uniform pulse signal of the standard rate obtained after frequency division, and then superimposing the superimposed signal Pulse counting, to obtain uniform read and write addresses, used for reading and writing between FIFO1 and FIFO2 and address phase discrimination.

As can be seen from Fig. 1, the unit includes a minimum leakage interval counter, which is used to count the passed minimum leakage interval, and resets to count again after the leakage pulse signal is generated; a comparator, which is used to compare the minimum leakage interval count and the bit The value of the leakage interval, when the two are equal, a leakage pulse signal consistent with the positive and negative values of T is generated; the frequency divider is used to divide the frequency of the high-speed clock to obtain a uniform pulse signal with the standard rate of the branch signal; the pulse counter , for superimposing the uniform pulse signal and the leakage pulse signal and counting the pulses of the superimposed signal, and the counting result is output as a read-write address between the first-level and second-level buffers. The minimum leakage interval counter, the frequency divider and the pulse counter all use the high-speed clock as the basic clock for counting and frequency division.

Through the above device, the part of the actual tributary signal adjusted by the pointer adjustment and the mapping adjustment relative to the standard rate tributary signal is evenly leaked to the standard rate tributary signal.

The leakage method of this embodiment will be described in detail below, and the application of this method in E/T3 signal smooth leakage is taken as an example to illustrate. As shown in Figure 2, it includes the following steps:

Step 100, demap the tributary signal from the VC virtual container and write it into the first-level cache;

Step 110, calculate the number T of bits T increased or decreased by the actually demapped tributary signal relative to the standard rate tributary signal in each selected unit time, the T value reflects the pointer adjustment and mapping frequency offset The number of bit changes in a unit of time;

In the example, 1/3 second is selected as the unit time, and the number of actually effective signal bits during this period is accumulated according to the demapped data valid indication signal within the unit time, while for the standard rate E/T3 signal, During this period of time, there are 34.368*125*8000/3=11456000 bits for E3, and 44.736*125*8000/3=14912000 bits for T3. Use the actual effective signal bit number and -11456000 or T3 of the E3 signal By adding the -14912000 bit values of the signal, it is possible to know how many bits the actual signal has increased or decreased compared with the standard rate tributary signal during this period.

According to the standard, the frequency deviation allowed by pointer adjustment is +-4.6ppm, and the frequency deviation allowed by PDH branch signal is +-20ppm. Therefore, no matter it is E3 or T3 signal, the number of bit changes caused by pointer adjustment and mapping adjustment within a certain range.

Step 120, taking the mean value of all T values of the current unit time and the previous n-1 consecutive unit times to obtain T, as the number of bits to be leaked in the next unit time;

In the example, make a sliding average of the data calculated in 8 units of time, add the value of the first 7 units of time to the value obtained by the current unit of time, and then divide it by 8, as the bit to be leaked in the next unit of time In this way, the number of bit changes in the 8 unit time is divided equally, which further ensures that the change of the T value in each selected unit time is smoother.

Step 130, taking out the corresponding leakage rate according to the number T of bits to be leaked, including the integer part M0 and the initial remainder part N0;

The minimum leakage interval can be determined according to the structure of the branch signal mapping frame. The time corresponding to the signal structure segment that can appear repeatedly in the signal flow can be used as the minimum leakage interval. For example, the time corresponding to a subframe can be selected, so here The leak rate indicates how many minimum leak intervals one bit needs to pass through.

According to the frame structure of the PDH signal E3/T3, it can be seen that the signal is repeatedly sent in units of one subframe, and the subframe of E3 is three times the length of the subframe of T3, so the minimum leakage interval can be selected to correspond to one E3 subframe time interval. In 1/3 second, there are 8000 E3 subframes. Divide the minimum number of leakage intervals that can be transmitted per unit time by the number T of bits that need to be leaked to get the leakage rate corresponding to T, that is, it takes How many minimum time intervals are separated, subframes in this instance. The value of the leakage rate is not necessarily an integer, and the integer part and the remainder part should be taken at the same time for accurate leakage. For the E3 signal, the integer part of the leak rate value is M0=INT(8000/T), and the remainder part is N0=MOD(8000/T).

When introducing the device, it has been mentioned that in this embodiment, the values of the integer part and the remainder part of the leakage rate corresponding to all possible T values in the selected unit time are pre-stored in the ROM storage unit, and each T and Corresponding index relationship table of the leak rate integer part M0 and the initial remainder part N0. In this way, M0 and N0 can be directly taken out according to the T value. It has been pointed out above that the number of bit changes ultimately caused by pointer adjustment and mapping adjustment is within a certain range, but considering the impact of sudden changes when the network is out of sync, this embodiment also appropriately expands the range of the T value.

Step 140: In each unit time, use the initial remainder N0 as the increment and initial value, accumulate the remainder once every bit leakage interval, and when the accumulated remainder value < T, use M0 as the next bit release The bit leakage interval of , and when the accumulated remainder value ≥ T, take M0+1 as the bit leakage interval of the next bit release and subtract T from the accumulated remainder value;

In the example, after the start of each (1/3 second) unit time, take the corresponding M0, N0, and N0 as the initial value and increment of the remainder of the leak rate according to the T value calculated in the previous (1/3 second) , and start subframe accumulative counting. When the subframe count value is equal to the integer part of the leakage rate M0, the first bit will be leaked, the subframe count will be reset to zero, and the remainder of the leakage rate will be accumulated once. When the accumulated remainder When the value is greater than or equal to T, take the next bit leakage interval as M0+1, and subtract T from the accumulated part of the remainder, otherwise take the leakage interval as M0. Next time when the subframe count is equal to the bit leakage interval, another bit is leaked, and the above calculation is repeated: the subframe count is cleared, and the remainder of the leakage rate is accumulated to obtain the next bit leakage interval, etc. So, until (1/3 second) unit time is over. The next (1/3 second) unit time moment begins, and the corresponding M0 and N0 are taken out according to the new T value to start leaking.

Use another simple example to illustrate, assuming that there are 100 subframes in a unit time, and the number of bits to be leaked after smoothing is T=8, then the integer part of the leakage rate M0=12, and the initial remainder part N0=4. According to the method of this embodiment, the calculated bit leakage intervals are 12, 13, 12, 13, 12, 13, 12, 13 in sequence, so that 8 bits are evenly leaked in a unit time.

Step 150, when the bit leakage interval is equal to the minimum leakage interval count value, generate a positive or negative leakage pulse (equivalent to an indication signal of a bit leakage, when T is positive, it is a positive leakage pulse, otherwise it is a negative leakage pulse ) and clear the count value, superimpose the leakage pulse signal on the uniform pulse signal with the standard rate of the branch signal, and count the pulses of the superimposed signal, every time a standard rate signal pulse and a positive leakage pulse appear, the count increases by 1, Each time a negative leakage pulse occurs, the count is decremented by 1;

In the example, the basic clock adopts a high-speed clock with a rate of 77.76M. For the branch signal part of the standard rate, we need to obtain a uniform pulse signal of the standard rate to add one to the read and write address at each pulse effective position. This standard rate pulse can be obtained by evenly dividing the frequency of the 77.76M high-speed clock. As long as the pulse is uniform, the accumulative increment of the read and write addresses is uniform. For the clock signal of 77.76M, there are 3240 clock cycles in a subframe of 125μs/3, while for the branch signal of the standard rate, the E3 signal of the rate 34.368M has 1432 clock cycles in the same time , the T3 signal with a rate of 44.736368M has 1864 clock cycles, which requires 1432 or 1864 clock pulses to be taken out evenly in 3240 clock cycles. But in the example, we only take 1431 and 1863 pulses, which is one less than the standard number, and the reason will be introduced below.

On the standard rate pulse, we also need to superimpose the part where the number of bits changes due to pointer adjustment and mapping adjustment, that is, we need to evenly superimpose the calculated leakage bits on the standard rate pulse according to the calculated leakage rate. , it should be noted that the position of the positive and negative leakage pulses cannot overlap with the position of the standard signal pulse. Therefore, according to the leak rate, a leak indication pulse is generated at the position of each bit leak. If T is positive, the pulse is a positive leak pulse, and the read and write address is increased by one at the pulse position; if T is negative, the pulse is Negative leakage pulse, the read and write address should be decremented by one at the pulse position, but the actual design does not directly decrement the address by one at this position. Considering that the subtraction operation of the read-write address will cause its value to change back and forth, resulting in an increase in jitter, therefore, when calculating the number of bits at the standard rate, in a subframe, only 1431 pulses are taken for E3, T3 Take 1863 pulses, which is one less than the actual number, which leads to a standard frequency deviation of about -700ppm, which is much larger than the range of ±20ppm. Therefore, within the time interval corresponding to each subframe, if there is no negative leakage pulse , add one to the read and write address, and when there is a negative leakage pulse, the read and write address remains unchanged, just do not add. This approach also achieves the purpose of decrementing the count by 1 each time a negative leakage pulse occurs, but it is realized within a subframe, not necessarily at the position where the negative leakage pulse is generated. This solves the problem of bit number reduction caused by negative frequency deviation.

Step 160, using the uniformly changing signal obtained by counting the superimposed signal as a read/write address, smoothly reading out the cached branch signal and writing it into the L2 cache. The accumulated read-write address contains two parts, one is the branch signal part of the standard rate, and the other is the leakage part.

Step 170, using the uniform address signal generated by the counting as a phase detection signal to recover a uniform clock, and then use the uniform clock to read the secondary buffered branch signals to recover the final required uniform branch signal. Secondary buffering can further smooth the recovered tributary signal.

Obviously, the present invention is not limited to E3, T3 rate signals, as a general method, it can be used when PDH tributary signals are recovered from SDH. Through the above method, not only the number of bits increased or decreased relative to the standard rate signal after the pointer adjustment and mapping adjustment within the selected time period can be leaked, but also the smoothness of the bit leakage interval is guaranteed. Therefore, after processing with this method, recovery The output tributary clock signal has a smaller jitter value.

On the basis of the foregoing embodiments, the present invention can also perform various transformations. For example, it is not necessary for the present invention to perform a sliding average on T. The present invention can also be directly applied as the next unit time without taking the average value of T. the number of bits.

In addition, when using the local processor to calculate the leakage rate and bit leakage interval, logically, the fractional part of the quotient of the minimum number of leak intervals that can be transmitted per unit time divided by the number of bits T that need to be leaked can be replaced by the fractional part of the leakage rate. The remainder part is accumulated and calculated. When the accumulated value is greater than 1, the next bit leakage interval is taken as M0+1 and the accumulated value is subtracted by 1. This scheme has the same effect as the scheme of the above-mentioned embodiment, and the calculation of the method of this embodiment is more accurate. Keep it simple.

In addition, after the uniformly varying bit leakage interval is obtained, the leakage implementation device and method for obtaining uniformly varying read and write addresses based on the bit leakage interval can also adopt other schemes, such as the one used in the recovery of branch signals based on integer leakage rates. plan.

Claims (12)

1. A branch signal recovery method based on a non-integer leakage rate, comprising the following steps: (a) demap branch signals from the virtual container and cache them; (b) Calculate the number of bits T increased or decreased by the actual demapped tributary signal relative to its standard rate tributary signal for each selected unit time, and determine the next unit time according to the T value The number of bits T to be leaked; (c) According to the number of bits T to be leaked and the minimum number of leak intervals included in the unit time, the leak rate corresponding to T is obtained, including the integer part M0 and the initial remainder part N0. The minimum leakage interval number divided by the bit number T that needs to be leaked can obtain the leakage rate corresponding to this T, wherein the unit time refers to each selected unit time in step (b), and the minimum leakage interval is Refers to the time corresponding to the signal structure segment that can appear repeatedly in the signal flow; (d) In each unit time, calculate the bit leakage interval that is an integer multiple of the minimum leakage interval according to the integer part M0 of the leakage rate and the initial remainder part N0 and make it change uniformly, the number of bits T to be leaked in this unit time Leak out one by one according to the current bit leakage interval, specifically, use N0 as the increment and initial value, accumulate the remainder once every time a bit leakage interval passes, and when the accumulated value<T, use M0 as the next bit release The bit leakage interval, and when the accumulated value ≥ T, take M0+1 as the bit leakage interval of the next bit release and subtract T from the accumulated remainder value; (e) Generate a leakage pulse signal consistent with the positive and negative values of T every time a bit leakage interval passes, superimpose the leakage pulse signal with the uniform pulse signal having the standard rate of the branch signal, and accumulate the pulses of the superimposed signal Counting to obtain a uniformly changing address signal, using the address signal to read out the cached branch signal; (f) Utilize the uniform address signal generated by the counting to write the read branch signal into another register for secondary buffering, and use the address signal as a phase detection signal to recover a uniform clock, and then use the uniform clock Read the secondary cached branch signals to recover the final required uniform branch signals. 2. branch signal recovery method as claimed in claim 1, is characterized in that, in described step (e), is to described minimum leakage interval counting, when counting value is equal to described bit leakage interval value, produces a Positive or negative leakage pulse signal and restart counting. 3. The branch signal recovery method as claimed in claim 1 or 2, wherein, in the step (b), the average value of all T values of the current unit time and several consecutive unit times before that is used to determine the Describe the number T of bits to be leaked. 4. The branch signal recovery method as claimed in claim 1 or 2, wherein in the step (c), the leakage rate is directly taken out from the storage unit according to the T value, and the storage unit prestores Leakage rates for all possible values of T are given. 5. The branch signal recovery method as claimed in claim 1 or 2, wherein, when the step (e) superimposes the leakage pulse signal and the uniform pulse signal of the standard rate, it is necessary to combine the two Pulse signals are staggered to avoid overlapping of pulses, and when counting the superimposed signals of the two, each time a standard rate signal pulse and a positive leakage pulse appear, the count increases by 1, and each time a negative leakage pulse occurs, the count decreases by 1. 6. The branch signal recovery method as claimed in claim 5, characterized in that, in order to realize that a negative leakage pulse count is subtracted by 1, when dividing the frequency of the high-speed clock, the obtained uniform pulse signal of the standard rate The number of pulses in the minimum leakage interval is one less than its standard number. If there is no negative leakage pulse in the superimposed signal within a minimum leakage interval, add 1 to the read address generated by the count. If there is a negative leakage pulse, count The resulting read address remains unchanged. 7. A branch signal restoration device based on a non-integer leak rate, including a first-level buffer module for buffering the irregular branch signal after demapping and a device for providing an address signal to read out the buffered branch signal The signal smoothing module also includes a secondary buffer module connected to the first-level buffer module, wherein the signal smoothing module further includes an adjustment affected bit counting unit, a leakage interval calculation unit and a leakage realization unit, The secondary buffer module is used to buffer the branch signal read from the first level buffer module, and read it out through the uniform branch clock signal recovered by address phase detection, wherein: The adjustment-affected bit counting unit is used to calculate the number of bits T increased or decreased by the branch signal actually demapped in the selected unit time relative to the standard rate branch signal, and determine and output the next unit time according to the T value The number of bits T to be leaked; The leakage interval calculation unit is used to calculate the bit leakage interval according to the integer part M0 of the leakage rate and the initial remainder part N0 in each unit time and make it change uniformly, and the number T of bits to be leaked in the unit time is calculated according to the current The bit leakage interval of is leaked one by one, specifically, with N0 as the increment and initial value, the remainder is accumulated once every time a bit leakage interval passes, and when the accumulated value<T, the selector is instructed to gate the value of M0 output, and when the accumulated value ≥ T, instruct the selector to strobe the M0+1 value output and subtract T from the accumulated remainder value; The leakage realization unit is used to generate a leakage pulse signal consistent with the positive and negative values of T every time a bit leakage interval passes, superimpose the leakage pulse signal with the uniform pulse signal having the standard rate of the branch signal, and superimpose The pulses of the signal are accumulated and counted to obtain a uniformly changing address signal, and the buffered branch signal is read out by using the address signal. 8. The branch signal restoration device according to claim 7, wherein the adjustment-affected bit counting unit further comprises a sliding average subunit, which is used to compare the current unit time and previous n-1 consecutive unit times All T values are averaged to obtain the number T of bits to be leaked. 9. The branch signal restoration device according to claim 7, wherein the leakage interval calculation unit comprises a leakage rate acquisition subunit, a logical operation subunit and a selector, wherein: The leakage rate obtaining subunit is used to obtain the leakage rate including the integer part M0 and the initial remainder part N0 according to the number of bits T to be leaked, specifically, divide the minimum number of leaking intervals that can be transmitted per unit time by the number of bits that need to be leaked The number of bits T can obtain the leakage rate corresponding to this T, wherein the unit time refers to the selected unit time, and the minimum leakage interval refers to the time corresponding to the signal structure segment that can reappear in the signal stream; The logic operation subunit is used to use N0 as an increment and an initial value to accumulate the remainder once after a bit leakage interval, and when the accumulated value<T, instruct the selector to strobe the M0 value output, And when the accumulated value ≥ T, instruct the selector to strobe the M0+1 value output and subtract T from the accumulated remainder part value; The selector is configured to select one of M0 and M0+1 according to the indication signal of the logical operation subunit to output as the bit leakage interval value for the next bit release. 10. The branch signal recovery device according to claim 7, characterized in that, the leakage realization unit comprises: a minimum leakage interval counter, which is used to count the passed minimum leakage interval and clear it after outputting the leakage pulse signal, The minimum leakage interval refers to the time corresponding to the signal structure segment that can appear repeatedly in the signal stream; the comparator is used to compare the count value of the minimum leakage interval counter with the bit leakage interval value, and generates when the two are equal A leakage pulse signal consistent with the positive and negative values of T; a frequency divider, used to divide the frequency of the high-speed clock to obtain a uniform pulse signal with the standard rate of the branch signal; a pulse counter, used to combine the uniform pulse signal and the leakage The pulse signal is superimposed and the pulses of the superimposed signal are counted, and the counting result is output as a read address signal of the first-level buffer module. 11. The branch signal recovery device according to claim 9, wherein the leakage rate acquisition subunit includes a memory for storing the integer part M0 of the leakage rate corresponding to all possible T values and the initial The remainder part value N0 is for taking out. 12. The branch signal recovery device as claimed in claim 7, 8, 9 or 10, wherein each module of the branch signal recovery device is connected with a high-speed clock whose rate is higher than that of the branch signal It is used as the basic clock for each module to perform branch signal smoothing.

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