CN1845458B - Automatic Compensation Alternating Integrator and Its Control Method - Google Patents

Abstract

The automatic compensation alternating integrator and its control method, with the automatic compensation low zero drift integrator as the integration unit, is characterized in that two integration units are set, including integration unit A and integration unit B, and the signal input of the two integration units Terminals ViA and ViB are alternately connected to the integral signal input terminal Vi through a changeover switch, and an accumulation circuit is set at the signal output terminals of the two integral units, and the unit integral signals VoA and VoB respectively output by the integral unit A and the integral unit B The input is in the accumulation circuit, and the integral voltage Vo is output through the accumulation operation of the accumulation circuit. The invention is not limited by integral time and can work effectively for a long time.

Description

Automatic Compensation Alternating Integrator and Its Control Method

Technical field:

The invention relates to an integrator and a control method thereof, more specifically to a long-time integrator with an integral time of more than 100s and a control method thereof.

Background technique:

Long time integrators are mainly used in electromagnetic measurements of some devices. For example, in the process of tokamak discharge experiment, the output of many electromagnetic measurement diagnostic signals is the differential component of the signal. To restore the signal, an integrator is needed. With the continuous development of tokamak nuclear fusion research, the discharge time of plasma is getting longer and longer, so the integration time is also required to be longer and longer. The discharge time of EAST just built by the Institute of Plasma Physics, Chinese Academy of Sciences will reach thousands of seconds. class. However, due to the existence of drift, the general analog integrator can work effectively for tens of seconds. The more advanced digital integrator converts the analog quantity into a digital quantity through the method of AD or VF, and then completes the integral operation through corresponding algorithm processing, and finally converts the result into an analog quantity through DA or FV. The accuracy of the digital integrator mainly depends on the resolution of AD or VF, the higher the resolution, the higher the accuracy, so the digital integrator generally needs to choose a higher resolution AD or VF, which makes it expensive.

The integral drift is mainly caused by the offset voltage V _IO and the offset current I _IO , so the offset compensation at the input terminal can effectively suppress the integral drift. For this reason, the present inventor has proposed a kind of invention patent application of " automatic compensation low zero drift integrator " before this, as shown in Fig. 1, this analog integrator adopts the method of feedback compensation, consists of a basic integrator It is composed of a feedback network composed of a sample-and-hold circuit. The sample-and-hold circuit is used to record the zero drift, and then the input terminal is compensated during integration to offset the zero drift.

The specific scheme is shown in Figure 1: it consists of a feedback network composed of a basic integrator and a sample-and-hold circuit; it includes: the inverting input terminal resistance R of the operational amplifier IC1 constituting the integrator is connected to the input voltage ViA through the selection switch K1, Or ground; there are four parallel branches between the inverting input and output of the operational amplifier IC1, one is composed of switch K4, one is composed of integrating capacitor C and switch K3 in series, and one is composed of resistor Rf and switch K2 connected in series Composition, the other one is composed of resistor Rf, switch K5 and sample and hold circuit, wherein the sample and hold circuit is located on the output side of the operational amplifier; the positive output terminal of the operational amplifier is grounded through the positive input terminal resistor R.

The control method of the "automatically compensated low zero-drift integrator" is divided into the following two stages according to the timing:

First: In the preparation stage, follow the steps below to deduct the zero drift and clear the integral capacitor:

a. Measuring zero drift:

K1 is grounded, K2 is closed, and switches K3, K4, and K5 are opened to form an amplifier, and the zero-drift amplified signal output by the amplifier is recorded by the sample-and-hold circuit;

b. Compensation for zero drift:

K1 is grounded, K2 and K5 are closed, K3 and K4 are open, and the sample-and-hold circuit negatively feeds back the stored zero-drift value to the inverting input terminal of operational amplifier IC1 to compensate for zero-drift;

c. Clear the integral capacitor:

K1 is grounded, K3, K4, and K5 are all closed, and K2 is opened. Before the integration starts, the charge on the integration capacitor is cleared;

Second: Integral stage

After the preparation stage, K3 and K5 are closed, K1 is connected to the input signal ViA, and K2 and K4 are opened to form an integrator with a time constant of RC and start integration.

In this scheme, the inverting input terminal resistor R connected to the switch K1, the operational amplifier IC1 and the capacitor C constitute a basic integral circuit, and the integral time constant is RC. The resistor Rf connected to the switch K2 is used to measure the zero drift, and the sample and hold circuit is used to sample and hold the zero drift, and it is compensated to the '-' terminal of the operational amplifier IC1 through K5 and Rf, and the sample and hold circuit can be directly used by the sample and hold device accomplish.

It has been verified that the scheme can effectively overcome zero drift and work effectively within 100s. However, devices such as operational amplifiers and resistors have temperature drift, and integral capacitors have dielectric loss and leakage resistance. As time goes by, the drift will become larger and larger. Therefore, a longer time integration cannot be completed by relying on only one integrator.

Invention content:

The purpose of the present invention is to avoid the shortcomings of the above-mentioned prior art, and provide an automatic compensation alternating integrator that is not limited by the integration time and can work effectively for a long time; the present invention also provides a control method for the integrator.

The technical solution used by the present invention to solve technical problems is:

The automatic compensation alternating integrator of the present invention adopts the automatic compensation low zero drift integrator as the integration unit, and its structural feature is to set two integration units, including integration unit A and integration unit B, and the unit signal input of the two integration units Terminals ViA and ViB are alternately connected to the integral signal input terminal Vi through a changeover switch, and an accumulation circuit is set at the signal output terminals of the two integral units, and the unit integral signals VoA and VoB respectively output by the integral unit A and the integral unit B The input is in the accumulation circuit, and the integral voltage Vo is output through the accumulation operation of the accumulation circuit.

The control method of the automatic compensation alternating integrator of the present invention is:

Set the working cycle. In one working cycle, half of the cycle is the preparation stage, and the other half of the cycle is the integration stage. Under the conversion of the switch, the integration unit A and the integration unit B complete the following alternate work in sequence:

In the first half of the first working cycle, the integration unit A is in the integration phase, and its signal input terminal ViA is connected to the integration signal input terminal Vi through a switch, and the unit integration signal VoA1 is output; in this phase, the integration unit B is in preparation stage;

In the second half of the first working cycle, the integration unit A turns to enter the preparation stage, and at the same time, the integration unit B turns to the integration stage, and outputs the unit integration signal VoB1;

In the first half of the second working cycle, the integration unit A enters the integration phase, the output unit integration signal VoA2, and the integration unit B enters the preparation phase;

In the second half of the second working cycle, integration unit A enters the preparation phase, integration unit B enters the integration phase, and the output unit integration signal VoB2;

The above process is carried out cyclically; the obtained integrated signals VoA1, VoB1, VoA2, VoB2... are accumulated in the accumulation circuit to obtain the integrated signal Vo of the input signal Vi within the set time.

The present invention adopts the automatic compensation low zero drift integrator, which can well reduce the integral drift caused by the input offset _V'I , and the influence of capacitance and temperature drift can be effectively controlled by shortening the duty cycle T in the present invention. A single automatic compensation zero-drift integrator, that is, the integration unit has almost no drift in a short period of time. Take a shorter time, such as 20s, as the duty cycle T, and the two integration units alternate between the preparation phase and the integration phase. work, and then accumulate the output integration signals of the two integration units in the subsequent accumulation circuit to obtain an integration signal that is not limited by time.

Compared with the prior art, the beneficial effects of the present invention are reflected in:

1, in the present invention, a single integral unit has the function of automatically compensating for zero drift, which effectively solves the influence of the offset voltage _VIO and offset current _IIO of the operational amplifier, and can effectively suppress drift in a short time.

2. The present invention adopts alternate operation, realizes the alternate operation of two integration units, effectively solves the influence of temperature drift and capacitance, and can be applied to long-time integration.

3. The present invention can use digital signals to control each state of the integrating unit, and complete the alternate work of the two integrating units and the function of the accumulating circuit in the form of combination of modulus and digital.

4. The whole system of the present invention can be completed by using common components, which is cheap and has wide practicability.

Description of drawings:

Fig. 1 is a circuit schematic diagram of the automatic compensation low zero drift integrator of the present invention.

Fig. 2 is a circuit schematic diagram of an alternating integrator of the present invention.

Fig. 3 is a control sequence diagram of an alternate integrator according to the present invention.

Fig. 4 is a schematic diagram of the accumulation circuit of the present invention.

FIG. 5 is a schematic diagram of the adder circuit of the present invention.

The present invention is described further below by specific embodiment:

Detailed ways:

Referring to FIG. 1 , in this embodiment, the automatic compensation low zero-drift integrator shown in FIG. 1 is used as the integration unit, and the preparation phase and integration phase in the working process of the integration unit have been specifically described in the background technology.

Referring to Fig. 2, in the present embodiment, two-way integration units are set, including integration unit A and integration unit B, and the unit signal input terminals ViA and ViB of the two-way integration units are alternately connected to the integration signal input terminal Vi through a changeover switch. The signal output terminals of the two integration units are equipped with an accumulation circuit, and the unit integration signals VoA and VoB respectively output by the integration unit A and the integration unit B are input into the accumulation circuit, and the integration voltage Vo is output through the accumulation operation of the accumulation circuit.

Referring to Fig. 3, the control method of the automatic compensation alternating integrator of the present embodiment is:

Set the working cycle. In one working cycle, half of the cycle is the preparation stage, and the other half of the cycle is the integration stage. Under the conversion of the switch, the integration unit A and the integration unit B complete the following alternate work in sequence:

In the first half of the first working cycle, the integration unit A is in the integration phase, and its unit signal input terminal ViA is connected to the integration signal input terminal Vi through a switch, and the unit integration signal VoA1 is output; in this phase, the integration unit B is in the Preparation Phase;

In the second half of the first working cycle, the integration unit A turns to enter the preparation stage, and at the same time, the integration unit B turns to the integration stage, and outputs the unit integration signal VoB1;

In the first half of the second working cycle, the integration unit A enters the integration phase and outputs the unit integration signal VoA2, and the integration unit B enters the preparation phase;

In the second half of the second working cycle, the integration unit A enters the preparation phase, and the integration unit B enters the integration phase, and outputs the unit integration signal VoB2;

The above process is carried out cyclically; the obtained unit integral signals VoA1, VoB1, VoA2, VoB2... are accumulated in the accumulation circuit to obtain the integral signal Vo of the input signal Vi within the set time.

It can be seen from Figure 3 that the integration route is along the direction of the arrow. When the integration unit A is in the integration phase, the integration unit B is in the preparation phase; when the alternate time is reached, the integration unit B starts to integrate, and the integration unit A enters the preparation stage. Let the preparation time of the integration unit be t _p and the integration time t _I , take t _p =t _I =τ, where τ is the alternate time, that is, the duty cycle.

In this embodiment, the output of the two integration units is the integral value of each time period, and the output values of the two integration units need to be continuously accumulated through an accumulation circuit to obtain a complete integration signal.

Referring to Fig. 4 and Fig. 5, the accumulating circuit adopts a forward adder, and at the input end of the forward adder, one way switches between the unit integral signal output ends of the integral unit A and the integral unit B through the changeover switch S1, and another One path is switched between the output terminals of the sample-and-hold circuit 1 and the sample-and-hold circuit 2 through the conversion switch S2, and the sampling signals of the adopting-holding circuit 1 and adopting-holding circuit 2 are the output signal Vo of the adder.

The accumulation circuit shown in Figure 4 completes the addition of two unit integral signals through the forward adder shown in Figure 5, and the sample-and-hold device is used to save the accumulated value before the last alternation.

Fig. 5 is the specific implementation of the adder shown in Fig. 4. The forward adder is formed by the operational amplifier IC and the resistor Ra to complete the addition operation of the two signals.

According to the implementation mode of this embodiment, the accumulation circuit completes the accumulation work according to the following process:

1. The switch S1 is connected to the unit integration signal V _OA output by the integrating unit A, and the switch S2 is connected to the output V1 of the sample holder 1. At this time, the sample holder 1 is in the holding state, and the accumulated value V1 before the last alternation is saved. The accumulation of this period of time is realized by the adder. At the same time, the sample holder 2 is in the sampling state, and the current accumulation output value Vo of the sampling accumulation circuit is prepared for the next alternation;

2. When the alternate time is up, the switch S1 is connected to the integration unit B to output V _OB , the switch S2 is connected to the output V2 of the sample holder 2, and the accumulation of this period is completed through the adder, and the sample holder 1 continuously samples the current output value Vo .

3. Through this continuous alternate accumulation operation, the entire integral value is obtained.

Assume that the integration unit A starts to integrate first after the integration starts, and when the alternation time is reached, When the alternation time is up, integrating unit B starts to integrate, and when the alternation time is up,

The output is cleared to zero before integration begins. In the first alternation, the accumulated value is V _A1 ; in the second alternation, the accumulated value is (V _A1 +V _B2 ); in the third alternation, the accumulated value is ((V _A1 +V _B2 )+V _A2 ) ;……,So

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>$

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; RC</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; RC</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&tau;</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; RC</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&tau;</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; \&tau;</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; RC</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; \&tau;</span>}}^{\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; \&tau;</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>$

$=-\frac{1}{\mathrm{RC}}({\&Integral;}_0^{\mathrm{\&tau;}}f\left(x\right)\mathrm{dt}+{\&Integral;}_{\mathrm{\&tau;}}^{2\mathrm{\&tau;}}f\left(x\right)\mathrm{dt}+{\&Integral;}_{2\mathrm{\&tau;}}^{3\mathrm{\&tau;}}f\left(x\right)\mathrm{dt}+{\&Integral;}_{3\mathrm{\&tau;}}^{4\mathrm{\&tau;}}f\left(x\right)\mathrm{dt}+...)$ in,

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; RC</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dt</span>}<span\; class="notranslate">\; .</span>$

RC is the integration time constant, T is the total integration time, and f(x) is the integrated signal.

The smaller the value of the alternation time τ, the smaller the drift of a single integrating unit. However, the system works alternately, and there are errors in the alternation itself. At the same time, the accumulating circuit behind the two integrating units also has an impact on the entire integration process. Therefore, it is necessary to consider these factors and choose an appropriate alternation time.

Claims (2)

1. The automatic compensation alternating type integrator takes an automatic compensation low-zero-drift integrator as an integration unit and is characterized in that two paths of integration units are arranged and comprise an integration unit A and an integration unit B, signal input ends ViA and ViB of the two paths of integration units are alternately connected with an integration signal input end Vi through a change-over switch, an accumulation circuit is arranged at a signal output end of the two paths of integration units, unit integration signals VoA and VoB respectively output by the integration unit A and the integration unit B are input into the accumulation circuit, and integration voltage Vo is output through accumulation operation of the accumulation circuit.

2. A control method for an automatic compensation alternative integrator is characterized by comprising the following steps:

setting a working cycle, wherein in one working cycle, a half cycle is a preparation phase, the other half cycle is an integration phase, and under the conversion of a change-over switch, the integration unit A and the integration unit B sequentially complete the following alternate work:

in the first half of the first working period, the integrating unit a is in an integrating stage, and a unit signal input end ViA is connected with an integrating signal input end Vi through a change-over switch and outputs a unit integrating signal VoA 1; in this phase, the integrating unit B is in the preparation phase;

in the second half of the first working period, the integrating unit a enters the preparation stage, and meanwhile, the integrating unit B enters the integration stage and outputs a unit integration signal VoB 1;

in the first half of the second working period, the integrating unit A enters an integrating stage and outputs a unit integrating signal VoA2, and the integrating unit B enters a preparation stage;

in the second half of the second working period, the integrating unit A enters a preparation stage, the integrating unit B enters an integrating stage, and a unit integrating signal VoB2 is output;

the above processes are performed circularly, and the obtained unit integration signals VoA1, VoB1, VoA2 and VoB2.

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