CN1845310A - Manufacturing method of pixel array substrate - Google Patents

Abstract

A method for manufacturing a pixel array substrate comprises forming a plurality of grid electrodes, a plurality of scanning lines, a plurality of data line patterns and a plurality of pixel electrode patterns on a substrate. And forming a plurality of channels above the gate electrode and forming a plurality of contact hole openings exposing the data line patterns. And then forming a plurality of contact holes in the contact hole openings and electrically connected with the data line patterns. And then forming a plurality of connecting parts electrically connected with the contact holes, a plurality of source electrodes electrically connected with the data line patterns and a plurality of drain electrodes electrically connected with the pixel electrodes. The data line patterns in the same row are electrically connected with each other through the connecting part and the contact hole to form a data line. Therefore, the phenomenon of data signal transmission delay can be improved, and the pixel array substrate has lower manufacturing cost.

Description

Manufacturing method of pixel array substrate

technical field

The invention relates to a manufacturing method of a semiconductor element substrate, and in particular to a manufacturing method of a pixel array substrate.

Background technique

With the advancement of modern video technology, various displays have been widely used on display screens of consumer electronic products such as mobile phones, notebook computers, digital cameras and personal digital assistants (PDAs). Among these displays, liquid crystal displays (LCDs) and organic electroluminescence displays (OLEDs) have become the mainstream in the market due to their advantages of light weight, small size, and low power consumption. Whether it is a liquid crystal display or an organic electroluminescent display, the manufacturing process includes forming a pixel array substrate by semiconductor technology. By correspondingly adjusting the colors displayed by each pixel in the pixel array substrate, the display can generate images.

1 is a partial top view of a known pixel array substrate, and FIGS. 2A-2E are schematic cross-sectional views of the manufacturing process of the pixel array substrate in FIG. Please refer to FIG. 1 first. The known pixel array substrate 100 includes a substrate 110 and a plurality of thin film transistors 120 disposed on the substrate 110, a plurality of scanning lines 130, a plurality of data lines 140 and a plurality of pixel electrodes 150, each of which The gate 122 , source 124 and drain 126 of the thin film transistor 120 are electrically connected to the corresponding scan line 130 , data line 140 and pixel electrode 150 respectively. Generally speaking, the data lines 140 and the scan lines 130 are arranged alternately in rows and columns to define a plurality of pixel regions (not shown). Specifically, the scan lines 130 are arranged in the column direction, and the data lines 140 are arranged in the row direction, and the thin film transistor 120 is adjacent to the intersection of the scan lines 130 and the data lines 140 .

Following the above, the thin film transistor 120 is determined to be on or off according to the scanning signal transmitted from the scanning line 130 . When the thin film transistor 120 is turned on, the pixel electrode 150 can receive the data signal transmitted from the data line 140 through the thin film transistor 120 , so that the corresponding pixel can adjust the displayed color. Due to technical considerations, the thickness of the data line 140 is usually smaller than that of the scan line 130 , so that the area resistance of the data line 140 is greater than the area resistance of the scan line 130 . This will cause a phenomenon of data signal transmission delay, thereby degrading the display quality of the pixel array substrate 100 . Especially as the size of the pixel array substrate 100 continues to increase, the phenomenon of data signal transmission delay will become more serious.

Hereinafter, the manufacturing process of the pixel array substrate 100 will be described, please refer to FIG. Figure 1). Referring to FIG. 2B , a dielectric layer 160 is then formed on the substrate 110 to cover the gate 122 , and a second masking process is performed to define a channel 128 above the gate 122 . Referring to FIG. 2C , a third masking process is then performed to define the source 124 , the drain 126 and the data line 140 , wherein the gate 122 , the source 124 , the drain 126 and the channel 128 form the TFT 120 . Referring to FIG. 2D, a passivation layer 170 is formed on the substrate 110 to cover the thin film transistor 120, and a fourth masking process is performed to define a contact hole opening 172 in the passivation layer 170 to expose part Drain 126 . Please refer to FIG. 1 and FIG. 2E at the same time. Finally, a fifth masking process is performed to define the pixel electrode 150 on the passivation layer 170, wherein part of the pixel electrode 150 is filled into the contact hole opening 172, so that the pixel electrode 150 is electrically connected. connected to the drain 126. So far, the fabrication of the pixel array substrate 100 is completed.

Following the above, one of the main costs of manufacturing the pixel array substrate 100 is the manufacturing cost of the mask, and the known technology must use five different masks to perform five masking processes before the pixel array substrate 100 can be formed, so the pixel array The manufacturing cost of the substrate 100 cannot be reduced. Especially as the size of the substrate increases, a mask with a larger area must be used to form the pixel array substrate 100 , which further increases the manufacturing cost of the pixel array substrate 100 .

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a pixel array substrate, which can reduce the manufacturing cost of the pixel array substrate and improve the phenomenon of data signal transmission delay.

To achieve the above or other objectives, the present invention proposes a method for manufacturing a pixel array substrate. First, a transparent conductive layer and a first conductive layer are sequentially formed on a substrate, and then a first masking process is performed. The first conductive layer and the transparent conductive layer are patterned to form a plurality of gates, a plurality of scan lines electrically connected to the gates, a plurality of data line patterns and a plurality of pixel electrode patterns. After that, a dielectric layer and a semiconductor layer are sequentially formed on the substrate, and a second mask process is performed to pattern the dielectric layer and the semiconductor layer, and a channel is formed above each gate, and an exposed A plurality of contact holes of the data line patterns are opened, and the first conductive layer of the pixel electrode patterns is removed to form a plurality of pixel electrodes. Then a second conductive layer is formed on the substrate, and the second conductive layer will fill the openings of the contact holes to form a plurality of contact holes electrically connected with the data line patterns, and then perform a third masking process to patterning the second metal layer to form a plurality of connection parts electrically connected to the contact holes, a plurality of source electrodes electrically connected to the data line patterns, and a plurality of drain electrodes electrically connected to the pixel electrodes, and The second conductive layer on each pixel electrode is removed. Wherein, the data line patterns located in the same row are electrically connected to each other through the connecting portions and the contact holes to form a data line.

In addition, in order to achieve the above or other objectives, the present invention further proposes a method for manufacturing a pixel array substrate. First, a transparent conductive layer and a first conductive layer are sequentially formed on a substrate, and then a first masking process is performed. In the film process, the first conductive layer and the transparent conductive layer are patterned to form a plurality of gates, a plurality of scanning line patterns electrically connected to these gates, a plurality of data lines and a plurality of pixel electrode patterns. Then a dielectric layer and a semiconductor layer are sequentially formed on the substrate, and then a second mask process is performed to pattern the dielectric layer and the semiconductor layer, and a channel is formed above each gate, and an exposed A plurality of contact hole openings of the scan line patterns are opened, and the first conductive layer of the pixel electrode patterns is removed to form a plurality of pixel electrodes. Then a second conductive layer is formed on the substrate, and the second conductive layer will fill the openings of the contact holes to form a plurality of contact holes electrically connected with the scan line patterns, and then perform a third masking process, patterning the second metal layer to form a plurality of connection portions electrically connected to the contact holes, a plurality of source electrodes electrically connected to the data lines, and a plurality of drain electrodes electrically connected to the pixel electrodes, and shifting removing the second conductive layer on each pixel electrode. Wherein, the scan line patterns located in the same row are electrically connected to each other through the connecting portions and the contact holes to form a scan line.

In one embodiment of the present invention, after the above-mentioned third masking process, the following steps are further included: first, a passivation layer and a photoresist layer are sequentially formed on the substrate, and then these gates, sources The electrode, the drain electrode, the scan line and the data line are used as masks, and a back exposure process and a development process are performed to form a patterned photoresist layer. Then the passivation layer is etched by using the patterned photoresist layer as a mask to expose the pixel electrodes, and finally the patterned photoresist layer is removed.

In an embodiment of the present invention, the above-mentioned first masking process further includes forming a plurality of pads, and each pad is connected to one end of a corresponding scan line or data line. In the above-mentioned second masking process, it further includes retaining the dielectric layer and the semiconductor layer on part of the pads, and removing part of the first conductive layer of the pads. In the above-mentioned third masking process, it further includes removing part of the second conductive layer above the pads.

In an embodiment of the present invention, the above-mentioned first masking process further includes forming a plurality of lower electrodes. In the above-mentioned second masking process, it further includes retaining the dielectric layer and the semiconductor layer above the lower electrodes. In the above-mentioned third masking process, it further includes forming a plurality of upper electrodes on the semiconductor layer above part of the lower electrodes, wherein these lower electrodes and these upper electrodes form a plurality of capacitors, and each lower electrode is connected to the corresponding The scanning lines are electrically connected, and each upper electrode is electrically connected to the corresponding pixel electrode.

In an embodiment of the present invention, in the above-mentioned third masking process, it further includes removing part of the thickness of these channels.

In an embodiment of the present invention, the above-mentioned semiconductor layer includes a channel material layer and an ohmic contact material layer.

In an embodiment of the present invention, the thickness of the above-mentioned first conductive layer is greater than the thickness of the second conductive layer.

In summary, in the pixel array substrate and its manufacturing method of the present invention, since the material of the data line pattern is the same as that of the scan line (both are the material of the first conductive layer), and the data line is mainly composed of the data line pattern , so the areal resistance of the data lines is similar to the areal resistance of the scan lines, thereby improving the transmission delay of data signals. In addition, compared with the prior art that must use five masks to perform five mask processes to fabricate the pixel array substrate, the present invention only needs to use three masks to perform three mask processes to complete the fabrication of the pixel array substrate. Therefore, the manufacturing cost of the pixel array substrate can be reduced.

Description of drawings

FIG. 1 is a partial top view of a known pixel array substrate.

2A to 2E are schematic cross-sectional views of the manufacturing process of the pixel array substrate of FIG. 1 .

FIG. 3 is a partial top view of a pixel array substrate according to an embodiment of the present invention.

4A-4F are schematic cross-sectional views of the manufacturing process of the pixel array substrate of FIG. 3 .

4G to 4J are schematic cross-sectional views of a manufacturing process for forming a passivation layer on a pixel array substrate according to an embodiment of the present invention.

5A and 5B are top views after the process of FIG. 4B and FIG. 4D respectively.

FIG. 6 is a partial top view of a pixel array substrate according to another embodiment of the present invention.

Description of main component symbols:

100: pixel array substrate

110: substrate 120: thin film transistor

122: Gate 124: Source

126: Drain 128: Channel

130: Scanning line 140: Data line

150: Pixel electrode 160: Dielectric layer

170: Passivation layer 172: Contact hole opening

300, 600: pixel array substrate

310: substrate 320: active components

322: Gate 324: Source

326: Drain 328: Channel

330: Scanning line 340: Data line

342: Data line pattern 344: Connection part

346: Contact hole 350: Pixel electrode

350': pixel electrode pattern 360: capacitor

362: Lower Electrode 364: Upper Electrode

370: Welding pad 510: Transparent conductive layer

520: first conductive layer 530: dielectric layer

532: Contact hole opening 540: Semiconductor layer

542: channel material layer 544: ohmic contact layer

550: Second conductive layer 560: Passivation layer

570: Photoresist layer 572: Patterned photoresist layer

630: scan line 632: scan line pattern

634: Connecting part 640: Data line

Detailed ways

In order to make the above-mentioned technical solutions, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows.

3 is a partial top view of a pixel array substrate according to an embodiment of the present invention, and FIGS. 4A-4F are schematic cross-sectional views of the manufacturing process of the pixel array substrate in FIG. CC' line. Please refer to FIG. 3 first. The pixel array substrate 300 of the present invention includes a substrate 310 and a plurality of active elements 320 disposed on the substrate 310, a plurality of scanning lines 330, a plurality of data lines 340 and a plurality of pixel electrodes 350, wherein Each active element 320 is electrically connected to the corresponding scan line 330 , data line 340 and pixel electrode 350 . In addition, each data line 340 includes a plurality of data line patterns 342 and a plurality of connection portions 344, wherein the connection portions 344 are electrically connected to the data line patterns 342, and each connection portion 344 crosses one of the scan lines 330, but It is not electrically connected to the scan line 330 .

Specifically, the data line 340 is mainly composed of a data line pattern 342 , wherein the data line pattern 342 is made of the same material as the scan line 330 and is formed at the same time. In order to avoid a short circuit at the intersection of the scan line 330 and the data line 340 , the connecting portion 344 straddles the scan line 330 to electrically connect between two adjacent data line patterns 342 . In this way, since the data line patterns 342 have the same electrical characteristics as the scan lines 330 , the overall areal resistance of the data lines 340 is similar to that of the scan lines 330 , thereby improving the transmission delay of data signals.

In this embodiment, the active element 320 may be a thin film transistor. In detail, the gate 322 of the active element 320 is connected to the corresponding scan line 330, the source 324 of the active element 320 is connected to the corresponding data line 340, and the drain 326 of the active element 320 is connected to the corresponding pixel electrode 350. In addition, the pixel array substrate 300 may further include a plurality of capacitors 360 and a plurality of welding pads 370 disposed on the substrate 310, wherein the capacitors 360 are used to maintain a stable voltage on the pixel electrode 350, and the welding pads 370 are connected to the scanning lines 330 Or one end of the data line 340 serves as a pin.

Hereinafter, the manufacturing process of the pixel array substrate 300 of the present invention will be described in detail with reference to the accompanying drawings. Please refer to FIG. 4A. First, a transparent conductive layer 510 and a first conductive layer 520 are sequentially formed on the substrate 310, wherein the material of the transparent conductive layer 510 can be indium tin oxide (Indium Tin Oxide, ITO) or indium zinc oxide ( Indium Zinc Oxide, IZO), and the material of the first conductive layer 520 can be selected from aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), titanium nitride (TiN), chromium (Cr ), chromium nitride (CrN), or combinations thereof. In this embodiment, the first conductive layer 520 may be a four-layer stacked structure of titanium nitride/aluminum/titanium/titanium nitride, wherein the preferred thickness of aluminum is between 500 Ȧ and 2000 Ȧ, and titanium or The preferred thickness of titanium nitride is between 300 Ȧ˜1000 Ȧ.

In order to make the drawings clearer, FIG. 5A shows the top view of FIG. 4B after the process. Please refer to FIG. 4B and FIG. 5A, and then perform a first masking process to pattern the transparent conductive layer 510 and the first conductive layer 520 to form a plurality of gates 322, a plurality of scanning lines 330, and a plurality of data line patterns 342 and a plurality of pixel electrode patterns 350 ′, wherein each gate 322 is electrically connected to a corresponding scan line 330 .

Incidentally, the first masking process includes forming a photoresist layer (not shown) above the patterned transparent conductive layer 510 and the first conductive layer 520, and using a mask (not shown) Exposing and developing the photoresist layer to form a patterned photoresist layer (not shown). Then, an etching process is performed on the patterned transparent conductive layer 510 and the first conductive layer 520 by using the patterned photoresist layer as a mask (mask), so as to define the above-mentioned multiple elements. Finally, the first masking process is completed by removing the patterned photoresist layer. Those who are familiar with this technique should be able to clearly understand the detailed steps of the masking process by referring to the foregoing, and will not repeat the detailed steps of the masking process later.

In addition, in this step of this embodiment, a plurality of welding pads 370 and a plurality of lower electrodes 362 can be formed at the same time, wherein the lower electrodes 362 are important components of the capacitor 360, and each lower electrode 362 is electrically connected to the corresponding The scan line 330 . Incidentally, in order to increase the aperture ratio of the pixel array substrate 300 , the present invention does not provide a special area for accommodating the lower electrodes 362 , but uses part of the scanning lines 330 as the lower electrodes 362 .

Referring to FIG. 4C, a dielectric layer 530 and a semiconductor layer 540 are sequentially formed on the substrate 310, wherein the material of the dielectric layer 530 is, for example, silicon nitride (SiN _x ), silicon oxide (SiO _x ) or nitrogen Silicon oxide (SiO _x N _y ) is used as an insulating layer. In addition, in order to improve the electrical properties of the semiconductor layer 540, in this embodiment, the semiconductor layer 540 may include a channel material layer 542 and an ohmic contact layer 544, wherein the material of the channel material layer 542 is, for example, amorphous silicon (amorphous silicon) , α-Si), and the material of the ohmic contact layer 544 is, for example, heavily doped amorphous silicon (n+amorphous silicon, n+α-Si).

In order to make the drawings clearer, FIG. 5B shows the top view of FIG. 4D after the process. Referring to FIG. 4D and FIG. 5B , a second masking process is then performed to pattern the dielectric layer 530 and the semiconductor layer 540 to form a channel 328 above each gate 322 . In this step, the first conductive layer 520 of the pixel electrode pattern 350' is also removed simultaneously, and the transparent conductive layer 510 of the pixel electrode 350' is exposed to form a plurality of pixel electrodes 350. It is worth noting that the present invention forms a plurality of contact hole (contact window) openings 532 in the dielectric layer 530 and the semiconductor layer 540 to expose the data line pattern 342, wherein these contact hole openings 532 are located at both ends of the data line pattern 342 nearby. In this way, the multiple data line patterns 342 in the same row can be electrically connected to each other to form the data line 340 in subsequent processes.

In addition, in this step of this embodiment, part of the dielectric layer 530 and the semiconductor layer 540 above the pad 370 can be kept at the same time, and part of the first conductive layer 520 of the pad 370 is removed to expose the solder pad 370. Partially transparent conductive layer 510 . In addition, the dielectric layer 530 and the semiconductor layer 540 above the lower electrode 362 may also be retained.

Please refer to FIG. 4E, continue to form a second conductive layer 550 above the substrate, and the second conductive layer 550 will fill the contact hole opening 532 to form a plurality of contact holes 346, wherein each contact hole 346 is connected to a corresponding data line The patterns 342 are electrically connected. The material of the second conductive layer 550 may be selected from aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), titanium nitride (TiN), chromium (Cr), chromium nitride (CrN) or a combination thereof. In this embodiment, the second conductive layer 550 may be a three-layer stacked structure of titanium/aluminum/titanium nitride, wherein the preferred thickness of aluminum is between 500 Ȧ and 2000 Ȧ, and the thickness of titanium or titanium nitride A preferred thickness is between 300 Ȧ˜1000 Ȧ. In addition, the thickness of the first conductive layer 520 is greater than that of the second conductive layer 550 , for example.

Please refer to FIG. 4F and FIG. 3 , wherein FIG. 3 is also a top view after the process of FIG. 4F . Then a third masking process is performed to pattern the second conductive layer 550 to form a plurality of connection portions 344 , wherein the connection portions 344 are electrically connected to the corresponding contact holes 346 . In this way, the data line patterns 342 in the same row can be electrically connected to each other through the corresponding connecting portion 344 and the contact hole 346 to form the data line 340 . Since the data line 340 is mainly composed of the data line pattern 342, and the data line pattern 342 has the same electrical characteristics as the scan line 330 (both are the first conductive layer 520), so the overall surface resistance of the data line 340 will be the same as that of the scan line. The sheet resistance of 330 is similar. Therefore, the pixel array substrate 300 manufactured by the method disclosed in the present invention can improve the phenomenon of data signal transmission delay.

Following the above, in this step, the source electrode 324 and the drain electrode 326 are also formed simultaneously, wherein the drain electrode 326 is electrically connected to the corresponding pixel electrode 324 , and the source electrode 324 is electrically connected to the corresponding data line 342 . Specifically, the source electrode 324 is connected to the corresponding connecting portion 344 and is electrically connected to the data line pattern 342 through the contact hole 346 . In this way, the gate 322 , the source 324 , the drain 326 and the channel 328 constitute the active device 320 . Incidentally, in the present invention, part of the thickness of the channel 328 can also be removed in this step. Specifically, part of the ohmic contact layer 544 of the channel 328 can be removed, and part of the channel material of the channel 328 can be exposed. layer 542 to prevent the source 324 and the drain 326 from being short-circuited.

It is worth noting that the fabrication of the pixel array substrate 300 of the present invention is completed so far. Since the present invention only uses three masks to perform three mask processes to complete the fabrication of the pixel array substrate 300 , the fabrication cost of the pixel array substrate 300 can be reduced.

In addition, in this step of the present embodiment, a plurality of upper electrodes 364 may be formed, and the upper electrodes 364 are located on the semiconductor layer 540 above part of the lower electrodes 362 and are electrically connected to the corresponding pixel electrodes 350 . In this way, the lower electrode 362 and the upper electrode 364 can form a capacitor 360 to maintain a stable voltage of the pixel electrode 350 . In addition, part of the second conductive layer 550 above the pad 370 may also be removed, and in this embodiment, all of the second conductive layer 550 above the pad 370 is removed.

In order to further improve the quality of the pixel array substrate, the present invention can form a passivation layer (protective layer) to protect the underlying components, so that the pixel array substrate is not easily damaged by external influences. 4G-4J are schematic cross-sectional views of a manufacturing process for forming a passivation layer according to an embodiment of the present invention, wherein FIG. 4G is a process subsequent to FIG. 4F . Please refer to FIG. 4G. First, a passivation layer 560 and a photoresist layer 570 are formed above the substrate 310, wherein the material of the passivation layer 560 is, for example, silicon nitride, silicon oxide or silicon oxynitride to isolate the outside world. And the type of the photoresist layer 570 is, for example, positive photoresist. Then use the gate 322, the source 324, the drain 326, the scan line (not shown), the data line 340 and other elements (such as the capacitor 360) with a light-shielding effect as a mask to expose the photoresist layer 570 on the back side. craft.

Referring to FIG. 4H , a developing process is performed on the photoresist layer 570 afterwards, wherein the unexposed part of the photoresist layer 570 will not be developed to form a patterned photoresist layer 572 . Since the material of the pixel electrode 350 is composed of the transparent conductive layer 510 which can transmit light, the photoresist layer 570 above the pixel electrode 350 will be developed due to exposure to expose the passivation layer 560 . Similar to the above, since there is no light-shielding element above the part of the pad 370 , the passivation layer 560 above the part of the pad 370 will also be exposed.

Referring to FIG. 4I , the passivation layer 560 is then etched using the patterned photoresist layer 572 as a mask to expose the pixel electrode 350 and part of the pad 370 . Referring to FIG. 4J , finally, a stripper process is performed to remove the patterned photoresist layer 572 , that is, the fabrication of the pixel array substrate 300 with a passivation layer is completed. It is worth noting that in the above process of forming the passivation layer, the backside exposure process is completed by using the element with light-shielding effect as a mask, so there is no need to add an additional mask, so the production of the pixel array substrate 300 can be reduced. cost.

In the pixel array substrate of the foregoing embodiments, the data lines are electrically connected in a plurality of segmented data line patterns, so that the data lines have an area resistance similar to that of the scan lines to improve signal data delay. . However, the foregoing method is not intended to limit the present invention. For example, the present invention may also decompose the scan line into multiple scan line patterns, and then electrically connect these scan line patterns, which will be described below with reference to the accompanying drawings.

FIG. 6 is a partial top view of a pixel array substrate according to another embodiment of the present invention. Please refer to FIG. 6 , the pixel array substrate 600 of this embodiment is similar to the pixel array substrate 300 (as shown in FIG. 3 ), the difference is that each scanning line 630 includes a plurality of scanning line patterns 632 and a plurality of connecting parts 634, wherein The connection portions 634 are electrically connected to the scan line patterns 632 , and each connection portion 634 crosses over one of the data lines 640 , but is not electrically connected to the data lines 640 .

In addition, the manufacturing method of the pixel array substrate 600 is similar to the manufacturing method of the pixel array substrate 300 , and the differences will be described below. During the first mask process, in this embodiment, a plurality of scan line patterns 632 and data lines 640 are formed. During the second masking process, in this embodiment, contact hole openings (not shown) are formed above part of the scan line patterns 632 , and then contact holes are formed in the contact hole openings to electrically connect the scan line patterns 632 . During the third mask process, in this embodiment, the connecting portion 634 is formed, and the connecting portion 634 is electrically connected to the contact hole. In this way, the scan line patterns 632 in the same column can be electrically connected to each other through the corresponding connection portions 634 and contact holes to form the scan lines 630 . Those who are familiar with this art can refer to the above-mentioned embodiment to deduce it by themselves, so it will not be shown here.

Incidentally, the concept of segmentation in the present invention is not limited to be applicable only to scan lines or data lines. When any two different types of wires (such as common line, power line, repair line, etc.) must be arranged alternately and have similar electrical characteristics, this method can be used Invented the concept of segmentation, one of the wires is divided into multiple wire patterns, and then these wire patterns are electrically connected. Those who are familiar with this technique should be able to introduce it easily, so I won't repeat it here.

To sum up, the manufacturing method of the pixel array substrate of the present invention has at least the following advantages:

1. Compared with the prior art that requires five masks to fabricate the pixel array substrate, the present invention only needs to use three masks to complete the fabrication of the pixel array substrate, so the fabrication cost of the pixel array substrate can be reduced.

2. The manufacturing method of the pixel array substrate of the present invention is compatible with the existing process, so there is no need to add additional process equipment.

3. Since the data line pattern and the scan line are formed from the same material at the same time, they have the same electrical characteristics. In addition, the data lines are mainly composed of data line patterns, so the overall surface resistance of the data lines is similar to that of the scan lines, which can improve the transmission delay of data signals.

Although the present invention has been disclosed with specific embodiments, it is not intended to limit the present invention. Any person skilled in the art can make replacements of equivalent components without departing from the concept and scope of the present invention, or replace them according to the present invention. The equivalent changes and modifications made in the scope of patent protection should still fall within the scope of this patent.

Claims (14)

1. A method for manufacturing a pixel array substrate, comprising: sequentially forming a transparent conductive layer and a first conductive layer on a substrate; performing a first masking process to pattern the first conductive layer and the transparent conductive layer to form a plurality of gates, a plurality of scan lines electrically connected to the gates, a plurality of data line patterns and a plurality of pixel electrode pattern; sequentially forming a dielectric layer and a semiconductor layer over the substrate; performing a second masking process, patterning the dielectric layer and the semiconductor layer, forming a channel above each gate, and forming a plurality of contact hole openings exposing the data line pattern, and removing the first conductive layer of the pixel electrode pattern to form a plurality of pixel electrodes; A second conductive layer is formed on the substrate, and the second conductive layer will fill the opening of the contact hole to form a plurality of contact holes electrically connected to the data line pattern; and performing a third masking process to pattern the second metal layer to form a plurality of connection portions electrically connected to the contact holes, a plurality of source electrodes electrically connected to the data line patterns, and a plurality of drains electrically connected to the pixel electrodes, and removing the second conductive layer on each pixel electrode; Wherein, the data line patterns located in the same row are electrically connected to each other through the connecting portion and the contact hole to form a data line. 2. The method for manufacturing a pixel array substrate according to claim 1, further comprising: after the third masking process: sequentially forming a passivation layer and a photoresist layer on the substrate; Using the gate, the source, the drain, the scan line and the data line as a mask, perform a back exposure process and a development process to form a patterned photoresist layer; etching the passivation layer using the patterned photoresist layer as a mask to expose the pixel electrode; and The patterned photoresist layer is removed. 3. The method for manufacturing a pixel array substrate according to claim 1, characterized in that: In the first masking process, it further includes forming a plurality of welding pads, and each welding pad is connected to one end of the corresponding scanning line or the data line; In the second masking process, further comprising retaining part of the dielectric layer and part of the semiconductor layer above the pad, and removing part of the first conductive layer of the pad; and In the third masking process, it further includes removing part of the second conductive layer above the pad. 4. The method for manufacturing a pixel array substrate according to claim 1, characterized in that: In the first masking process, it further includes forming a plurality of lower electrodes; In the second masking process, further comprising retaining the dielectric layer and the semiconductor layer above the lower electrode; and In the third masking process, it further includes forming a plurality of upper electrodes on the semiconductor layer above part of the lower electrodes; Wherein, the lower electrode and the upper electrode form a plurality of capacitors, and each lower electrode is electrically connected to the corresponding scanning line, and each upper electrode is electrically connected to the corresponding pixel electrode. 5 . The method for manufacturing a pixel array substrate as claimed in claim 1 , further comprising removing part of the thickness of the channel in the third masking process. 5 . 6. The method of manufacturing a pixel array substrate as claimed in claim 1, wherein the semiconductor layer comprises a channel material layer and an ohmic contact material layer. 7. The method for manufacturing a pixel array substrate as claimed in claim 1, wherein the thickness of the first conductive layer is greater than that of the second conductive layer. 8. A method for manufacturing a pixel array substrate, comprising: sequentially forming a transparent conductive layer and a first conductive layer on a substrate; performing a first mask process to pattern the first conductive layer and the transparent conductive layer to form a plurality of gates, a plurality of scan line patterns electrically connected to the gates, a plurality of data lines and a plurality of a pixel electrode pattern; sequentially forming a dielectric layer and a semiconductor layer over the substrate; performing a second mask process, patterning the dielectric layer and the semiconductor layer, forming a channel above each of the gates, and forming a plurality of contact hole openings exposing the scanning line pattern, and removing the first conductive layer of the pixel electrode pattern to form a plurality of pixel electrodes; forming a second conductive layer on the substrate, and the second conductive layer will fill the opening of the contact hole to form a plurality of contact holes electrically connected to the scanning line pattern; and performing a third masking process to pattern the second metal layer to form a plurality of connecting portions electrically connected to the contact holes, a plurality of sources electrically connected to the data lines, and a plurality of sources electrically connected to the The pixel electrodes are electrically connected to a plurality of drain electrodes, and the second conductive layer on each pixel electrode is removed; Wherein, the scan line patterns located in the same column are electrically connected to each other through the connecting portion and the contact hole to form a scan line. 9. The method for manufacturing a pixel array substrate according to claim 8, further comprising: after the third masking process: sequentially forming a passivation layer and a photoresist layer on the substrate; Using the gate, the source, the drain, the scan line and the data line as a mask, perform a back exposure process and a development process to form a patterned photoresist layer; etching the passivation layer using the patterned photoresist layer as a mask to expose the pixel electrode; and The patterned photoresist layer is removed. 10. The method for manufacturing a pixel array substrate according to claim 8, characterized in that: In the first masking process, it further includes forming a plurality of welding pads, and each welding pad is connected to one end of the corresponding scanning line or the data line; In the second masking process, further comprising retaining part of the dielectric layer and part of the semiconductor layer above the pad, and removing part of the first conductive layer of the pad; and In the third masking process, it further includes removing part of the second conductive layer above the pad. 11. The method for manufacturing a pixel array substrate according to claim 8, characterized in that: In the first masking process, it further includes forming a plurality of lower electrodes; In the second masking process, further comprising retaining the dielectric layer and the semiconductor layer above the lower electrode; and In the third masking process, it further includes forming a plurality of upper electrodes on the semiconductor layer above part of the lower electrodes; Wherein, the lower electrode and the upper electrode form a plurality of capacitors, and each lower electrode is electrically connected to the corresponding scanning line, and each upper electrode is electrically connected to the corresponding pixel electrode. 12 . The method for manufacturing a pixel array substrate as claimed in claim 8 , further comprising removing part of the thickness of the channel in the third masking process. 13 . 13. The method for manufacturing a pixel array substrate as claimed in claim 8, wherein the semiconductor layer comprises a channel material layer and an ohmic contact material layer. 14. The method for manufacturing a pixel array substrate as claimed in claim 8, wherein the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

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