CN1738034A - Integrated circuit or discrete component flat array bump package structure - Google Patents
Integrated circuit or discrete component flat array bump package structure Download PDFInfo
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- CN1738034A CN1738034A CN200510041043.5A CN200510041043A CN1738034A CN 1738034 A CN1738034 A CN 1738034A CN 200510041043 A CN200510041043 A CN 200510041043A CN 1738034 A CN1738034 A CN 1738034A
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Abstract
本发明涉及一种集成电路或分立元件平面阵列凸点式封装结构，属集成电路或分立元件技术领域。包括基岛(1)、芯片(2)、功能输出脚(3)以及塑封体(5)，所述的功能输出脚(3)分布于基岛(1)的外圈和外侧，芯片(2)放置于基岛(1)上，其特征在于：所述的塑封体(5)外部的基岛(1)和功能输出脚(3)凸出于塑封体(5)表面；所述的基岛(1)有单个基岛或多个基岛；所述的功能输出脚(3)有圈状分布的，也有排状分布的，圈状的有单圈或/和多圈，排状的有单排或/和多排；所述的芯片(2)有单颗或多颗。本发明生产顺畅、良率提高，成本低廉，品质优良，可靠性高，散热性高。
The invention relates to an integrated circuit or discrete component planar array bump package structure, which belongs to the technical field of integrated circuits or discrete components. It includes a base island (1), a chip (2), a functional output pin (3) and a plastic package (5), the functional output pin (3) is distributed on the outer circle and the outside of the base island (1), and the chip (2 ) placed on the base island (1), characterized in that: the base island (1) outside the plastic package (5) and the functional output pin (3) protrude from the surface of the plastic package (5); the base The island (1) has a single base island or multiple base islands; the functional output feet (3) are distributed in a circle or in a row, and the circle has a single circle or/and multiple circles, and a row There are single row or/and multiple rows; the chip (2) has single or multiple chips. The invention has smooth production, improved yield, low cost, good quality, high reliability and high heat dissipation.
Description
Technical field:
The present invention relates to a kind of integrated circuit or discrete component, be specifically related to a kind of integrated circuit or discrete component flat array bump package structure. Belong to integrated circuit or discrete component encapsulation technology field.
Background technology:
Before the present invention made, traditional integrated circuit or discrete component packing forms mainly contained four limits without pin surface label chip encapsulation (QFN) and spherical array encapsulation (BGA) two kinds, and there is certain deficiency separately in they, now are described below:
| Four limits encapsulate without pin surface label chip | Spherical array encapsulation | |
| One, the collocation form of Ji Dao and chip | Adopt total eclipse to carve and add the lead frame of adhesive tape, limit, can only make single Ji Dao in the same packaging body and be subjected to total eclipse to carve the lead frame ability, and the performance of the ability of single Ji Dao is limited. | Adopt the plastic circuit substrate can accomplish that single basic island single-chip, many of single Ji Dao arrange chip, single basic island multiple-level stack chip, in same packaging body, can also accomplish many modes of emplacements of arranging chip and how basic island multiple-level stack chip of many Ji Dao, but the cost of plastic circuit substrate is higher. |
| Two, the difference mode of plastic-sealed body external energy output pin | Adopt total eclipse to carve and add the lead frame of adhesive tape, limit and be subjected to total eclipse to carve the lead frame ability, outside individual pen or the single function output pin only may accomplished of plastic-sealed body distributes. | Because adopting the plastic circuit substrate, the distribution form of external function output pin can be individual pen, multi-turn, single, many rows etc.; But there is equally the higher problem of plastic circuit substrate cost. |
| Three, the protrusion performance of plastic-sealed body external function output pin | The ability that is subjected to total eclipse to carve the lead frame that adds adhesive tape is limit, and can't accomplish that the function output pin of plastic-sealed body outside protrudes from the plastic-sealed body bottom; So function output pin is relative relatively poor with the Weldability between printed circuit board (PCB), and produce easily the problem of tin cream short circuit in the welding process. | Limit by the ability of plastic circuit substrate, can't accomplish directly that the function output pin of plastic-sealed body outside protrudes from the plastic-sealed body surface, so for output pin being protruded and having increased the expensive tin ball technique of planting. |
| Four, the coplanar ability of Ji Dao and function pin | Adopt total eclipse to carve the lead frame that adds adhesive tape, be easy in process of production produce function output pin and be depressed in the plastic-sealed body centre and cause the bad problem of paster contact. | The mode of tin ball is implanted in employing in plastic circuit substrate bottom, but the tin ball can't be implanted on the Ji Dao, thereby makes Ji Dao and tin ball that the size dimension inequality often be arranged again and the bad problem of contact when causing paster, |
| The tin ball also often has the phenomenon of ball and causes the problem that lacks ball in addition. | ||
| Five, Ji Dao exposes the heat-sinking capability of colloid bottom | Adopt total eclipse to carve the lead frame that adds adhesive tape and can make the Ji Dao of heat transmission be exposed to the plastic-sealed body bottom, but can't protrude from the bottom of plastic-sealed body, can not utilize air to dispel the heat. | Adopt the plastic circuit substrate can make Ji Dao be exposed to the plastic-sealed body bottom, and the plastic circuit substrate is indirectly to conduct heat to bottom, basic island by the mode that goes between, the air of Ji Dao recycling border dispels the heat, but the heat radiation resistance of air is larger, radiating efficiency is very poor, and in the lead-in wire process even can badly influence because heat amasss on the plastic circuit plate reliability performance of plastic circuit plate. |
| Six, chip | Single chip: take storage chip as example, the storage volume of its single chip is 128MB, because only having one chip on the Ji Dao, so maximum storage volume also only has 128MB. | Arrange chip for many: for example simultaneously placement stores with chip and power protection chip on same Ji Dao, thereby can protect storage chip to avoid dashing forward the injury of unstable power supply. |
| Seven, chip and output function pin | Single-chip, individual pen are or/and single: individual pen/row and a small amount of I/O (input and output signal) be if change multi-turn into or/and arrange function output pin more, and its package dimension can be than original to when young 1/4th. Key is different chips or packing forms, and the size of single packaging body is saved and also had nothing in common with each other. | Arrange chip, circle or/and row for many: may come according to the needs of product the chip of integrated or many difference in functionalitys, be packaged into many and arrange chips, multi-turn or/and arrange the integrated circuit of function output pin more; Single the chip individual packages face of comparing says that it can economize the at the most space of a packaging body of next base. Key is that the quantity of the chip that is arranged in parallel is different, and the size of packaging body can be different. |
Summary of the invention:
The object of the invention is to overcome above-mentioned deficiency, provide that a kind of production is smooth and easy, yield improves, with low cost, best in quality, reliability is high, the integrated circuit that thermal diffusivity is high or discrete component flat array bump package structure.
The object of the present invention is achieved like this: a kind of integrated circuit or discrete component flat array bump package structure, comprise Ji Dao, chip, function output pin and plastic-sealed body, described function output pin is distributed in outer ring and the outside of Ji Dao, and chip is positioned on the Ji Dao, it is characterized in that:
Ji Dao and the function output pin of described plastic-sealed body outside protrude from the plastic-sealed body surface;
Described Ji Dao has single Ji Dao or a plurality of Ji Dao;
Described function output pin has round to distribute, and also has row's shape to distribute, round individual pen is arranged or/and multi-turn, row's shape have single or/and many rows;
Described chip has single or many.
Compared with prior art, the present invention adopts plane salient point array encapsulation (FBP BGA) to have following advantage:
One, the collocation form of Ji Dao and chip:
The mode that the metal substrate employing etches partially is arranged in pairs or groups behind the circuit finish layer again, can accomplish that equally single basic island single-chip, many of single Ji Dao arrange chip, single basic island multiple-level stack chip, can accomplish equally that in same packaging body many of many Ji Dao arrange the modes of emplacements such as chip and how basic island multiple-level stack chip; And the cost of metal substrate is lower. The cost of plastic circuit substrate exceeds more than the twice at least than the metal substrate material cost of plane salient point array encapsulation.
Two, the difference mode of plastic-sealed body external function output pin:
Metal substrate adopts twice etched mode can easily reach the multiple distribution mode of plastic-sealed body external function output pin, as individual pen, multi-turn, single, arrange and the row of circle is mixed etc. more, and cost is lower.
Three, the protrusion performance of plastic-sealed body external function output pin
The function output pin that metal substrate adopts twice etched mode can easily reach the plastic-sealed body outside protrudes from the surface of plastic-sealed body.
Four, the coplanar ability of Ji Dao and function output pin:
Metal substrate adopts twice etched mode to guarantee the absolute coplanarity of Ji Dao and function output pin, and the problem that can never have function output pin to fall, lack, cave in produces.
Five, Ji Dao exposes the heat-sinking capability of plastic-sealed body bottom
Metal substrate adopts the mode of second etch to make the Ji Dao of heat transmission directly expose and protrude from the bottom of plastic-sealed body, and Ji Dao is welded on the printed circuit board (PCB) with function output pin; So, when utilizing air to dispel the heat, the heat energy that chip changes into because of electric energy directly can also be seen through rapidly printed circuit board (PCB) and dissipate away.
Six, multiple-level stack chip
Take storage chip as example, the storage volume of its single chip is 128MB, on Ji Dao, can make storage volume increase to 256MB during stacking two chips, by that analogy, can make storage volume increase to 512MB in the time of stacking four, but the size of packaging body can not become greatly, thereby has strengthened the utilization rate of the useful space.
Seven, multiple-level stack chip, circle are or/and row
The vertical stack chip be can come according to the needs of product, multiple-level stack chip, multi-turn are packaged into or/and arrange the integrated circuit of function output pin after can adding in case of necessity the circuit finish layer more again; Single the chip individual packages of comparing, it can economize the space of next even many packaging bodies. Key is the different of the quantity of vertical stack chip and stacked group number, and the size of packaging body also can be different.
Description of drawings:
Fig. 1 embodiments of the invention 1 cross section structural representation.
Fig. 2 (a), (b)～5 (a), (b) are that embodiments of the invention 6 planes and O-O facade are arranged schematic diagram.
Fig. 6 (a), (b), 7 (a), (b) are that embodiments of the invention 7 planes and O-O facade are arranged schematic diagram.
Fig. 8 (a), (b)～20 (a), (b) are that embodiments of the invention 28 planes and O-O facade are arranged schematic diagram.
Figure 21 (a), (b)～22 (a), (b) are that embodiments of the invention 29 planes and O-O facade are arranged schematic diagram.
Figure 23 (a), (b)～25 (a), (b) are that embodiments of the invention 30 planes and O-O facade are arranged schematic diagram.
Figure 26 (a), (b) are that embodiments of the invention 34 planes and O-O facade are arranged schematic diagram.
The specific embodiment:
Embodiment 1:
Referring to Fig. 1, adopt integrated circuit of the present invention or discrete component flat array bump package structure, mainly formed by basic island 1, chip 2, function output pin 3, gold thread 4 and plastic-sealed body 5. Described function output pin 3 is distributed in outer ring and the outside on basic island 1, and described chip 2 is positioned on the basic island 1. Gold thread 4 is connected between chip 2 and the function output pin 3, and described basic island 1, chip 2, function output pin 3 and gold thread 4 are all sealed with plastic-sealed body 5, and makes the basic island 1 of plastic-sealed body outside and function output pin 3 protrude from plastic-sealed body 5 surfaces. Described function output pin 3 comprises metal level 3.1, active layer 3.2, metal substrate layer 3.3, active layer 3.4 and metal level 3.5 from the inside to the outside successively. The surface that function output pin 3 protrudes from plastic-sealed body 5 is coated by outer active layer 3.4 and outer layer metal layer 3.5. Described basic island 1 comprises metal level 1.1, active layer 1.2, metal substrate layer 1.3, active layer 1.4 and metal level 1.5 from the inside to the outside successively, and the surface that basic island 1 protrudes from plastic-sealed body 5 is coated by outer active layer 1.4 and outer layer metal layer 1.5.
There are single Ji Dao or a plurality of Ji Dao in described basic island 1; Described function output pin 3 has round to distribute, and also has row's shape to distribute, round individual pen is arranged or/and multi-turn, row's shape have single or/and many rows; Described chip 2 has single or many.
In addition: above-described embodiment 1 can also have several special cases:
1) inside and outside two-layer active layer 3.2,3.4 and 1.2,1.4 also can be save in function output pin 3 and basic island 1.
2) function output pin 3 and basic island 1 part that protrudes from plastic-sealed body 5 only have bottom face by outer active layer 3.4,1.4 and outer layer metal layer 3.5,1.5 coat, and remainder is not wrapped by.
3) inside and outside two-layer active layer 3.2,3.4 and 1.2,1.4 is save on function output pin 3 and basic island 1, and the part that function output pin 3 and basic island 1 protrude from plastic-sealed body only has bottom face to be coated by outer layer metal layer 3.5,1.5, and all the other surface portions are not wrapped by.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail:
Embodiment 2: single Ji Dao/individual pen, single function output pin/single-chip
Described Ji Dao has single, and the function output pin of single Ji Dao outer ring has individual pen, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of single Ji Dao, and the chip on single Ji Dao has single.
Embodiment 3: single Ji Dao/individual pen, arrange function output pin/single-chip more
Described Ji Dao has single, and the function output pin of single Ji Dao outer ring has individual pen, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in single Ji Dao more, and the chip on single Ji Dao has single.
Embodiment 4: single Ji Dao/multi-turn, single function output pin/single-chip
Described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of single Ji Dao, and the chip on single Ji Dao has single.
Embodiment 5: single Ji Dao/multi-turn, arrange function output pin/single-chip more
Described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in single Ji Dao more, and the chip on single Ji Dao has single.
Embodiment 6: single Ji Dao/individual pen, single function output pin/multi-chip
Referring to Fig. 2～5, described Ji Dao has single, the function output pin of single Ji Dao outer ring has individual pen, the function output pin in the outside has single, single function output pin is arranged in a side or the many sides (being a side among Fig. 2, is both sides among Fig. 3,4, is three sides among Fig. 5) of single Ji Dao, chip on single Ji Dao has many, and many arrangements of chip on Ji Dao have to be arranged or/and stacking.
Embodiment 7: single Ji Dao/individual pen, arrange function output pin/multi-chip more
Referring to Fig. 6～7, described Ji Dao has single, the function output pin of single Ji Dao outer ring has individual pen, the function output pin in the outside has many rows, a side or many sides that many row's function output pins are arranged in single Ji Dao (are both sides among Fig. 6, three sides among Fig. 7), the chip on single Ji Dao has many, and the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 8: single Ji Dao/multi-turn, single function output pin/multi-chip
Described Ji Dao has single, the function output pin of single Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of single Ji Dao, chip on single Ji Dao has many, and the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 9: single Ji Dao/multi-turn, arrange function output pin/multi-chip more
Described Ji Dao has single, the function output pin of single Ji Dao outer ring has multi-turn, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in single Ji Dao more, chip on single Ji Dao has many, and the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 10: many Ji Dao/individual pens, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 11: many Ji Dao/individual pens, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 12: many Ji Dao/individual pens, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has single, and many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 13: many Ji Dao/multi-turns, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 14: many Ji Dao/multi-turns, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 15: many Ji Dao/multi-turns, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 16: many Ji Dao/individual pens, multi-turn, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 17: many Ji Dao/individual pens, multi-turn, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 18: many Ji Dao/individual pens, multi-turn, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, the function output pin in the outside has single, many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, and single chip is arranged on each Ji Dao in the how basic island.
Embodiment 19: many Ji Dao/individual pens, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 20: many Ji Dao/individual pens, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 21: many Ji Dao/individual pens, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and the function output pin in the outside has single, and many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips are arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 22: many Ji Dao/multi-turns, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 23: many Ji Dao/multi-turns, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 24: many Ji Dao/multi-turns, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has multi-turn, and the function output pin in the outside has single, and many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips are arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 25: many Ji Dao/individual pens, multi-turn, single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, and the function output pin in the outside has single, and single function output pin is arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 26: many Ji Dao/individual pens, multi-turn, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, and the function output pin in the outside has many rows, arranges a side or many sides that function output pin is arranged in Ji Dao more, on each Ji Dao multiple chips is arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 27: many Ji Dao/individual pens, multi-turn, single, arrange function output pin/multi-chip more
Described Ji Dao has a plurality of, and the function output pin of Ji Dao outer ring has individual pen, and multi-turn is also arranged, the function output pin in the outside has single, many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on each Ji Dao multiple chips are arranged in the how basic island. The arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 28: many Ji Dao/individual pens, single function output pin/list, multi-chip
Referring to Fig. 8～20, described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, the function output pin in the outside has single, single function output pin is arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 29: many Ji Dao/individual pens, arrange function output pin/list, multi-chip more
Referring to Figure 21～22, described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, the function output pin in the outside has many rows, many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 30: many Ji Dao/individual pens, single, arrange function output pin/list, multi-chip more
Referring to Figure 23～25, described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, the function output pin in the outside has single, many rows are also arranged, and single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip are arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 31: many Ji Dao/multi-turns, single function output pin/list, multi-chip
Described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has multi-turn, the function output pin in the outside has single, single function output pin is arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 32: many Ji Dao/multi-turns, arrange function output pin/list, multi-chip more
Described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has multi-turn, the function output pin in the outside has many rows, many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 33: many Ji Dao/multi-turns, single, arrange function output pin/list, multi-chip more
Described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has multi-turn, the function output pin in the outside has single, many rows are also arranged, single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 34: many Ji Dao/individual pens, multi-turn, single function output pin/list, multi-chip
Described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, multi-turn is also arranged, the function output pin in the outside has single, single function output pin is arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 35: many Ji Dao/individual pens, multi-turn, arrange function output pin/list, multi-chip more
Described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, multi-turn is also arranged, the function output pin in the outside has many rows, many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 36: many Ji Dao/individual pens, multi-turn, single, arrange function output pin/list, multi-chip more
Referring to Figure 26, described Ji Dao has a plurality of, the function output pin of Ji Dao outer ring has individual pen, multi-turn is also arranged, and the function output pin in the outside has single, and many rows are also arranged, single and many row's function output pins are arranged in a side or the many sides of Ji Dao, on the Ji Dao that has in a plurality of basic islands single chip is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Claims (40)
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510041043.5A CN1738034A (en) | 2005-07-02 | 2005-07-02 | Integrated circuit or discrete component flat array bump package structure |
| US11/910,893 US20080285251A1 (en) | 2005-04-07 | 2006-04-06 | Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same |
| PCT/CN2006/000608 WO2006105734A1 (en) | 2005-04-07 | 2006-04-06 | A packaging substrate with flat bumps for electronic devices and method of manufacturing the same |
| US11/910,878 US20080258273A1 (en) | 2005-04-07 | 2006-04-06 | Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same |
| PCT/CN2006/000607 WO2006105733A1 (en) | 2005-04-07 | 2006-04-06 | Package structure with flat bumps for electronic device and method of manufacture the same |
| PCT/CN2006/000609 WO2006105735A1 (en) | 2005-04-07 | 2006-04-06 | Package structure with flat bumps for integrate circuit or discrete device and method of manufacture the same |
| PCT/CN2006/000610 WO2006122467A1 (en) | 2005-04-07 | 2006-04-06 | A packaging substrate with flat bumps for ic or discrete device and method of manufacturing the same |
| US11/910,885 US20080315412A1 (en) | 2005-04-07 | 2006-04-06 | Package Structure with Flat Bumps for Integrate Circuit or Discrete Device and Method of Manufacture the Same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510041043.5A CN1738034A (en) | 2005-07-02 | 2005-07-02 | Integrated circuit or discrete component flat array bump package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1738034A true CN1738034A (en) | 2006-02-22 |
Family
ID=36080768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200510041043.5A Pending CN1738034A (en) | 2005-04-07 | 2005-07-02 | Integrated circuit or discrete component flat array bump package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1738034A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413801A (en) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | DFN package lead frame |
| CN104681509A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Improved double-base-island packaging structure |
-
2005
- 2005-07-02 CN CN200510041043.5A patent/CN1738034A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413801A (en) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | DFN package lead frame |
| CN104681509A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Improved double-base-island packaging structure |
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