CN1738037A - Integrated circuit or discrete component flat bump combination package structure - Google Patents

Abstract

The invention relates to an integrated circuit or discrete component planar bump combined packaging structure, which belongs to the technical field of integrated circuits or discrete components. It includes a base island (1), a chip (2), a functional output pin (3) and a plastic package (5), and the functional output pin (3) is distributed on the outer ring or/and outside of the base island (1), The chip (2) is placed on the base island (1), and it is characterized in that: the base island (1) outside the plastic package (5) and the functional output pin (3) protrude from the surface of the plastic package (5); The base island (1) has a single base island or multiple base islands; the functional output feet (3) are distributed in circles, or in rows, or mixed in circles and rows; There are single or multiple chips (2). The invention has smooth production, improved yield, low cost, good quality, high reliability and high heat dissipation.

Description

Integrated circuit or discrete component planar bump package structure

Technical field:

The invention relates to an integrated circuit or a discrete component, in particular to an integrated circuit or a discrete component planar bump package structure. It belongs to the technical field of packaging of integrated circuits or discrete components.

Background technique:

Before the present invention was made, the traditional integrated circuit or discrete component packaging forms mainly contained two kinds of four-sided non-foot surface mount packages (QFN) and ball array packages (BGA), and they each had certain deficiencies, which are now described as follows : Quadruple leadless surface mount package Ball Array Package 1. The matching form of base island and chip A fully etched lead frame with tape is used, but limited by the capacity of the fully etched lead frame, only a single base island can be fabricated in the same package, and the capability of a single base island is limited. The use of plastic circuit substrates can achieve single-base island single chip, single-base island multiple array chips, single-base island multi-layer stacked chips, and multi-base island multiple array chips and multi-base island multi-layer in the same package. Stacked chips are placed, but the cost of the plastic circuit substrate is relatively high. 2. How to separate the output pins from the outside of the plastic package The lead frame with full etching and tape is used, but due to the limitation of the capacity of the full etching lead frame, it is only possible to achieve single-turn or single-row functional output pin distribution outside the plastic package. Due to the use of plastic circuit boards, the distribution of external function output pins can be single-turn, multi-turn, single-row, multi-row, etc.; but there is also the problem of high cost of plastic circuit boards. 3. The protruding performance of the external functional output pin of the plastic package Limited by the ability of the fully etched lead frame with adhesive tape, it is impossible to make the functional output pin outside the plastic package protrude from the bottom of the plastic package; therefore, the soldering ability between the functional output pin and the printed circuit board is relatively poor, and during the soldering process It is easy to cause the problem of solder paste short circuit. Limited by the capacity of the plastic circuit board, it is impossible to directly protrude the functional output pins outside the plastic package from the surface of the plastic package. Therefore, in order to make the output pins protrude, a high-cost solder ball planting process is added. 4. The coplanarity of base island and functional foot The lead frame with full etching and tape is easy to produce the problem that the functional output pin is sunken in the middle of the plastic package during the production process, resulting in a bad patch contact. The method of implanting solder balls on the bottom of the plastic circuit board is adopted, but the solder balls cannot be implanted on the base island, so that the base island and the solder balls often have uneven sizes, resulting in poor contact during placement. In addition, tin balls often fall off the ball and cause the problem of missing balls. 5. The base island exposes the heat dissipation capacity of the bottom of the colloid The lead frame with full etching and adhesive tape can expose the base island for heat dissipation at the bottom of the plastic package, but cannot protrude from the bottom of the plastic package, and cannot use air to dissipate heat. Using a plastic circuit board can make the base island exposed at the bottom of the plastic package, and the plastic circuit board indirectly conducts heat to the bottom of the base island through leads, and the base island uses the surrounding air to dissipate heat, but the heat dissipation resistance of the air is relatively large , the heat dissipation efficiency is very poor, and the reliability of the plastic circuit board will be seriously affected due to heat accumulation on the plastic circuit board during the wiring process. 6. Chip Single chip: Taking a memory chip as an example, the storage capacity of a single chip is 128MB, and there is only a single chip on the Genesis Island, so the maximum storage capacity is only 128MB. Multiple array chips: For example, a storage chip and a power protection chip are placed on the same base island at the same time, so that the storage chip can be protected from sudden and unstable power supply. 7. Chip and output function pin Single-chip, single-turn or/and single-row: If a small number of I/O (input and output signals) are changed to multi-turn or/and multi-row function output pins for single-turn/row, the package size can be at least four times smaller than the original one-third. The key lies in the different chip or package forms, and the size savings of a single package are also different. Multiple array chips, circles or/and rows: It is possible to integrate one or more chips with different functions according to the needs of the product, and package them into an integrated circuit with multiple array chips, multiple circles or/and multiple rows of functional output pins; Compared with the independent packaging of a single chip, it can save the space of one base to multiple packages. The key is that the size of the package will vary depending on the number of chips arranged in parallel.

Invention content:

The object of the present invention is to overcome the above disadvantages and provide a planar bump package structure for integrated circuits or discrete components with smooth production, improved yield, low cost, high quality, high reliability and high heat dissipation.

The object of the present invention is achieved in this way: an integrated circuit or discrete component planar bump package structure, including a base island, a chip, a functional output pin and a plastic package, and the described functional output pin is distributed on the outer ring of the base island Or/and outside, the chip is placed on the base island, characterized in that:

The base island outside the plastic package and the functional output pin protrude from the surface of the plastic package;

The base island has a single base island or multiple base islands;

The functional output pins are distributed in circles, or in rows, or mixed in circles and rows;

There are single or multiple chips.

Compared with the prior art, the present invention adopts the planar bump bump package (FBP BGA) and has the following advantages:

1. The matching form of base island and chip:

After the metal substrate is semi-etched and matched with the line finishing layer, it can also achieve single-base island single chip, single-base island multi-chip array, single-base island multi-layer stacked chip, and multi-base island in the same package. Placement methods such as multiple array chips on the island and multi-layer stacked chips on the multi-base island; and the cost of the metal substrate is relatively low. The cost of the plastic circuit substrate is at least two times higher than the material cost of the metal substrate of the planar bump array package.

2. How to separate the output pins of the external functions of the plastic package:

The metal substrate can be etched twice to easily achieve various distribution methods of the external functional output pins of the plastic package, such as single-turn, multi-turn, single-row, multi-row, and mixed-row, etc., and the cost is low.

3. The protruding performance of the external functional output pin of the plastic package

The metal substrate is etched twice to easily achieve the function outside the plastic package. The output pin protrudes from the surface of the plastic package.

4. The coplanarity between the base island and the function output pin:

The metal substrate is etched twice to ensure the absolute coplanarity between the base island and the functional output pins, and there will be absolutely no problems of missing, missing, or recessed functional output pins.

5. The base island exposes the heat dissipation capacity of the bottom of the plastic package:

The metal substrate adopts secondary etching to directly expose the base island for heat dissipation and protrude from the bottom of the plastic package, and the base island and the functional output pin are welded on the printed circuit board together; therefore, while using air for heat dissipation, it also The heat energy converted by the chip due to electrical energy can be dissipated directly and quickly through the printed circuit board.

6. Multi-layer stacked chips

Taking the storage chip as an example, the storage capacity of a single chip is 128MB. When two chips are stacked on the base island, the storage capacity can be increased to 256MB. By analogy, when four chips are stacked, the storage capacity can be increased to 512MB. However, The size of the package body will not become larger, thereby enhancing the utilization rate of the effective space.

7. Multi-layer stacked chips, circles or/and rows

Chips can be stacked vertically according to the needs of the product, and if necessary, a line finishing layer can be added and then packaged into an integrated circuit with multi-layer stacked chips, multi-turn or/and multi-row functional output pins; compared with the independent packaging of a single chip, It can save the space of one or more packages. The key lies in the difference in the number of vertically stacked chips and the number of stacked groups, and the size of the package will also be different.

Description of drawings:

Fig. 1 is a cross-sectional schematic diagram of Embodiment 1 of the present invention.

Fig. 2 (a), (b) is respectively the plane and O-O elevation layout diagram of Embodiment 2 of the present invention.

Fig. 3 (a), (b) is respectively the plane and O-O elevation layout diagram of Embodiment 4 of the present invention.

Fig. 4(a), (b) are the plane and O-O elevation layout diagrams of Embodiment 13 of the present invention, respectively.

Fig. 5(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 14 of the present invention.

Fig. 6(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 15 of the present invention.

Fig. 7(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 16 of the present invention.

Figures 8(a), (b)-9(a), (b) are the plane and O-O elevation layout views of Embodiment 17 of the present invention.

Figure 10 (a), (b) is the plan and O-O elevation layout diagram of Embodiment 18 of the present invention.

Figures 11(a), (b)-12(a), (b) are the plane and O-O elevation layout views of Embodiment 19 of the present invention.

Fig. 13(a), (b) are the plan and O-O elevation layout diagrams of Embodiment 20 of the present invention.

Figures 14(a), (b)-15(a), (b) are the plane and O-O elevation layout views of Embodiment 29 of the present invention.

Fig. 16(a), (b) are the plan and O-O elevation layout diagrams of Embodiment 30 of the present invention.

Figure 17 (a), (b) is the plane and O-O elevation layout diagram of Embodiment 31 of the present invention.

Figure 18 (a), (b) is the plan and O-O elevation layout diagram of Embodiment 32 of the present invention.

Figures 19(a), (b)-22(a), (b) are the plane and O-O elevation layout views of Embodiment 37 of the present invention.

Figure 23(a), (b), 24(a), (b) are the plan and O-O elevation layout diagrams of Embodiment 38 of the present invention.

Figures 25(a), (b)-37(a), (b) are the plan and O-O elevation layout views of Embodiment 59 of the present invention.

Figures 38(a), (b)-39(a), (b) are the plan and O-O elevation layout views of Embodiment 60 of the present invention.

Figures 40(a), (b)-42(a), (b) are the plane and O-O elevation layout views of Embodiment 61 of the present invention.

Figure 43 (a), (b) is the plan and O-O elevation layout diagram of Embodiment 65 of the present invention.

Detailed ways:

Example 1:

Referring to FIG. 1 , the integrated circuit or discrete component planar-bump combined package structure of the present invention is mainly composed of a base island 1 , a chip 2 , a functional output pin 3 , a gold wire 4 and a plastic package 5 . The functional output pins 3 are distributed on the outer circle and outside of the base island 1 , and the chip 2 is placed on the base island 1 . The gold wire 4 is connected between the chip 2 and the functional output pin 3, and the base island 1, the chip 2, the functional output pin 3 and the gold wire 4 are all encapsulated with a plastic package 5, and the base island 1 outside the plastic package is And the functional output pin 3 protrudes from the surface of the plastic package body 5 . The functional output pin 3 sequentially includes a metal layer 3.1, an activation layer 3.2, a metal substrate layer 3.3, an activation layer 3.4 and a metal layer 3.5 from inside to outside. The surface of the functional output pin 3 protruding from the plastic package 5 is covered by the outer activation layer 3.4 and the outer metal layer 3.5. The base island 1 sequentially includes a metal layer 1.1, an activation layer 1.2, a metal substrate layer 1.3, an activation layer 1.4 and a metal layer 1.5 from inside to outside, and the surface of the base island 1 protruding from the plastic package 5 is covered by an outer activation layer 1.4 And outer metal layer 1.5 coating.

The base island 1 has a single base island or multiple base islands; the functional output pins 3 are distributed in circles, in rows, or mixed in circles and rows. The said chip 2 has single or multiple chips.

In addition: above-mentioned embodiment 1 also can have several special cases:

1) The function output pin 3 and the base island 1 can also save the inner and outer activation layers 3.2, 3.4 and 1.2, 1.4.

2) Only the bottom end surface of the functional output pin 3 and base island 1 protruding from the plastic package 5 is plated by the outer activation layer 3.4, 1.4 and the outer metal layer 3.5, 1.5, while the rest is not plated.

3) The functional output pin 3 and the base island 1 omit the inner and outer activation layers 3.2, 3.4 and 1.2, 1.4, and the part of the functional output pin 3 and the base island 1 protruding from the plastic package is only covered by the outer layer of metal Layers 3.5, 1.5 are plated, while the rest of the surface part is not plated.

The specific embodiment of the present invention is described in further detail below in conjunction with accompanying drawing:

The present invention has three sets of schemes

Option 1: The functional output pins are distributed in a circle, and the circle has a single circle or/and multiple circles. See Examples 2-16 for details.

Solution 2: The functional output pins are arranged in a row, and the row has a single row or/and multiple rows. See Examples 17-32 for details.

Scheme 3: The functional output pins are distributed in a mixed manner in circles and rows. See Examples 33-67 for details.

Embodiment 2: Single base island/multi-turn function output pin/single chip

Referring to Fig. 2, the base island has a single, and the functional output pin of the outer ring of a single base island has multiple turns; there is a single chip on a single base island.

Embodiment 3: Single base island/single-turn function output pin/multi-chip

The base island has a single base, the functional output pin of the outer circle of the single base island has a single circle, there are multiple chips on the single base island, and the arrangement of the multiple chips on the single base island is arranged or/and stacked.

Embodiment 4: Single base island/multi-turn function output pin/multi-chip

Referring to Fig. 3, the base island has a single, and the function output pin of the outer ring of a single base island has multiple turns; there are multiple chips on the single base island, and the arrangement of the multiple chips on the single base island is arranged or/and stack.

Embodiment 5: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, the function output pins of the outer rings of the multiple base islands have a single turn, and each of the multiple base islands has a single chip.

Embodiment 6: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, each of the multiple base islands has a single function output pin on the outer ring, and each of the multiple base islands has a single chip.

Embodiment 7: multi-base island/multi-turn function output pin/multi-chip

There are multiple base islands, each of the multiple base islands has multiple turns of function output pins on the outer ring, and each of the multiple base islands has a single chip.

Embodiment 8: multi-base island/single and multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pin of the outer ring of each base island in the multiple base islands has a single turn or multiple turns, and each base island in the multiple base islands has a single chip.

Embodiment 9: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single circle. Each of the multiple base islands has multiple chips, and the arrangement of multiple chips on each base island There are permutations or/and stacks.

Embodiment 10: Multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, and the function output pin of each base island outer ring in multiple base islands has a single circle. Islands can be arranged in rows or/and stacked.

Embodiment 11: Multi-base island/multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pins of the outer circle of each base island in the multiple base islands have multiple turns, and there are multiple chips on each base island among the multiple base islands, and the multiple chips have Islands can be arranged in rows or/and stacked.

Embodiment 12: multi-base island/single and multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pins of the outer circle of each base island in the multiple base islands have a single circle or multiple circles. Each base island in the multiple base islands has multiple chips, and multiple chips The arrangement on each base island includes permutation or/and stacking.

Embodiment 13: multi-base island/single-turn function output pin/single and multi-chip

Referring to Figure 4, there are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single circle. Some of the multiple base islands have a single chip on the base island, and some base islands have multiple chips. Chips, multiple chips are arranged or/and stacked on the base island.

Embodiment 14: multi-base island/single-turn function output pin/single and multi-chip

Referring to Fig. 5, there are multiple base islands, and the function output pin of each base island outer ring in multiple base islands has a single circle, and some base islands have a single chip on the multiple base islands, and some base islands have a single chip. There are multiple chips on the island, and the multiple chips are arranged or/and stacked on the base island.

Embodiment 15: multi-base island/multi-turn function output pin/single and multi-chip

Referring to Fig. 6, there are multiple base islands, and the function output pins of each base island outer ring in multiple base islands have multiple turns, some of the multiple base islands have a single chip on the base island, and some base islands have There are multiple chips on the island, and the multiple chips are arranged or/and stacked on the base island.

Embodiment 16: multi-base island/single and multi-turn function output pin/single and multi-chip

Referring to Fig. 7, there are multiple base islands, and the functional output pins of the outer circle of each base island in the multiple base islands have a single turn or multiple turns, and some of the multiple base islands have a single chip on the base island , some base islands have multiple chips, and the arrangement of multiple chips on the base island is arranged or/and stacked.

Embodiment 17: Single base island/single row of functional output pins/single chip

Referring to Figures 8-9, the base island has a single base, and the functional output pins on the outside of the single base island have a single row, and the single row of functional output pins is arranged on one side of the single base island (Figure 8) or multiple sides (Figure 9) , there is a single chip on a single base island.

Embodiment 18: Single base island/multiple rows of functional output pins/single chip

Referring to FIG. 10 , the base island has a single base, and there are multiple rows of functional output pins on the outside of the single base island, and the multiple rows of functional output pins are arranged on one or more sides of the single base island; there is a single chip on the single base island.

Embodiment 19: Single base island/single row of function output pins/multi-chip

Referring to Figures 11-12, the base island has a single base, and the functional output pins on the outside of the single base island have a single row, and the single row of functional output pins is arranged on one side of the single base island (Figure 11) or multiple sides (Figure 12) , there are multiple chips on a single base island. Multiple chips can be arranged or/and stacked on a single substrate island.

Embodiment 20: Single base island/multiple rows of functional output pins/multiple chips

Referring to FIG. 13 , the base island has a single base, and there are multiple rows of functional output pins on the outside of the single base island, and the multiple rows of functional output pins are arranged on one or more sides of the single base island; there are multiple chips on the single base island. Multiple chips can be arranged or/and stacked on a single substrate island.

Example 21: Multiple base islands/single row of function output pins/multiple chips

There are multiple base islands, and the functional output pins outside the multiple base islands have a single row, and the single row of functional output pins is arranged on one or more sides of the multiple base islands, and each base island in the multiple base islands There is a single chip.

Example 22: Multiple base islands/single row of function output pins/multiple chips

There are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row, and the single row of functional output pins is arranged on one or more sides of each base island. There is a single chip on each base island.

Embodiment 23: Multiple base islands/multiple rows of functional output pins/multiple chips

There are multiple base islands, and there are multiple rows of functional output pins on the outside of each base island among the multiple base islands, and the multiple rows of functional output pins are arranged on one or more sides of each base island; There is a single chip on each base island.

Embodiment 24: multi-base island/single and multi-row function output pins/multi-chip

There are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row or multiple rows. The single or multiple rows of functional output pins are arranged on one or more sides of each base island. side; a single chip on each of the plurality of base islands.

Example 25: Multiple base islands/single row of function output pins/multiple chips

There are multiple base islands, and the functional output pins on the outside of the multiple base islands have a single row, and the single row of functional output pins is arranged on one or more sides of the multiple base islands; each base island in the multiple base islands There are multiple chips. Multiple chips are arranged or/and stacked on each base island.

Example 26: Multi-base island/single row of function output pins/multi-chip

There are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row, and the single row of functional output pins is arranged on one or more sides of each base island. There are multiple chips on each base island. Multiple chips are arranged or/and stacked on each base island.

Embodiment 27: Multiple base islands/multiple rows of functional output pins/multiple chips

There are multiple base islands, and there are multiple rows of functional output pins on the outside of each base island among the multiple base islands, and the multiple rows of functional output pins are arranged on one or more sides of each base island; There are multiple chips on each base island. Multiple chips are arranged or/and stacked on each base island.

Embodiment 28: multi-base island/single and multi-row function output pins/multi-chip

There are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row or multiple rows. The single or multiple rows of functional output pins are arranged on one or more sides of each base island. side; each of the plurality of base islands has multiple chips. Multiple chips are arranged or/and stacked on each base island.

Embodiment 29: multi-base island/single row of function output pins/single and multi-chip

Referring to Figures 14-15, there are multiple base islands, and the functional output pins outside the multiple base islands have a single row, and the single row of functional output pins is arranged on one or more sides of the multiple base islands; multiple base islands Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangements of the multiple chips on the base island are arranged or/and stacked.

Embodiment 30: Multi-base island/single row of function output pins/single and multi-chip

Referring to Figure 16, there are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row, and the single row of functional output pins are arranged on one or more sides of each base island; multiple Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangement of the multiple chips on the base islands can be arranged or/and stacked.

Embodiment 31: Multi-base island/multi-row function output pins/single and multi-chip

Referring to Figure 17, there are multiple base islands, and there are multiple rows of functional output pins on the outside of each base island among the multiple base islands, and the multiple rows of functional output pins are arranged on one or more sides of each base island; multiple Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangement of the multiple chips on the base islands can be arranged or/and stacked.

Embodiment 32: multi-base island/single and multi-row function output pins/single and multi-chip

Referring to Figure 18, there are multiple base islands, and the functional output pins on the outside of each base island in the multiple base islands have a single row or multiple rows, and single or multiple rows of functional output pins are arranged on each base island. One side or multiple sides; some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or/and stacked.

Embodiment 33: Single base island/single circle, single row of functional output pins/single chip

The base island has a single, the functional output pins of the outer ring of the single base island have a single circle, and the outer functional output pins have a single row, and the single row of functional output pins are arranged on one or more sides of the single base island, and the single base island There is a single chip on it.

Embodiment 34: Single base island/single circle, multiple rows of functional output pins/single chip

The base island has a single one, and the functional output pins of the outer ring of the single base island have a single circle, and the outer functional output pins have multiple rows, and the multi-row functional output pins are arranged on one or more sides of the single base island, and the single base island There is a single chip on it.

Embodiment 35: Single base island/multi-turn, single row of functional output pins/single chip

The base island has a single, multi-turn functional output pins on the outer ring of the single base island, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one or more sides of the single base island. There is a single chip on it.

Embodiment 36: Single base island/multi-turn, multi-row functional output pins/single chip

The base island has a single, multi-turn functional output pins on the outer ring of the single base island, and multiple rows of functional output pins on the outside, and the multi-row functional output pins are arranged on one or more sides of the single base island. There is a single chip on it.

Embodiment 37: Single base island/single circle, single row of functional output pins/multi-chip

Referring to Figures 19-22, there is a single base island, the outer ring of the single base island has a single ring of functional output pins, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one side of the single base island or Multiple sides (one side in Figure 19, two sides in Figures 20 and 21, and three sides in Figure 22), there are multiple chips on a single base island, and the arrangement of multiple chips on the base island is arranged or/and stack.

Embodiment 38: Single-base island/single-turn, multi-row functional output pins/multi-chip

Referring to Figures 23 to 24, there is a single base island, and the functional output pins of the outer ring of the single base island have a single circle, and the outer functional output pins have multiple rows, and the multi-row functional output pins are arranged on one side of the single base island or Multiple sides (two sides in FIG. 23 and three sides in FIG. 24 ), there are multiple chips on a single base island, and the arrangement of multiple chips on the base island can be arranged or/and stacked.

Embodiment 39: Single base island/multi-turn, single row of function output pins/multi-chip

The base island has a single, multi-turn functional output pins on the outer ring of the single base island, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one or more sides of the single base island. There are multiple chips on the base island, and the arrangement of multiple chips on the base island can be arranged or/and stacked.

Example 40: Single base island/multi-turn, multi-row functional output pins/multi-chip

The base island has a single, multi-turn functional output pins on the outer ring of the single base island, and multiple rows of functional output pins on the outside, and the multi-row functional output pins are arranged on one or more sides of the single base island. There are multiple chips on the base island, and the arrangement of multiple chips on the base island can be arranged or/and stacked.

Example 41: multi-base island/single-turn, single-row function output pins/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have a single row. The single-row functional output pins are arranged on one or more sides of the base island. There is a single chip on each base island.

Example 42: Multi-base island/single-turn, multi-row functional output pins/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have multiple rows. The multi-row functional output pins are arranged on one or more sides of the base island. There is a single chip on each base island.

Example 43: multi-base island/single-turn, single-row, multi-row functional output pins/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have a single row or multiple rows. The single row and multi-row functional output pins are arranged on one side of the base island or Multi-sided, multiple base islands with a single chip on each base island.

Example 44: Multi-base island/multi-turn, single-row functional output pin/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have multiple turns, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one or more sides of the base island. There is a single chip on each base island.

Embodiment 45: Multi-base island/multi-turn, multi-row function output pin/multi-chip

There are multiple base islands, the outer ring of the base island has multiple circles of functional output pins, and the outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. There is a single chip on each base island.

Example 46: multi-base island/multi-turn, single-row, multi-row functional output pins/multi-chip

There are multiple base islands, the functional output pins on the outer ring of the base island have multiple turns, and the outer functional output pins have a single row or multiple rows. The single row and multi-row functional output pins are arranged on one side of the base island or Multi-sided, multiple base islands with a single chip on each base island.

Embodiment 47: multi-base island/single-turn, multi-turn, single-row function output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer circle of the base island have a single turn or multiple turns. The outer functional output pins have a single row, and the single row of functional output pins are arranged on one or more sides of the base island. There is a single chip on each base island in multiple base islands.

Embodiment 48: Multi-base island/single-turn, multi-turn, multi-row functional output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have a single circle or multiple circles. The outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. There is a single chip on each base island in multiple base islands.

Embodiment 49: multi-base island/single-turn, multi-turn, single-row, multi-row functional output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have a single circle or multiple circles, and the outer functional output pins have a single row or multiple rows, and the single-row and multi-row functional output pins are arranged on the base island On one or more sides of the multi-base island, there is a single chip on each base island.

Embodiment 50: multi-base island/single-turn, single-row function output pin/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have a single row. The single-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 51: Multi-base island/single circle, multi-row functional output pins/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have multiple rows. The multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 52: multi-base island/single-turn, single-row, multi-row function output pins/multi-chip

There are multiple base islands. The functional output pins on the outer ring of the base island have a single circle, and the outer functional output pins have a single row or multiple rows. The single row and multi-row functional output pins are arranged on one side of the base island or Multiple sides, multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 53: multi-base island/multi-turn, single-row functional output pin/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have multiple turns, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one or more sides of the base island. There are multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 54: multi-base island/multi-turn, multi-row function output pin/multi-chip

There are multiple base islands, the outer ring of the base island has multiple circles of functional output pins, and the outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 55: multi-base island/multi-turn, single-row, multi-row functional output pins/multi-chip

There are multiple base islands, the functional output pins on the outer ring of the base island have multiple turns, and the outer functional output pins have a single row or multiple rows. The single row and multi-row functional output pins are arranged on one side of the base island or Multiple sides, multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 56: multi-base island/single-turn, multi-turn, single-row function output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer circle of the base island have a single turn or multiple turns. The outer functional output pins have a single row, and the single row of functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in multiple base islands. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 57: multi-base island/single-turn, multi-turn, multi-row functional output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have a single circle or multiple circles. The outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in multiple base islands. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 58: multi-base island/single-turn, multi-turn, single-row, multi-row functional output pins/multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have a single circle or multiple circles, and the outer functional output pins have a single row or multiple rows, and the single-row and multi-row functional output pins are arranged on the base island On one or more sides of the multi-base island, there are multiple chips on each base island. The arrangements of multiple chips on the base island include arrangement or/and stacking.

Embodiment 59: multi-base island/single circle, single row of function output pins/single, multi-chip

Referring to Figures 25-37, there are multiple base islands. The functional output pins on the outer circle of the base island have a single circle, and the outer functional output pins have a single row. The single row of functional output pins is arranged on one side or more of the base island. On the other hand, among the multiple base islands, some base islands have a single chip, some base islands have multiple chips, and the arrangement of the multiple chips on the base islands is arranged or/and stacked.

Embodiment 60: multi-base island/single circle, multi-row function output pin/single, multi-chip

Referring to Figures 38-39, there are multiple base islands. The functional output pins on the outer circle of the base island have a single circle, and the outer functional output pins have multiple rows. The multi-row functional output pins are arranged on one side or more of the base island. On the other hand, among the multiple base islands, some base islands have a single chip, some base islands have multiple chips, and the arrangement of the multiple chips on the base islands is arranged or/and stacked.

Embodiment 61: multi-base island/single-turn, single-row, multi-row functional output pins/single, multi-chip

Referring to Figures 40-42, there are multiple base islands. The functional output pins on the outer circle of the base islands have a single circle, and the outer functional output pins have single or multiple rows. The single-row and multi-row functional output pins are arranged on One or more sides of the base island, some of the multiple base islands have a single chip, and some base islands have multiple chips, and the arrangement of multiple chips on the base island is arranged or/and stacked .

Embodiment 62: multi-base island/multi-turn, single-row function output pin/single, multi-chip

There are multiple base islands, the outer circle of the base island has multiple turns of functional output pins, and the outer functional output pins have a single row, and the single row of functional output pins is arranged on one or more sides of the base island, and multiple base islands Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangements of the multiple chips on the base island are arranged or/and stacked.

Embodiment 63: multi-base island/multi-turn, multi-row function output pin/single, multi-chip

There are multiple base islands, the outer ring of the base island has multiple circles of functional output pins, and the outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangements of the multiple chips on the base island are arranged or/and stacked.

Embodiment 64: multi-base island/multi-turn, single row, multi-row function output pin/single, multi-chip

There are multiple base islands, the functional output pins on the outer ring of the base island have multiple turns, and the outer functional output pins have a single row or multiple rows. The single row and multi-row functional output pins are arranged on one side of the base island or Multiple sides, some of the base islands have a single chip, and some of the base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or/and stacked.

Embodiment 65: multi-base island/single-turn, multi-turn, single-row function output pin/single, multi-chip

There are multiple base islands, and the functional output pins on the outer circle of the base island have a single turn or multiple turns. The outer functional output pins have a single row, and the single row of functional output pins are arranged on one or more sides of the base island. Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangement of the multiple chips on the base islands can be arranged or/and stacked.

Embodiment 66: multi-base island/single-turn, multi-turn, multi-row function output pins/single and multi-chip

There are multiple base islands, and the functional output pins on the outer ring of the base island have a single circle or multiple circles. The outer functional output pins have multiple rows, and the multiple rows of functional output pins are arranged on one or more sides of the base island. Some of the base islands have a single chip, some of the base islands have multiple chips, and the arrangement of the multiple chips on the base islands can be arranged or/and stacked.

Embodiment 67: multi-base island/single-turn, multi-turn, single-row, multi-row function output pins/single and multi-chip

Referring to Fig. 43, there are multiple base islands, and the functional output pins on the outer circle of the base island can be single-turned or multi-turned, and the outer functional output pins can be single-row or multi-row, single-row and multi-row functional output pins Arranged on one or more sides of the base island, some of the multiple base islands have a single chip, and some base islands have multiple chips, and the arrangement of the multiple chips on the base island has an arrangement or/ and stack.

Claims (74)

1. An integrated circuit or discrete component planar bump package structure, including a base island (1), a chip (2), a functional output pin (3) and a plastic package (5), the functional output pin (3) ) is distributed on the outer ring or/and outside of the base island (1), and the chip (2) is placed on the base island (1), characterized in that: The base island (1) and the functional output pin (3) outside the plastic package (5) protrude from the surface of the plastic package (5); The base island (1) has a single base island or multiple base islands; The functional output pins (3) are distributed in circles, or in rows, or mixed in circles and rows; The chip (2) has a single chip or multiple chips. 2. A planar bump package structure for integrated circuits or discrete components according to claim 1, characterized in that: the functional output pin (3) and the base island (1) sequentially include metal from the inside to the outside Layers (3.1, 1.1), metal substrate layers (3.3, 1.3) and metal layers (3.5, 1.5), the functional output pin (3) protruding from the plastic package (5) and the bottom surface of the base island (1) are covered The metal layer (3.5, 1.5) is plated. 3. A planar bump package structure for integrated circuits or discrete components according to claim 1, characterized in that: the functional output pin (3) and the base island (1) sequentially include metal Layers (3.1, 1.1), metal substrate layers (3.3, 1.3) and metal layers (3.5, 1.5), the surfaces of the functional output feet (3) and the base island (1) protruding from the plastic package (5) are covered with metal Layer (3.5, 1.5) coating. 4. A planar bump package structure for integrated circuits or discrete components according to claim 1, characterized in that: the functional output pin (3) and the base island (1) sequentially include metal Layer (3.1, 1.1), activation layer (3.2, 1.2), metal substrate layer (3.3, 1.3), activation layer (3.4, 1.4) and metal layer (3.5, 1.5), protruding from the function of the plastic package (5) The bottom end surfaces of the output pin (3) and the base island (1) are plated by the outer active layer (3.4, 1.4) and the outer metal layer (3.5, 1.5). 5. A planar bump package structure for integrated circuits or discrete components according to claim 1, characterized in that: said functional output pin (3) and base island (1) sequentially include metal Layer (3.1, 1.1), activation layer (3.2, 1.2), metal substrate layer (3.3, 1.3), activation layer (3.4, 1.4) and metal layer (3.5, 1.5), protruding from the function of the plastic package (5) The surfaces of the output pin (3) and the base island (1) are covered by the outer activation layer (3.4, 1.4) and the outer metal layer (3.5, 1.5). 6. An integrated circuit or discrete component planar bump package structure according to any one of claims 1 to 5, characterized in that: the functional output pins (3) are distributed on the base island (1) the outer ring. 7. According to one of claims 1 to 5, an integrated circuit or discrete element planar bump package structure, characterized in that: said functional output pins (3) are distributed on the base island (1) outside. 8. According to one of claims 1 to 5, an integrated circuit or discrete element planar bump package structure, characterized in that: said functional output pins (3) are distributed on the base island (1) The outer ring and outer side. 9. An integrated circuit or discrete component planar encircled bump package structure according to claim 6, characterized in that: the base island has a single, and the functional output pins of the outer ring of a single base island have multiple turns; There is a single chip on a single substrate island. 10. An integrated circuit or discrete element planar bump package structure according to claim 6, characterized in that: the base island has a single, and the functional output pin of the outer circle of a single base island has a single circle, There are multiple chips on the single base island, and the multiple chips are arranged or/and stacked on the single base island. 11. An integrated circuit or discrete component planar encircled bump package structure according to claim 6, characterized in that: the base island has a single, and the functional output pin of the outer ring of a single base island has multiple turns; There are multiple chips on the single base island, and the multiple chips are arranged or/and stacked on the single base island. 12. A planar encircled bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single In the circle, there is a single chip on each of the plurality of base islands. 13. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer circle of each base island among the multiple base islands The function output pin has a single turn, and each of the multiple base islands has a single chip. 14. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer circle of each base island among the multiple base islands The function output pin has multiple turns, and each of the multiple base islands has a single chip. 15. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer ring of each base island among the multiple base islands The function output pin has single-turn or multi-turn, and there is a single chip on each of the multiple base islands. 16. A planar encircled bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single In the circle, there are multiple chips on each of the multiple base islands, and the arrangement of the multiple chips on each base island is arranged or/and stacked. 17. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer circle of each base island among the multiple base islands The functional output pin has a single turn, and each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island can be arranged or/and stacked. 18. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer ring of each base island among the multiple base islands The functional output pin has multiple turns, each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island is arranged or/and stacked. 19. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer ring of each base island among the multiple base islands The functional output pin has a single turn or multiple turns, and each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island can be arranged or/and stacked. 20. A planar encircled bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single In the circle, some of the base islands have a single chip, some of the base islands have multiple chips, and the multiple chips are arranged or/and stacked on the base island. 21. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer ring of each base island among the multiple base islands The functional output pin has a single turn, some of the base islands have a single chip, and some of the base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or/and stacked. 22. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer ring of each base island among the multiple base islands The function output pin has multiple turns, some of the multiple base islands have a single chip, and some of the base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or/and stacked. 23. A planar surrounding bump package structure for integrated circuits or discrete components according to claim 6, characterized in that: there are multiple base islands, and the outer circle of each base island among the multiple base islands The function output pin has single-turn and multi-turn. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of multiple chips on the base island is arranged or / and stack. 24. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: the base island has a single, and the functional output pins outside the single base island have a single row, a single row The functional output pins are arranged on multiple sides of the single-base island, and there is a single chip on the single-base island. 25. A planar bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: the base island has a single, and the functional output pins outside the single base island have multiple rows, and multiple rows The functional output pins are arranged on one or more sides of the single-base island; there is a single chip on the single-base island. 26. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: the base island has a single, and the functional output pins outside the single base island have a single row, a single row of function The output pins are arranged on one or more sides of the single-base island, and there are multiple chips on the single-base island, and the arrangements of the multiple chips on the single-base island can be arranged or/and stacked. 27. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: said base island has a single base island, and there are multiple rows of functional output pins outside the single base island, and multiple rows of functional output pins The output pins are arranged on one or more sides of the single-base island; there are multiple chips on the single-base island, and the arrangement of multiple chips on the single-base island can be arranged or/and stacked. 28. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and there is a single row of functional output pins outside the multiple base islands. A single row of functional output pins is arranged on one or more sides of multiple base islands, and each of the multiple base islands has a single chip. 29. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There is a single row of pins, and the single-row functional output pins are arranged on one or more sides of each base island, and each base island has a single chip in the multiple base islands. 30. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are multiple rows of pins, and the multiple rows of functional output pins are arranged on one or more sides of each base island; each of the multiple base islands has a single chip. 31. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are single or multiple rows of pins, and the single or multiple rows of functional output pins are arranged on one or more sides of each base island; there is a single chip on each base island among multiple base islands. 32. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and there is a single row of functional output pins outside the multiple base islands. The single-row functional output pins are arranged on one or more sides of multiple base islands; each of the multiple base islands has multiple chips, and the arrangement of multiple chips on each base island has an arrangement or/and stack. 33. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There is a single row of pins, and the single-row functional output pins are arranged on one or more sides of each base island. There are multiple chips on each base island among multiple base islands. The arrangement of multiple chips on each base island There are permutations or/and stacks. 34. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are multiple rows of pins, and multiple rows of functional output pins are arranged on one or more sides of each base island; there are multiple chips on each base island in multiple base islands, and the arrangement of multiple chips on each base island There are permutations or/and stacks. 35. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are single or multiple rows of pins, and the single or multiple rows of functional output pins are arranged on one or more sides of each base island; there are multiple chips on each base island among multiple base islands, and multiple chips are placed on each base island. The arrangement on each base island includes arrangement or/and stacking. 36. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and there is a single row of functional output pins outside the multiple base islands. The single-row functional output pins are arranged on one or more sides of multiple base islands; some of the base islands have a single chip, and some base islands have multiple chips, and multiple chips are on the base island Arrangement methods include permutation and/or stacking. 37. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that there are multiple base islands, and the functional output of each base island in the multiple base islands There is a single row of pins, and the single-row functional output pins are arranged on one or more sides of each base island; among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips and multiple chips. The arrangement of the chips on the base island includes arrangement or/and stacking. 38. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are multiple rows of pins, and the multi-row functional output pins are arranged on one or more sides of each base island; among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips and multiple chips. The arrangement of the chips on the base island includes arrangement or/and stacking. 39. A planar arrangement bump package structure for integrated circuits or discrete components according to claim 7, characterized in that: there are multiple base islands, and the function output outside each of the multiple base islands There are single or multiple rows of pins, and single or multiple rows of functional output pins are arranged on one or more sides of each base island; some of the base islands have a single chip, and some base islands There are multiple chips, and the multiple chips are arranged or/and stacked on the base island. 40. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pin of the outer circle of the single base island has a single circle, and the outer There is a single row of functional output pins, and the single row of functional output pins is arranged on one or more sides of the single-base island, and there is a single chip on the single-base island. 41. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pin of the outer ring of the single base island has a single ring, and the outer There are multiple rows of functional output pins, and the multiple rows of functional output pins are arranged on one or more sides of the single-base island, and there is a single chip on the single-base island. 42. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pins of the outer ring of the single base island have multiple turns, and the outer There is a single row of functional output pins, and the single row of functional output pins is arranged on one or more sides of the single-base island, and there is a single chip on the single-base island. 43. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pins of the outer ring of the single base island have multiple turns, and the outer There are multiple rows of functional output pins, and the multiple rows of functional output pins are arranged on one or more sides of the single-base island, and there is a single chip on the single-base island. 44. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pin of the outer circle of the single base island has a single circle, and the outer There is a single row of functional output pins, and the single-row functional output pins are arranged on one or more sides of the single-base island. There are multiple chips on the single-base island, and the arrangement of multiple chips on the base island can be arranged or/and stack. 45. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pin of the outer ring of the single base island has a single ring, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the single-base island. There are multiple chips on the single-base island, and the arrangement of multiple chips on the base island is arranged or/and stack. 46. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pins of the outer ring of the single base island have multiple turns, and the outer There is a single row of functional output pins, and the single-row functional output pins are arranged on one or more sides of the single-base island. There are multiple chips on the single-base island, and the arrangement of multiple chips on the base island can be arranged or/and stack. 47. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: the base island has a single, and the functional output pins of the outer ring of the single base island have multiple turns, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the single-base island. There are multiple chips on the single-base island, and the arrangement of multiple chips on the base island is arranged or/and stack. 48. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands have a single circle, and the outer There is a single row of functional output pins, and the single row of functional output pins is arranged on one or more sides of the base island, and there is a single chip on each base island in the multi-base island. 49. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have a single circle, and the outer There are multiple rows of functional output pins, and the multiple rows of functional output pins are arranged on one or more sides of the base island, and each base island in the multi-base island has a single chip. 50. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands have a single circle, and the outer There are single row or multiple rows of functional output pins. The single row and multiple rows of functional output pins are arranged on one or more sides of the base island, and there is a single chip on each base island in the multiple base islands. 51. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that there are multiple base islands, and the functional output pins on the outer ring of the base islands have multiple turns, and the outer There is a single row of functional output pins, and the single row of functional output pins is arranged on one or more sides of the base island, and there is a single chip on each base island in the multi-base island. 52. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are multiple rows of functional output pins, and the multiple rows of functional output pins are arranged on one or more sides of the base island, and each base island in the multi-base island has a single chip. 53. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are single row or multiple rows of functional output pins. The single row and multiple rows of functional output pins are arranged on one or more sides of the base island, and there is a single chip on each base island in the multiple base islands. 54. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have a single row, and the single-row functional output pins are arranged on one or more sides of the base island, and each base island in the multi-base island has a single chip. 55. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have multiple rows, and the multi-row functional output pins are arranged on one or more sides of the base island, and each base island in the multi-base island has a single chip. 56. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer ring of the base islands include single circles and Multi-turn, the outer functional output pins have a single row or multiple rows. The single-row and multi-row functional output pins are arranged on one or more sides of the base island, and each base island in the multi-base island has a single chip. 57. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands have a single circle, and the outer There is a single row of functional output pins, and the single-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island, and the arrangement of multiple chips on the base island is arranged. or/and stack. 58. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have a single circle, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island, and the arrangement of multiple chips on the base island is arranged or/and stack. 59. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have a single circle, and the outer There are single row and multiple rows of functional output pins. The single row and multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island. Islands can be arranged in rows or/and stacked. 60. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There is a single row of functional output pins, and the single-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island, and the arrangement of multiple chips on the base island is arranged. or/and stack. 61. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island, and the arrangement of multiple chips on the base island is arranged or/and stack. 62. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are single row and multiple rows of functional output pins. The single row and multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island. Islands can be arranged in rows or/and stacked. 63. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer ring of the base islands include single circles and Multi-turn, the outer functional output pins have a single row, and the single-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island, and multiple chips are on the base island. Arrangement methods include permutation or/and stacking. 64. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands include single circles and For multi-turn, the outer functional output pins have multiple rows, and the multi-row functional output pins are arranged on the base island in an array or/and stacked manner. 65. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have a single row or multiple rows. The single-row and multi-row functional output pins are arranged on one or more sides of the base island. There are multiple chips on each base island in the multi-base island. The arrangement of chips on the base island can be arranged or/and stacked. 66. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands have a single circle, and the outer The functional output pins are arranged in a single row, and the single-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of the chips on the base island includes arrangement or/and stacking. 67. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands have a single circle, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of chips on the base island can be arranged or/and stacked. 68. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer ring of the base islands have a single ring, and the outer There are single-row and multi-row functional output pins. The single-row and multi-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands There are a plurality of chips on the base island, and the arrangements of the plurality of chips on the base island are arranged or/and stacked. 69. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There is a single row of functional output pins, and the single-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of chips on the base island can be arranged or/and stacked. 70. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are multiple rows of functional output pins, and the multi-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of chips on the base island can be arranged or/and stacked. 71. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands have multiple turns, and the outer There are single-row and multi-row functional output pins. The single-row and multi-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands There are a plurality of chips on the base island, and the arrangements of the plurality of chips on the base island are arranged or/and stacked. 72. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have a single row, and the single-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. chips, and multiple chips are arranged or/and stacked on the base island. 73. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins on the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have multiple rows, and the multi-row functional output pins are arranged on one or more sides of the base island. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. chips, and multiple chips are arranged or/and stacked on the base island. 74. A planar bump package structure for integrated circuits or discrete components according to claim 8, characterized in that: there are multiple base islands, and the functional output pins of the outer circle of the base islands include single circles and Multi-turn, the outer functional output pins have a single row or multiple rows. The single-row and multi-row functional output pins are arranged on one or more sides of the base island. Some of the multiple base islands have a single chip on the base island. Some base islands have multiple chips, and the multiple chips are arranged or/and stacked on the base island.

Images