CN1722078A - Memory device and associated memory module, memory controller and method - Google Patents

Abstract

A memory module includes a plurality of memory devices. A method of controlling a memory module comprising providing a mode register set command from a memory controller to each integrated circuit memory device over a command/address bus during a mode register set operation. An inhibit signal is provided via a signal line from the memory controller to a first one of the integrated circuit memory devices to inhibit execution of the mode register set instruction of the first integrated circuit memory device. An enable signal is provided via a signal line from the memory controller to a second one of the integrated circuit memory devices to enable execution of the mode register set instruction of the second integrated circuit memory device. Also, during a mode register set operation, the disable signal is not provided to the second integrated circuit memory device, and the enable signal is not provided to the first integrated circuit memory device. Related systems, devices, and additional methods are also discussed.

Description

Memory device and associated memory module, memory controller and method

Cross References to Related Applications

This application is a continuation-in-part of, and claims priority to, U.S. Patent Application No. 10/199,857, filed July 19, 2002, and claiming priority from said U.S. Patent Application, filed July 20, 2001, with Application No. 10-2001- Priority of Korean application 0043789. This application also claims the priority of Korean Application No. 10-2004-0032500 filed on May 8, 2004. Published US Patent Application 10/199,857, Korean Application 10-2001-0043789, and Korean Application 10-2004-0032500 are hereby incorporated by reference in their entirety.

technical field

The present invention relates to the field of electronic instruments, in particular to electronic memory devices, memory modules, memory controllers, and related methods

Background technique

In a digital memory system, a memory controller 10 may control the operation of a memory module 20 comprising a plurality of memory devices 30, respectively identified as M1-M9. More specifically, each memory device 30 may be an integrated circuit dynamic random access memory device.

Data signals DATA1-DATA9 may be communicated between memory controller 10 and individual memory devices 30 using separate data signal bus lines. During a read operation, data signals DATA1-DATA9 can be simultaneously read from the memory devices M1-M9 into the memory controller 10 via separate data bus lines, and during a write operation, data signals DATA1-DATA9 can be simultaneously transferred from the memory devices M1-M9 to the memory controller 10. The controller writes to memory devices M1-M9. In addition, separate lines for the data strobe signals DQS1-DQS9 and separate lines for the data mask signals DM1-DM9 are provided between the memory controller 10 and each of the memory devices M1-M9. Accordingly, the propagation delays of data signals DATA1-DATA9, data strobe signals DQS1-DQS9, and data masks DM1-DM9 between memory controller 10 and each of memory devices M1-M9 are approximately the same. The arrangement of Figure 1 with a separate data bus between the memory controller 10 and each of the memory devices M1-M8 may be said to provide a point-to-point connection.

Instead, the same control/address/clock bus 12 may couple the control/address signal CA and the system clock signal CK from the memory controller 10 to each of the memory devices M1-M9. Therefore, the length of the clock signal CK transmission line is different for each memory device M1-M9, so that the clock signal CK propagation delay is different for each memory device M1-M9. If the memory devices M1-M9 are evenly spaced along the control/address/clock bus 12, the clock signal CK may experience an incremental propagation delay T (also known as a phase difference or shift delay) for each memory device M1-M9 in the module. Mutually). Arbitrarily assigning a propagation delay of 0 to the first memory device M1, for example, may generate a propagation delay T of the clock signal CK in the second memory device M2, may generate a propagation delay 2T in the third memory device M3, may generate a propagation delay in the fourth memory device M M4 produces a propagation delay of 3T, possibly in the fifth memory device M5 of 4T, possibly in the sixth memory device M6 of 5T, possibly in the seventh memory device M7 of 6T, possibly in the eighth memory device M8 A propagation delay of 7T is generated, and a propagation delay of 8T may be generated at the ninth memory device M9. The arrangement of FIG. 1 with a clock signal CK provided to each memory device M1-M9 is referred to as providing a fly-by clock.

The read and write data signals DATA1-DATA9 provided over respective point-to-point data buses may be synchronized with the flying system clock signal CK provided to each memory device over the same system clock signal line. But at relatively high operating speeds, it is difficult to synchronize the transmission of the data signals DATA1-DATA9 over respective point-to-point data buses, where different memory devices M1-M9 with different propagation delays are supplied with the system clock signal CK.

Figure 2 shows a memory module 20 comprising nine memory devices 30, respectively identified as M1-M9. As shown in the figure, each memory device 30 includes eight data pins PDQ1-PDQ8, a data mask pin PDM, and a data strobe pin PDQS, which are respectively connected to the memory controller. As shown, data signals DQ1-8 (that is, DATA1) are provided to/from the data pins PDQ1-PDQ8 of the memory device M1; data signals DQ9-DQ16 (that is, DATA2) are provided to/from the memory device M2 on the data pins PDQ1-PDQ8; data signals DQ17-DQ24 (that is, DATA3) are provided to/from the data pins PDQ1-PDQ8 of the memory device M3; data signals DQ25-DQ32 (that is, DATA4) are provided to/ From data pins PDQ1-PDQ8 of memory device M4; data signals DQ33-DQ40 (ie, DATA5) are provided to/from data pins PDQ1-PDQ8 of memory device M5; data signals DQ41-DQ48 (ie, DATA6) Provided to/from the data pins PDQ1-PDQ8 of the memory device M6; data signals DQ49-DQ56 (that is, DATA7) are provided to/from the data pins PDQ1-PDQ8 of the memory device M7; data signals DQ57-DQ64 ( ie DATA8) is provided to/from data pins PDQ1-PDQ8 of memory device M8; and data signals DQ65-DQ72 (ie DATA9) are provided to/from data pins PDQ1-PDQ8 of memory device M9. Through separate data mask lines, data mask signals DM1-DM9 are provided to the respective data mask pins PDM of each memory device M1-M9, and through separate data strobe lines, data strobe signals DQS1-DQS9 are provided to A respective data strobe pin PDQS for each memory device M1-M9.

As used herein, the term pin is defined to include any input or output structure of an integrated circuit memory device that provides electrical communication with other devices, a substrate, and/or a circuit board. For example, the term pin can include: dual in-line package (DIP), single in-line package (SIP), pin grid array (PGA), quad small outline package (QSOP), etc. wires; flip-chip solder bumps of a flip-chip, ball grid array, etc.; wire bonding; bonding pads; etc. In addition, each memory device M1 - M9 includes a plurality of clock/command/address pins PCA coupled to the same clock/command/address bus 12 . The system clock signal CK and the command/address signal CA are provided via the clock/command/address bus 12 to the clock/command/address pins of the memory devices M1-M9. Address signals communicated over clock/command/address bus 12 define memory locations of memory devices M1-M9 from which data signals DATA1-DATA9 are to be written or read. More specifically, address signals may define bank addresses and row/column addresses. A memory device, for example, may include four banks of memory cells, and each bank may be operated independently with selected row and column addresses.

Command signals communicated over clock/command/address bus 12 define the operations performed by memory devices M1-M9. The command signal can define commands, such as row valid command (ACTIVE), read command (READ), write command (WRITE), refresh command (REF), power down command (PWDN), mode register setting command (MRS), and so on. The command pins may include a clock enable pin, a chip select pin, a row address strobe pin, a column address strobe pin, and a write enable pin. 3A shows a schematic diagram of the pins of an integrated circuit DRAM device, and FIG. 3B is a diagram depicting the function of the pins of the memory device of FIG. 3A.

Figure 4 shows a block diagram of the functional blocks of a memory device. As shown, the memory device 30 includes an instruction decoder 34, an address buffer 35, an internal clock generator 36, a data I/O buffer 37, a row decoder 32, a column decoder 33, a memory cell array 31, and a read output amplifier 38. As shown in the figure, the command signal CMD of the clock/command/address signal CA is provided to the command decoder 34, the address signal ADD of the clock/command/address signal CA is provided to the address buffer 35, and the clock/command/address signal The system clock signal CK of CA is supplied to the internal clock generator 36 . Internal clock generator 36 generates internal clock signal iCLK in response to system clock signal CK.

Therefore, the command decoder 34 decodes the command signal CMD to determine that a specific operation (such as a read operation, a write operation, or a mode register setting operation) is to be performed. During a mode register set operation, a value is written to the mode register to define the mode of operation of the memory device. During a write operation, the data signal DATA from the memory controller is received into the data I/O buffer 37 and written as iDATA to the location of the memory cell array 31 defined by the address signal ADD received from the memory controller middle. During a read operation, iDATA from the location of the memory cell array defined by address signal ADD received from the memory controller is retrieved by data I/O buffer 37 and provided to the memory controller as data signal DATA. As shown in FIG. 4 , the data I/O buffer 37 operates in response to the iCLK signal generated by the internal clock generator 36 .

FIG. 5 shows a timing diagram of a read operation of a memory module 20 comprising a plurality of memory devices 30 , wherein the read operation is initiated in response to a read command READ received via the clock/command/address data bus 12 . Due to the different propagation delays along the clock/instruction/address bus 12, the system clock signal CK shifts in phase in each of the memory devices M1-M9. In FIG. 5, signal CK1 is the system clock signal CK received by memory device M1, signal CK5 is the system clock signal CK received by memory device M5, and signal CK9 is the system clock signal CK received by memory device M9. The internal clock signal iCLK5 of the memory device M5 is thus delayed by an interval of 4T relative to the internal clock signal iCLK1 of the memory device M1, and the internal clock signal iCLK9 of the memory device M9 is delayed by an interval of 4T relative to the internal clock signal iCLK5 of the memory device M5. Because the internal clock signals are not synchronized, and because the data I/O buffers of the memory devices operate in response to the respective internal clock signals, the data signals DATA1-DATA9 originate from the respective memory devices at different times that generate data skew. As shown in FIG. 5, the data signal DATA9 from the memory device M9 is thus delayed by an interval of 4T with respect to the data signal DATA5 from the memory device M5, and the data signal DATA5 from the memory device M5 is delayed with respect to the data signal DATA1 from the memory device M1. is delayed by 4T intervals. During write operations, data skew can limit the operating speed of the memory module.

FIG. 6 is a timing diagram illustrating a write operation of a memory module 20 including a plurality of memory devices 30 initiated in response to a write command WRITE received via the clock/command/address data bus 12 . Due to the different propagation delays along the clock/instruction/address bus 12, the system clock signal CK shifts in phase in each of the memory devices M1-M9. In FIG. 6, signal CK1 is the system clock signal CK received by memory device M1, signal CK5 is the system clock signal CK received by memory device M5, and signal CK9 is the system clock signal CK received by memory device M9. The internal clock signal iCLK5 of the memory device M5 is thus delayed by the 4T interval relative to the internal clock signal iCLK1 of the memory device M1, and the internal clock signal iCLK9 of the memory device M9 is delayed by the 4T interval relative to the internal clock signal iCLK5 of the memory device M5. Because the internal clock signals are not synchronized, and because the data I/O buffers of the memory devices operate in response to the respective internal clock signals, while the external data signals DATA1-DATA9 will be provided by the memory controller, but at different times creating data skew, The internal data signals iDATA1-iDATA9 will be generated by the respective data input/output buffers. As shown in FIG. 6, the internal data signal iDATA9 of the memory device M9 is thus delayed by an interval of 4T with respect to the internal data signal iDATA5 of the memory device M5, and the internal data signal iDATA5 of the memory device M5 is delayed with respect to the internal data signal iDATA1 of the memory device M1. is delayed by 4T intervals. During write operations, data skew can limit the operating speed of the memory module.

Contents of the invention

According to an embodiment of the present invention, a memory system may include a command/address bus having a plurality of command/address lines, first and second integrated circuit memory devices, and a memory controller. The first integrated circuit memory device may include a plurality of first command/address pins coupled to command/address lines of the command/address bus, a first mode register configured to store information defining operating characteristics of the first memory device, and a first instruction decoder. The instruction decoder may be configured to receive a mode register set instruction responsive to an enable signal received on a first predetermined pin of the first integrated circuit memory device, and to reject a disable signal responsive to receipt of the first predetermined pin. mode register set instruction. Accordingly, when an enable signal is received on a first predetermined pin during a mode register setting operation, information of a mode register setting instruction may be stored into the first mode register.

Similarly, the second integrated circuit memory device may include a plurality of second command/address pins coupled to the command/address lines of the command/address bus, the second mode register being configured to store information, and a second instruction decoder. The second command decoder may be configured to receive a mode register set command responsive to an enable signal received at a second predetermined pin of the second integrated circuit memory device, and to reject a disable signal responsive to a second predetermined pin of the second integrated circuit memory device. mode register set instruction. Accordingly, during the mode register setting operation, when the second predetermined pin receives the enable signal, information of the mode register setting instruction may be stored into the second mode register.

The memory controller may be coupled to the command/address bus, wherein during the first mode register set operation, the memory controller is configured to communicate the first mode register set command to the first and second integrated circuit memories via the command/address bus multiple first and second command/address pins of the device. The memory controller may be further configured to deliver a first enable signal to a first predetermined pin of the first integrated circuit memory device and, during the first mode register set operation, to deliver a first disable signal to the second integrated circuit memory device. In the second predetermined pin of the circuit memory device.

According to a further embodiment of the present invention, a method of controlling a memory module including a plurality of memory devices coupled to a memory controller through the same command/address bus is provided. More particularly, during a mode register set operation, a mode register set command is provided from the memory controller to each integrated circuit memory device via the command/address bus. During a mode register set operation, an inhibit signal may be provided from the memory controller to a first one of the integrated circuit memory devices via a signal line between the memory controller and the first integrated circuit memory device, thereby inhibiting the first integrated circuit A mode register of the memory device sets execution of the instruction. During a mode register set operation, an enable signal may be provided from the memory controller to a second of one of the integrated circuit memory devices via a signal line between the memory controller and the second integrated circuit memory device, thereby enabling the second Execution of a mode register setting instruction of an integrated circuit memory device. Also, the disable signal is not provided to the second integrated circuit memory device during the mode register set operation, and the enable signal is not provided to the first integrated circuit memory device during the mode register set operation. According to yet another embodiment of the present invention, an integrated circuit memory device may include a memory cell array, a mode register, an instruction decoder, and a data input/output buffer. The mode register may be configured to store information defining operating characteristics of the memory device. The instruction decoder may be configured to receive a select mode register set instruction responsive to an enable signal received on a predetermined pin of the integrated circuit memory device. During a select mode register set operation, the command decoder is further configured to reject a select mode register set command responsive to an inhibit signal received on a predetermined pin of the integrated circuit memory device. Accordingly, when an enable signal is received by a predetermined pin during a selection mode register setting operation, information of the selection mode register setting instruction may be stored into the mode register. According to the operating characteristics defined by the information stored in the mode register, during a write operation, the data input/output buffer can be configured to control the writing of data into the memory cell array, and during a read operation, the data input/output buffer can be configured to Controls the reading of data from the array of memory cells.

According to yet another embodiment of the present invention, a method of operating an integrated circuit memory device may include, during a first select mode register set operation, receiving a command with a first logic value received with a predetermined pin of the integrated circuit memory device. and a signal-responsive first selected mode register set command such that information corresponding to the first selected mode register set command is stored in the mode register. During a second selection mode register set operation, the second selection mode register set instruction is rejected in response to an inhibit signal having a second logic value received at a predetermined pin of the integrated circuit memory device such that the second selection mode register The information corresponding to the set command is not stored in the mode register. Additionally, the first and second logical values may be opposite logical values. Writing data to the memory cell array of the integrated circuit memory device may be controlled during a write operation and/or reading data from the memory cell array may be controlled during a read operation according to operating characteristics defined by information stored in the mode register.

According to further embodiments of the present invention, a method of operating a memory module including a plurality of integrated circuit memory devices is provided. Multiple memory devices may be coupled to the memory controller via the same command/address bus, and multiple memory devices may be separately coupled to the memory controller via respective data input/output buses. More particularly, using a first data input/output bus coupled between the memory controller and the first memory device, a mode register of a first one of the memory devices may be set to define operating characteristics of the first memory device. Using a second data input/output bus coupled between the memory controller and the second memory device, a mode register of a second one of the memory devices can be set to define operating characteristics of the second memory device. Furthermore, via the first data input/output bus, a first data signal may be written into the memory cell array of the first memory device, and via the second data input/output bus, a second data signal may be written into the second memory device array of memory cells.

According to still further embodiments of the present invention, an integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a mode register. During a data write operation, a plurality of data input/output pins may be configured to receive data from the memory controller and be written to the memory cell array, and during a data read operation, the data input/output pins may be further configured to Configured to provide data from the array of memory cells to the memory controller. The mode register can be configured to store information defining operating characteristics of the memory device, and utilizes a data input/output bus to configure the mode register.

According to further embodiments of the present invention, a method of operating a memory module comprising a plurality of memory devices coupled to a memory controller through the same command/address bus is provided. More particularly, during a mode register set operation, a mode register set command is received from the memory controller of each integrated circuit memory device via the command/address bus. receiving an inhibit signal from a memory controller of a first one of the integrated circuit memory devices via a signal line between the memory controller and the first integrated circuit memory device during a mode register set operation, thereby disabling the first integrated circuit memory device The mode register sets the execution of the instruction. receiving an enable signal from a memory controller of a second one of the integrated circuit memory devices via a signal line between the memory controller and the second integrated circuit memory device during a mode register set operation, thereby enabling the second integrated circuit A mode register of the memory device sets execution of the instruction. Furthermore, the disable signal will not be received by the second integrated circuit memory device during the mode register set operation, and the enable signal will not be received by the first integrated circuit memory device during the mode register set operation.

Description of drawings

1 is a block diagram illustrating a conventional memory system including a memory module and a memory controller;

2 is a block diagram illustrating a memory device of a conventional memory module;

3A is a schematic diagram showing a pin configuration of a conventional memory device;

Figure 3B is a table defining the pin labels of the conventional memory device of Figure 3A;

4 is a block diagram illustrating a conventional memory device;

5 is a timing diagram illustrating a read operation of a conventional memory system;

6 is a timing diagram illustrating a write operation of a conventional memory system;

7 is a block diagram illustrating a memory system including a memory module and a memory controller according to an embodiment of the present invention;

8A is a block diagram illustrating a memory device according to an embodiment of the present invention;

8B is a table showing a mode register setting instruction according to an embodiment of the present invention;

9A is a block diagram illustrating an internal clock signal control unit according to an embodiment of the present invention;

FIG. 9B is a table illustrating a mode register setting instruction for internal clock signal timing adjustment according to an embodiment of the present invention;

10 is a timing diagram illustrating the timing of internal clock signals during a read operation according to an embodiment of the present invention;

11 is a timing diagram illustrating the timing of internal clock signals during a write operation according to an embodiment of the present invention;

12 is a block diagram illustrating a coupled mode register setting instruction and a mode register setting enable/disable signal according to an embodiment of the present invention;

13 is a timing diagram illustrating a mode register setting operation performed using dedicated lines and pins of the mode register setting enable/disable signal according to an embodiment of the present invention;

14 is a timing diagram illustrating data strobe and internal clock signal operations according to an embodiment of the present invention;

15 is a timing diagram illustrating a mode register setting operation performed using data mask lines and pins of the mode register setting enable/disable signal according to an embodiment of the present invention;

16 is a timing diagram illustrating a mode register setting operation performed using data strobe lines and pins of the mode register setting enable/disable signal according to an embodiment of the present invention;

17 is a timing diagram illustrating a mode register setting operation performed using a data signal line and a pin of a mode register setting enable/disable signal according to an embodiment of the present invention;

18 is a block diagram illustrating a topology of a memory module according to an embodiment of the present invention;

Figure 19 is a block diagram illustrating additional topologies of memory modules according to embodiments of the invention;

Figure 20 is a block diagram illustrating a reattach topology of memory modules according to an embodiment of the invention;

Figure 21 is a block diagram illustrating yet additional topologies of memory modules according to embodiments of the present invention;

Figure 22 is a block diagram showing more topologies of memory modules according to an embodiment of the invention;

Figure 23 is a block diagram illustrating still further topologies of memory modules according to embodiments of the present invention;

24 is a schematic diagram showing an output driver according to an embodiment of the present invention;

Figure 25 is a block diagram of a memory system 1900 according to another embodiment of the present invention;

Figure 26 is a block diagram of a memory system 2100 according to yet another embodiment of the present invention;

Figure 27 is a block diagram of a memory system 2200 according to yet another embodiment of the present invention; and

FIG. 28 is a block diagram of a memory system 2300 according to yet another embodiment of the present invention.

Detailed ways

The present invention will be described in more detail hereinafter based on the accompanying drawings showing embodiments of the invention. However, the invention should not be seen as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the above disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. It is further to be understood that the terms "comprises" and/or "comprising", when used in the specification, designate the presence of specified features, integers, steps, operations, units and/or elements, thereby but not excluding one or more other Existence or addition of features, integers, steps, operations, units, elements and/or combinations thereof.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when referring to elements that are to be "directly connected" or "directly coupled" to other elements, there are no intervening elements present. It will be understood that although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the art of the invention. It is further understood that said terms, such as those defined in commonly used dictionaries, should be construed to have a meaning consistent with their meaning in the relevant technical context, and should not be understood in an idealized or overly formal sense , unless so clearly defined here.

In a digital memory system according to an embodiment of the present invention shown in FIG. 7, a memory controller 100 may control operations of a memory module 200 including a plurality of memory devices 300M1-300M9. More particularly, each memory device 300 may be an integrated circuit dynamic random access memory device.

Data signals DATA1-DATA9 can be communicated between memory controller 100 and individual memory devices 300M1-300M9 using separate data signal bus lines. During read operations, data signals DATA1-DATA9 can be read from memory devices 300M1-300M9 into memory controller 100 simultaneously via separate data bus lines, and during write operations, data signals DATA1-DATA9 can be simultaneously read from memory devices 300M1-300M9 to memory controller 100. The memory device 100 is written to the memory devices 300M1-300M9. In addition, separate lines for the data strobe signals DQS1-DQS9 and separate lines for the data mask signals DM1-DM9 are provided between the memory controller 100 and each of the memory devices 300M1-300M9.

In addition, separate lines for the mode register set enable/disable signals ID1-ID9 are provided between the memory controller 100 and each of the memory devices 300M1-300M2. For example, separate dedicated lines may be provided between the memory controller and dedicated mode register setting enable/disable pins on each memory device. Alternatively, lines used to pass data strobe signals DQS1-DQS9 during read/write operations, lines used to pass data signals DATA1-DATA9 during read/write operations, or lines used to pass data mask signals DM1-DATA during read/write operations Lines of DM9 may be used to independently pass mode register set enable/disable signals ID1-ID9 to each memory device 300M1-300M9 during a mode register set operation.

Therefore, the propagation delay between the memory controller 100 and each of the memory devices 300M1-300M9 is critical for the data signals DATA1-DATA9, data strobe signals DQS1-DQS9, data mask signals DM1-DM9, and mode register set enable/disable signal ID1 -ID9 is roughly equal. The configuration of FIG. 1 with separate data buses between the memory controller 100 and each of the memory devices 300M1-300M9 may be said to provide a point-to-point connection.

Conversely, clock/command/address bus 112 may couple control/address signal CA and system clock signal CK from memory controller 100 to each memory device 300M1-300M9. Therefore, the length of the clock signal CK transmission line is different for each memory device 300M1-300M9, so that the propagation delay of the clock signal CK is different for each memory device 300M1-300M9. If the memory devices 300M1-300M9 were evenly spaced along the control/address/clock bus 112, the clock signal CK would experience an incremental propagation delay (also referred to as for phase difference or phase shift). Arbitrarily assigning to the first memory device 300M1 a propagation delay of 0, for example, a clock signal CK propagation delay T would be generated in the second memory device 300M2, a propagation delay of 2T would be generated in the memory device 300M3, and a propagation delay of 3T would be generated in the memory device 300M4 , a propagation delay of 4T will be generated in memory device 300M5, a propagation delay of 5T will be generated in memory device 300M6, a propagation delay of 6T will be generated in memory device 300M7, a propagation delay of 7T will be generated in memory device 300M8, and a propagation delay of 8T will be generated in memory device 300M9. The arrangement of FIG. 7 with a clock signal CK provided to each memory device 300M1-300M9 may be said to provide a fly-by clock.

With the fly-by system clock signal CK provided to each memory device 300M1-300M9 over the same system clock signal line over the clock/command/address bus 112, the read and write data signals DATA1-DATA9 provided over the corresponding point-to-point data bus can be synchronized. According to an embodiment of the present invention, however, each memory device 300M1-300M9 may include an internal clock signal generator configured to adjust the timing of the internal clock signal so that the internal clock signals of the different memory devices 300M1-300M9 may be substantially synchronized even with System clock signals with different propagation delays are received on different memory devices. More particularly, the timing of each internal clock signal can be adjusted relative to a system clock signal CK received at the respective memory device in response to a value stored in a mode register of the memory device. Therefore, the mode registers of different memory devices can be programmed to different values to compensate for the propagation delay difference of the system clock signal CK received by different memory devices.

When the same mode register setting command is applied to all of the memory devices 300M1-300M9 via the address line of the clock/command/address bus 112, during the select mode register setting operation, for example, the mode register setting enable/disable signal ID1- ID9, may be used to enable or disable individual ones of the memory devices 300M1-300M9. For example, during the first selection mode register set operation, the enable mode register set enable/disable signal ID1 may be applied to the memory device 300M1, and the inhibit mode register set enable/disable signals ID2-ID9 may be applied to the memory device 300M1. Device 300M2-300M9. During the second selection mode register set operation, the enable mode register set enable/disable signal ID2 can be applied to the memory device 300M2, and the inhibit mode register set enable/disable signals ID1 and ID3-ID9 can be applied to the memory device 300M2. Apparatus 300M1 and 300M3-300M9. During the third selection mode register setting operation, the enable mode register setting enable/disable signal ID3 may be applied to the memory device 300M3, and the inhibit mode register setting enable/disable signals ID1-ID2 and ID4-ID9 may be applied into memory devices 300M1-300M2 and 300M4-300M9. During the fourth selection mode register setting operation, the enable mode register setting enable/disable signal ID4 may be applied to the memory device 300M4, and the inhibit mode register setting enable/disable signals ID1-ID3 and ID5-ID9 may be applied into memory devices 300M1-300M3 and 300M5-300M9. During the fifth selection mode register setting operation, the enable mode register setting enable/disable signal ID5 may be applied to the memory device 300M5, and the inhibit mode register setting enable/disable signals ID1-ID4 and ID6-ID9 may be applied into memory devices 300M1-300M4 and 300M6-300M9. During the sixth selection mode register setting operation, the enable mode register setting enable/disable signal ID6 may be applied to the memory device 300M6, and the inhibit mode register setting enable/disable signals ID1-ID5 and ID7-ID9 may be applied into memory devices 300M1-300M5 and 300M7-300M9. During the seventh selection mode register setting operation, the enable mode register setting enable/disable signal ID7 may be applied to the memory device 300M7, and the inhibit mode register setting enable/disable signals ID1-ID6 and ID8-ID9 may be applied into memory devices 300M1-300M6 and 300M8-300M9. During the eighth selection mode register setting operation, the enable mode register setting enable/disable signal ID8 can be applied to the memory device 300M8, and the inhibit mode register setting enable/disable signals ID1-ID7 and ID9 can be applied to the memory device 300M8. Apparatus 300M1-300M7 and 300M9. During the ninth selection mode register setting operation, the enable mode register setting enable/disable signal ID9 may be applied to the memory device 300M9, and the inhibit mode register setting enable/disable signals ID1-ID8 may be applied to the memory device 300M1 -300M8 in.

Thus, a series of nine select mode register set operations can be used to program nine different memory devices in different modes of operation. For example, different ones of the memory devices 300M1-300M9 may be programmed to provide adjustments of different timings of the respective internal clock signals relative to the system clock signal CK received by the respective memory devices. In this way, the internal clock signals of the different memory devices are substantially synchronized despite the different propagation delays of the system clock signal CK received by the respective memory devices. Alternatively, or in addition, different ones of the memory devices 300M1 - 300M9 may be programmed to provide different driver output characteristics (eg, driver strengths) for the data signals DATA1 - DATA9 read by the memory controller 100 . Alternatively or additionally, different ones of the memory devices 300M1-300M9 may be programmed to provide different settings and/or supporting characteristics of the data signals DATA1-DATA9 written to the corresponding memory devices. If multiple memory devices 300M1-300M9 are programmed to provide the same characteristics (e.g., same drive strength), the enable mode register set enable/disable signal may be applied to the multiple memory devices during the same select mode register set operation. device.

As shown in FIG. 8A, a memory device 300 according to an embodiment of the present invention may include an internal clock signal generator 310 with a timing control unit 315, an instruction decoder 320, a data input/output (I/O) buffer 330, a memory cell array 340 , address buffer 350 , row decoder 360 , column decoder 380 , and sense amplifier 370 . As mentioned above, the system clock signal CK, the command signal CMD and the address signal ADD may be provided to the clock/command/address pins of the memory device 300 through the lines of the clock/command/address bus 112 . The system clock signal CK may be provided to a dedicated pin of the memory device 300 through a dedicated line of the bus 112 . A command signal CMD such as a chip select (/CS) signal, a row address strobe (/RAS) signal, a column address strobe (/CAS) signal, and a write enable (/WE) signal can be provided to the memory through a dedicated line of the bus 112 Device 300 dedicated pin and instruction decoder 320 . Address signals ADD (including column address signals, row address signals and/or bank address signals) may be provided to the address buffers through address lines of the bus 112 during read and/or write operations. However, during mode register set operations, mode register set instructions may be provided via the address lines of bus 112 . As noted above, the lines of address bus 112 may be connected to multiple memory devices in a memory module.

Data bus lines are connected only between the memory controller and the memory device 300 . More particularly, the data signal DATA, the data strobe signal DQS, and the data mask signal DM may be provided to corresponding input/output, data strobe, and data mask pins through lines of the data bus during reading and/or writing. For example, the mode register setting enable/disable signal ID, during the mode register setting operation, may be provided to a dedicated mode register setting enable/disable pin of the memory device 300, and during read and write operations, the dedicated pin is disabled. effect. Alternatively, the mode register setting enable/disable signal ID may be supplied to one of the data input/output, data strobe or data mask pins during the mode register setting operation.

During a read operation, data is read from the memory cell of the memory cell array 340 identified by the address signal ADD provided by the address buffer 350 . More particularly, sense amplifier 370 reads out data in addresses identified by row decoder 360 and column decoder 380 and provides the data to data I/O buffer 330 as internal data signal iDATA. The buffer 330 provides the data signal DATA corresponding to the internal data signal iDATA, and provides the data signal DATA synchronously with the internal clock signal iCLK generated by the internal clock generator 310 .

During a write operation, the data signal DATA is supplied from the memory controller to the data input/output pin of the memory device 300 and is latched in the data input/output buffer 330 in synchronization with the internal clock signal iCLK. The data signal DATA in the buffer 330 is then provided to the memory cell array 340 as an internal data signal iDATA. The address signal ADD received by the address buffer 350 through the address pins of the memory device 300 defines the memory cell locations of the memory cell array 340 to be written with the internal data signal iDATA.

The mode register setting operation is started by supplying the command signal CMD corresponding to the mode register setting operation. For example, the chip select (/CS) signal, row address strobe (/RAS) signal, column address strobe (/CAS) signal, and write enable (/WE) signal all pass through the clock/command/address bus 112 as low The signal is provided to command decoder 320 to initiate a mode register set operation. Once the mode register set operation is initiated, the mode register set command is provided to the address pins and address buffer 350 via the address line of the clock/command/address bus 112 . Since the mode register set operation has been initiated, the signal received over the address line is interpreted as a mode register set command opposite to the memory address.

The signals provided to the address pins can define various mode register set instructions as shown in the table of FIG. 8B. The bank address pin BA2, for example, can be used to distinguish a normal mode register set operation (logic value "0") from a select mode register set operation according to an embodiment of the present invention, where the select mode register according to an embodiment of the present invention In the setting operation, depending on the logic value of the mode register setting enable/disable signal ID, it is selected whether the mode register setting operation is enabled or disabled. If the normal mode register set operation is selected (by providing a logic value 0 on bank address pin BA2), the bank address pin BA1 can be reserved for future use (RFU) by providing a logic value on bank address pin BA0 A logic value of 0 on BA0 selects a mode register set (MRS) cycle, and a logic value of 1 on bank address pin BA0 selects an extended function mode register set (EMRS) cycle. In an MRS cycle, address pins A9-A12 can be reserved for future use (RFU), address pin A8 can receive a delay-locked loop (DLL) reset command, and address pin A7 can receive a test mode (TM) command , the address pins A4-A6 can receive the CAS latency command, the address pin A3 can receive the burst (burst) type (BT) command and the address pins A0-A3 can receive the burst length command. Conventional MRS and EMRS cycles may be provided to the various memory devices of the memory module by the memory controller on the address lines of the clock/command/address bus 112 . Furthermore, the plurality of memory devices connected to the clock/instruction/address bus 112 all implement conventional MRS or EMRS instructions provided over the bus.

When performing a select mode register set operation according to an embodiment of the present invention, the same select mode register set command is provided to multiple memory devices on the address line of the clock/command/address bus, but the mode register set command may be memory devices, but not other memory devices where the enable/disable signal ID is set according to the mode register applied to each memory device. As described above, a select mode register set instruction according to an embodiment of the present invention may be identified by providing a logic value "1" on bank address pin BA2.

By providing the command signal CMD corresponding to the mode register setting operation (such as /CS, /RAS, /CAS and /WE all being low), and providing a logic value "1" at the bank address pin BA2, it can start according to the present invention. Embodiment mode register set operation. When the command signal and bank address signal are provided to all the memory devices in the module through the clock/command/address bus 112, all the memory devices in the module can receive the command and address signals. But each memory device in the module can receive the mode register setting enable/disable signal ID via a different signal line from the memory controller. In addition, a specific mode register setting enable/disable signal ID received by a specific memory device may determine whether the mode register setting operation is performed in the device.

When the command signal CMD corresponding to the mode register setting operation is supplied to the command decoder 320 of the memory device 300, and when the address signal ADD including the bank address signal BA2 having a logic value of 1 is supplied to the address buffer 350, the memory The device can recognize a select mode register set operation according to an embodiment of the present invention. The memory device 300 determines whether to perform the selection mode register setting operation according to the value of the mode register setting enable/disable signal ID selectively provided to the memory device 300 but not to other memory devices in the module. If the enable mode register setting enable/disable signal ID is supplied to the memory device 300, the selection mode register setting operation is performed according to a mode register setting command received through an address line of the address buffer 350 according to an embodiment of the present invention. More particularly, part of the mode register setting instructions are written to a mode register (eg, provided in control unit 315) to achieve a desired mode of operation. If the inhibit mode register set enable/disable signal ID is supplied to the memory device 300, the select mode register set operation may be ignored according to an embodiment of the present invention.

A system clock signal CK may be provided as an input to the control unit in FIG. 8A, and an internal clock signal may be provided as an output of the iCLK control unit 315, as shown in FIG. 9A. More particularly, the control unit 315 in FIG. 8A may include a plurality of delay circuits 401a-h, and each delay circuit may include a respective buffer circuit 403a-h. The tap selection circuit 405 may select the input of the delay circuit 401a or the output of one of the delay circuits 401a-h to adjust the timing of the internal clock signal iCLK, and the tap selection may be determined in response to a selection mode register according to an embodiment of the present invention Set action. More particularly, the mode register MR provided in the tap selection circuit 405 can be set in response to a mode register set command received by the memory device during a select mode register set operation, so that desired timing of the internal clock signal can be achieved.

For example, the taps of delay circuit 401d can be arbitrarily selected and used as default taps to provide default timing outputs. Taps other than the default taps may be selected to advance or delay the internal clock signal relative to the default taps. Therefore, the tap selection circuit 405 can select a particular tap to define the timing of the internal clock signal iCLK relative to the system clock signal CK. In addition, the tap selection circuit 405 may select a particular tap in response to a select mode register setting operation according to an embodiment of the present invention. Therefore, the delay of the internal clock signal iCLK with respect to the system clock signal CK is different with respect to different memory devices in the memory module to compensate for different propagation delays of the system clock signal CK in different memory devices.

Accordingly, a select mode register set operation may be performed for the memory device 300 to adjust the timing of the internal clock signal iCLK relative to the system clock signal CK. By providing the command signal CMD corresponding to the mode register setting operation, and providing the address buffer 350 with the mode register setting command, and by providing the enabling mode register setting enable/disable signal ID to the memory device 300, the memory device 300 is started The select mode register sets the operation. A mode register set instruction may be identified as a select mode register set instruction, for example, by providing a logic value “1” to bank address line BA2 of clock/command/address bus 112 .

With the control unit 315 having nine different delay taps, nine different timing instructions MRS1-MRS9 can be used to define the taps to be selected by the tap selection circuit 405 shown in FIG. 9B. Additionally, four bit codes are provided to define the various timing commands MRS1-MRS9 via four predetermined address lines of the clock/command/address bus 112 during select mode register set operations. For example, each delay circuit 401a-h may provide an advance/delay T approximately equal to the propagation delay difference of the system clock signal CK between adjacent memory devices of the clock/instruction/address bus 112 along the clock/instruction/address bus 112 . 9A and 9B, the timing instruction MRS1 can provide the relative delay +4T of the internal clock signal iCLK by selecting the tap of the output of the delay circuit 401h; the timing instruction MRS2 can provide the internal clock signal iCLK by selecting the tap of the output of the delay circuit 401g The relative delay of +3T; the timing instruction MRS3 can provide the relative delay of the internal clock signal iCLK +2T by selecting the tap of the output of the delay circuit 401f; the timing instruction MRS4 can provide the internal clock signal iCLK by selecting the tap of the output of the delay circuit 401e The relative delay of +1T; the timing instruction MRS5 can provide the reference or default (0 advance or delay) of the internal clock signal iCLK by selecting the output tap of the delay circuit 401d; the timing instruction MRS6 can select the output tap of the delay circuit 401c , providing the relative advance of the internal clock signal iCLK -1T; the timing instruction MRS7 can provide the relative advance of the internal clock signal iCLK -2T by selecting the tap of the output of the delay circuit 401b; the timing instruction MRS8 can select the tap of the output of the delay circuit 401a , providing a relative advance of the internal clock signal iCLK by −3T; and the timing instruction MRS9 may provide a relative advance of the internal clock signal iCLK by −4T by selecting taps of the input of the delay circuit 401 a.

Referring to the memory module 200 and the memory controller 100 of FIG. 7, the same memory devices 300M1-300M9 may be provided on the module 200, and the module 200 has each memory device supporting the select mode register setting operation according to an embodiment of the present invention, so that Supports the timing adjustment of its internal clock. Memory controller 100 can perform nine select mode register set operations to define the operation of each memory device's internal clock generator. For example, the memory controller 100 may provide select mode register set instructions to adjust the timing of the internal clock signal based on the location of each memory device 300M1-300M9, and the assumed propagation delay of the system clock signal CK at each memory device location . Alternatively, memory controller 100 may provide select mode register set instructions to adjust internal clock timing based on the measured performance of the individual memory devices in module 200 .

According to a particular embodiment of the present invention, the selective mode register set instructions MRS1-MRS9 in FIG. 9B may be selectively applied to the respective memory devices 300M1-300M9. In a first select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS1 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID1 can be applied For memory device 300M1, and disable mode register setting enable/disable signals ID2-ID9 may be applied to memory devices 300M2-300M9. In a second select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS2 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID2 can be applied For memory device 300M2, and inhibit mode register setting enable/disable signals ID1 and ID3-ID9 may be applied to memory devices 300M1 and 300M3-300M9. In the third selection mode register setting operation, along clock/command/address, bus 112, mode register setting command MRS3 can be applied to all memory devices 300M1-300M9, enabling mode register setting enable/disable signal ID3 can be Applied to memory device 300M3, and inhibit mode register setting enable/disable signals ID1-ID2 and ID4-ID9 may be applied to memory devices 300M1-300M2 and 300M4-300M9. In a fourth select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS4 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID4 can be applied For memory device 300M4, and inhibit mode register setting enable/disable signals ID1-ID3 and ID5-ID9 may be applied to memory devices 300M1-300M3 and 300M5-300M9.

In the fifth select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS5 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID5 can be applied For memory device 300M5, and inhibit mode register setting enable/disable signals ID1-ID4 and ID6-ID9 may be applied to memory devices 300M1-300M4 and 300M6-300M9. In the sixth select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS6 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID6 can be applied For memory device 300M6, and inhibit mode register setting enable/disable signals ID1-ID5 and ID7-ID9 may be applied to memory devices 300M1-300M5 and 300M7-300M9. In the seventh selection mode register setting operation, along the clock/command/address bus 112, the mode register setting command MRS7 can be applied to all memory devices 300M1-300M9, and the enable mode register setting enable/disable signal ID7 can be applied For memory device 300M7, and inhibit mode register setting enable/disable signals ID1-ID6 and ID8-ID9 may be applied to memory devices 300M1-300M6 and 300M8-300M9. In the eighth select mode register set operation, along the clock/command/address bus 112, the mode register set command MRS8 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID8 can be applied For memory device 300M8, and inhibit mode register setting enable/disable signals ID1-ID7 and ID9 may be applied to memory devices 300M1-300M7 and 300M9. In the ninth selection mode register set operation, along the clock/command/address bus 112, the mode register set command MRS9 can be applied to all memory devices 300M1-300M9, and the enable mode register set enable/disable signal ID9 can be applied For memory device 300M9, and disable mode register setting enable/disable signals ID1-ID8 may be applied to memory devices 300M1-300M8.

As shown in the timing diagrams of FIGS. 10 and 11 , the above select mode register setting operation can provide substantially synchronous internal clock signal iCLK to different memory devices 300M1 - 300M9 in the memory module 200 shown in FIG. 7 . During a read operation as shown in FIG. 10 , due to different propagation delays along the clock/instruction/address bus 112 , different memory devices in the memory module receive transmissions of the system clock signal CK at different times. More particularly, the rising edge of the system clock signal may be received by memory device 300M1 before it is received by memory device 300M5, as indicated by signals CK1 and CK5, and before it is received by memory device 300M9, as indicated by signals CK5 and CK9. A rising edge of the system clock signal may be received by the memory device 300M5. The internal clock signals iCLK1, iCLK5, and iCLK9 can be substantially synchronized because the timing of the internal clock signals operating the memory devices has been selectively adjusted using the select mode register settings. More specifically, the delay of the internal clock signal iCLK1 can be increased relative to the clock signal CK1 received by the first memory device 300MI, and the default delay of the internal clock signal iCLK5 can be maintained relative to the clock signal CK5 received by the fifth memory device 300M5 , and the delay of the internal clock signal iCLK9 can be reduced relative to the clock signal CK9 received by the memory device 300M9.

Accordingly, the timing of latching the internal signal iDATA of each memory device 300M1-300M9 into the respective input/output buffer may be determined relative to the substantially synchronous internal clock signal iCLK1-9. Thus, the timing of providing the data signals DATA1-DATA9 to the memory controller 100 via the respective data buses is also approximately synchronized. Therefore, during the data read operation, the data signals DATA1-DATA9 can be provided to the respective data buses at approximately the same time, so that the data skew can be reduced.

During the write operation shown in FIG. 11 , different memory devices in the memory module receive transmissions of the system clock signal CK at different times due to different propagation delays along the clock/instruction/address bus 112 . As mentioned above, the internal clock signals iCLK1-iCLK9 are substantially synchronous. Accordingly, the timing of the latched data signal DATA from the memory controller of each memory device 300M1-300M9 to the respective input/output buffer may be determined relative to the substantially synchronous internal clock signal iCLK1-9. Thus, the timing of supplying the internal data iDATA1-iDATA9 from the I/O buffers to the memory cell array 340 through the respective data buses is also substantially synchronized. Therefore, during a data write operation, the data signals DATA1-DATA9 may be received into the respective input/output buffers of the memory devices in the module at approximately the same time, and thus the data skew is reduced.

In a memory module 200 comprising a plurality of memory devices 300M1-300Mn, the mode register set command is provided through a clock/command/address bus 112 coupled to all memory devices 300M1-300Mn. However, the mode register setting enable/disable signals ID1-IDn can be independently provided between the memory controller 100 and the respective memory devices 300M1-300Mn. As described above, according to an embodiment of the present invention, some mode register setting commands may identify select mode register set commands, enable mode register set enable/disable signals may identify respective memory devices to which select mode register set commands are applied, and disable The mode register set enable/disable signal may identify respective memory devices to which the select mode register set instruction is not applied. If only the mode register setting enable/disable signal ID1 is enabled, and the mode register setting enable/disable signals ID2-IDn are disabled, the select mode register setting command is only applied to the memory device 300M1. Alternatively, the enable mode register set enable/disable signal may be applied to a plurality of memory devices during the select mode register set operation so that the select mode register set operation may be applied to a plurality of enabled memory devices at the same time. Thus the selection mode register setting operation according to an embodiment of the present invention can be applied to one memory device in a module, a plurality of memory devices in a module, or all memory devices in a module.

As mentioned above, the mode register MR according to the embodiment of the present invention can be considered as a part of the internal clock generator 310 , more particularly a part of the tap selection circuit 405 . Alternatively, the mode register according to embodiments of the present invention may be considered part of instruction decoder 320 , address buffer 350 , data I/O buffer 330 , and/or other parts of memory device 300 . As further described above, the mode register MR may store information corresponding to select mode register set instructions defining memory device operating characteristics (eg, internal clock signal advance/retard). Additionally, multiple operating characteristics of the memory device (eg, internal clock signal advance/delay, output driver strength, data input setup time, and/or data input hold time) may be set using single select mode register set instructions. Thus, a single mode register according to an embodiment of the present invention may store information corresponding to a select mode register set instruction that defines multiple operating characteristics of the memory device. Alternatively, different operating characteristic settings can be provided to multiple mode registers using a single select mode register set instruction.

FIG. 13 is a timing diagram showing selection mode register setting operations of the memory devices 300M1-300Mn in FIG. 12 . In the example of FIG. 13, the mode register setting enable/disable signals ID1-IDn are provided to the dedicated mode register setting enable/disable pins in the respective memory devices 300M1-300Mn through the dedicated mode register setting enable/disable lines. . In other words, the dedicated mode register sets the enable/disable lines and pins to no effect during data read and/or write operations.

As shown in FIG. 13, the first mode register setting command MRS1 can be applied through the clock/command/address bus 112, the enable mode register setting enable/disable signal ID1 (logic value 0) can be applied to the first memory device 300M1, and During the first mode memory set operation C1, inhibit mode register set enable/disable signals ID2-IDn (logic value 1) may be applied to the memory devices 300M2-300Mn. Therefore, the first mode register setting operation C1 may provide delay adjustment for the internal clock signal iCLK1 of the memory device 300M1.

During the second mode register setting operation C2, the second mode register setting instruction MRS2 can be applied through the clock/command/address bus 112, and the enabling mode register setting enable/disable signal ID2 (logic value 0) can be applied to the second memory Device 300M2, and inhibit mode register set enable/disable signals ID1 and ID3-IDn (logic value 1) are applicable to memory devices 300M1 and 300M3-300Mn. Therefore, the second mode register setting operation C2 may provide delay adjustment for the internal clock signal iCLK2 of the memory device 300M2.

During the nth mode register setting operation Cn, the nth mode register setting command MRSn can be applied through the clock/command/address bus 112, and the enabling mode register setting enable/disable signal IDn (logic value 0) can be applied to the nth memory Device 300Mn, and inhibit mode register set enable/disable signal ID1-ID(n-1) (logic value 1) are applicable to memory devices 300M1-300M(n-1). Therefore, the nth mode register setting operation Cn may provide delay adjustment for the internal clock signal iCLKn of the memory device 300Mn.

Independent mode register setting operations can provide different internal clock timing adjustments for different memory devices in the memory module. Additionally/alternatively, separate mode register set operations may provide different driver strengths for different memory devices, different setup and/or hold times for different memory devices, and/or other variables that vary across memory devices of the same memory module. characteristic.

FIG. 14 is a timing diagram illustrating a write operation of the memory module 200 including memory devices 300M1-300M9 during a write operation. As shown, the first memory device 300M1 may receive the transmission of the system clock signal before the fifth memory device 300M5 as shown by signals CK1 and CK5, and the first memory device 300M9 before the ninth memory device 300M9 as shown by signals CK5 and CK9. Five memory devices 300M5 may receive transitions of the system clock signal. As mentioned above, the selection mode register setting operation can provide adjustment of the internal clock signals iCLK1-iCLK9 so that the internal clock signals can be substantially synchronized.

During a write operation, the data strobe signal DQS of each memory device may transition from a high impedance (Hi-Z) state to a logic low state, and the data strobe signal remains at Low state during DQS pre-sync period. Subsequent transitions of the data strobe signal may signal that each memory device on the respective data bus provides new data D1-D4. Therefore, the skew between the transition from the high-impedance state to the low-impedance state and the rising edge of the system clock signal received by each memory device can limit high frequency memory operations. With substantially synchronized internal clock signals in the different memory devices, the data strobe signals are substantially synchronized with respect to the internal clock signals of the different memory devices so that the frequency of operation can be increased.

FIG. 15 is a timing diagram showing the selection mode register setting operation of each of the memory devices 300M1-300Mn in FIG. 12 . In the example of FIG. 15, mode register set enable/disable signals ID1-IDn are supplied to data mask pins of respective memory devices 300M1-300M9 through data mask lines during select mode register set operations. The data mask lines and pins are used to provide data mask signals to respective memory devices during read and/or write operations. Since the mode register set enable/disable signals ID1-ID9 are provided through data mask lines and pins, the mode register set enable/disable signals are labeled DM1-DMn in FIG. 15 .

As shown in FIG. 15, during the first selection mode register setting operation C1, the first selection mode register setting instruction MRS1 is applied through the clock/command/address bus 112, and the enable mode register setting enable/disable signal ID1 can be applied as DM1 In the first memory device 300M1, and the disable mode register setting enable/disable signals ID2-IDn may be applied to the memory devices 300M2-300Mn as DM2-DMn. Therefore, the first mode register setting operation C1 may provide delay adjustment for the internal clock signal iCLK1 in the memory device 300M1.

During the second selection mode register setting operation C2, the second selection mode register setting instruction MRS2 is applied through the clock/command/address bus 112, and the enabling mode register setting enable/disable signal ID2 can be applied as DM2 to the second memory device 300M2 , and the inhibit mode register setting enable/disable signals ID1 and ID3-IDn may be applied to the memory devices 300M1 and 300M3-300Mn as DM1 and DM3-DMn. Therefore, the second selection mode register setting operation C2 may provide delay adjustment for the internal clock signal iCLK2 in the memory device 300M2.

During the nth selection mode register setting operation Cn, the nth selection mode register setting command MRSn is applied through the clock/command/address bus 112, and the enable mode register setting enable/disable signal IDn can be applied as DMn to the nth memory device 300Mn , and the inhibit mode register setting enable/disable signal ID1-ID(n-1) may be applied to the memory devices 300M1-300M(n-1) as DM1-DM(n-1). Therefore, the nth selection mode register setting operation Cn may provide delay adjustment for the internal clock signal iCLKn in the memory device 300Mn.

According to the embodiment shown in FIG. 15 , no additional dedicated mode register setting enable/disable lines and pins are required, since off-the-shelf data mask lines and pins are used. It is therefore possible to provide a selection mode register setting operation according to an embodiment of the present invention without increasing the number of pins of a memory device supporting the selection mode register setting operation.

FIG. 16 is a timing diagram showing the selection mode register setting operation of each memory device 300M1-300Mn in FIG. 12 . In the example of FIG. 16, during select mode register set operations, mode register set enable/disable signals ID1-IDn are provided to data strobe pins in respective memory devices 300M1-300M9 through data strobe lines. Data strobe lines and pins are used to provide data strobe signals to respective memory devices during read and/or write operations. Since the mode register set enable/disable signals ID1-ID9 are provided through data strobe lines and pins, the mode register set enable/disable signals are labeled DQS1-DQSn in FIG. 15 .

As shown in FIG. 16, during the first mode register setting operation C1, the first mode register setting command MRS1 is applied through the clock/command/address bus 112, and the enabling mode register setting enable/disable signal ID1 can be applied to the first mode register as DQS1. A memory device 300M1, and inhibit mode register set enable/disable signals ID2-IDn may be applied to the memory devices 300M2-300Mn as DQS2-DQSn. Therefore, the first mode register setting operation C1 may provide delay adjustment for the internal clock signal iCLK1 in the memory device 300M1.

During the second mode register set operation C2, the second mode register set command MRS2 is applied through the clock/command/address bus 112, the enable mode register set enable/disable signal ID2 can be applied to the second memory device 300M2 as DQS2, and Inhibit mode register setting enable/disable signals ID1 and ID3-IDn may be applied to memory devices 300M1 and 300M3-300Mn as DQS1 and DQS3-DQSn. Therefore, the second mode register setting operation C2 may provide delay adjustment for the internal clock signal iCLK2 in the memory device 300M2.

During the nth mode register setting operation Cn, the nth mode register setting command MRSn is applied through the clock/command/address bus 112, the enable mode register setting enable/disable signal IDn is available as DQSn to the nth memory device 300Mn, and Inhibit mode register setting enable/disable signals ID1-ID(n-1) may be applied to memory devices 300M1-300M(n-1) as DQS1-DQS(n-1). Therefore, the nth mode register set operation Cn may provide delay adjustment for the internal clock signal iCLKn in the memory device 300Mn.

According to the embodiment shown in FIG. 16, additional dedicated mode register setting enable/disable lines and pins are not required since existing data strobe lines and pins are used. A select mode register set operation according to an embodiment of the present invention thus does not require an increase in the pin count of a memory device supporting the select mode register set operation.

FIG. 17 is a timing diagram showing a selection mode register setting operation of each of the memory devices 300M1-300Mn in FIG. 12 . In the example of FIG. 17, mode register set enable/disable signals ID1-IDn are supplied to data signal pins in respective memory devices 300M1-300M9 through data signal lines during select mode register set operations. During read and/or write operations, the data signal lines and pins are used to communicate data read from and written to the respective memory devices. Since the mode register setting enable/disable signals ID1-ID9 are provided through data signal lines and pins, the mode register setting enable/disable signals in FIG. 15 are labeled DQ1-DQn. Multiple data signal pins are provided on each memory device, but a single one of the data signal pins in each memory device is used to receive a mode register set enable/disable signal during select mode register set operations .

As shown in FIG. 17, during the first mode register setting operation C1, the first mode register setting command MRS1 is applied through the clock/command/address bus 112, and the enabling mode register setting enable/disable signal ID1 can be applied to the first mode register as DQ1. A memory device 300M1, and inhibit mode register set enable/disable signals ID2-IDn may be applied to the memory devices 300M2-300Mn as DQ2-DQn. Therefore, the first mode register setting operation C1 may provide delay adjustment for the internal clock signal iCLK1 in the memory device 300M1.

During the second mode register set operation C2, the second mode register set command MRS2 is applied through the clock/command/address bus 112, the enable mode register set enable/disable signal ID2 can be applied as DQ2 to the second memory device 300M2, and Inhibit mode register setting enable/disable signals ID1 and ID3-IDn may be applied to memory devices 300M1 and 300M3-300Mn as DQ1 and DQ3-DQn. Therefore, the second mode register setting operation C2 may provide delay adjustment for the internal clock signal iCLK2 in the memory device 300M2.

During the nth mode register setting operation Cn, the nth mode register setting command MRSn is applied through the clock/command/address bus 112, the enable mode register setting enable/disable signal IDn can be applied to the nth memory device 300Mn as DQn, and Inhibit mode register setting enable/disable signals ID1-ID(n-1) may be applied to memory devices 300M1-300M(n-1) as DQ1-DQ(n-1). Therefore, the nth mode register set operation Cn may provide delay adjustment for the internal clock signal iCLKn in the memory device 300Mn.

According to the embodiment shown in FIG. 17, no additional dedicated mode register setting enable/disable lines and pins are required since existing data strobe lines and pins are used. A select mode register set operation according to an embodiment of the present invention thus does not require an increase in the pin count of a memory device supporting the select mode register set operation.

As described above, select mode register set operations according to embodiments of the present invention can be used to selectively adjust the timing of internal clock signals of different memory devices sharing the same clock/instruction/address bus. Additionally or alternatively, select mode register set operations according to embodiments of the present invention may be used to selectively set, adjust and/or change operating characteristics of memory devices sharing the same clock/instruction/address bus other than internal clock signal timing.

Furthermore, different layouts of the memory modules shown in FIG. 7 are provided according to embodiments of the present invention. As shown in FIG. 18, at a first end of a row of memory devices 300M1-300M9, a clock/instruction/address bus 112A may enter a memory module 200A, and at a second end of a row of memory devices, a terminal 400A may be provided to the bus 112 lines. More specifically, the terminals may include resistors coupled between the respective line ends and a reference voltage (eg, supply voltage Vcc). By providing terminal 400A, the quality of the various clock, command and/or address signals provided along clock/command/address bus 112 will be improved.

As shown in FIG. 19, between memory devices in rows of memory devices 300M1-300M9, clock/command/address bus 112B may enter memory module 200B, and bus 112 may extend in the opposite direction. Additionally, terminal 400B may be provided to bus 112 at the opposite end of the row of memory devices 300M1-300M9. Each line of the bus 112 may thus be terminated using a pair of resistors, the first resistor of the line terminating the line at the first end of the row of memory devices, and the second resistor of the pair having the line terminated at the second end of the row of memory devices. resistance. By feeding the bus approximately in the middle of a row of memory devices, the skew of the system clock signal received by different memory devices in the row is reduced. In the example of FIG. 7 , the memory device 300M9 may receive the transmission of the system clock signal 8T time period after the memory device 300M1 receives the transmission. Assuming an additional propagation delay of T for each memory device along bus 112B in FIG. 19, memory device 300M1 may receive the transmission of the system clock signal 4T time period after memory device 300M5 receives the transmission. Therefore, the maximum skew of the system clock signals received by different memory devices of the module 200B can be reduced by approximately a factor of 2.

As shown in Figure 20, separate clock/command/address buses 112C and 114C are provided to different groups of memory devices in a row of memory module 200C. For example, memory devices 300M1-300M5 may be provided along bus 112C, and memory devices 300M6-300M9 may be provided along bus 114C. Additionally, a terminal 400C may be provided at the end of each bus 112C and 114C. Although buses 112C and 114C are shown entering in the middle of a row of a memory device having terminations 400C at the end of the row of memory devices, buses 112C and 114C may also enter opposite ends of a row of memory devices with terminations provided in the middle of the row of memory devices. . In this way the maximum skew in the transfer of system clock signals received by different memory devices can be reduced, as described above with reference to FIG. 19 .

By providing independent buses 112C and 114C, select mode register setting operations according to embodiments of the present invention may be performed simultaneously for different memory devices in module 200C. If separate select mode register set operations are performed for each memory device 300M1-300M9, for example, five consecutive mode register set operations for memory devices 300M1-300M5 may be performed in parallel with four consecutive mode register set operations for memory devices 300M6-300M9 . Thus, two independent clock/instruction/address buses are used to perform independent select mode register set operations from nine memory devices compared to performing nine consecutive mode register set operations using a single clock/instruction/address bus. Time decreases.

As shown in FIG. 21, on buses 504A and 504B, clock/command/address bus 112D from the memory controller may feed register 500A which independently provides buffered clock/command/address signals. A phase locked loop (PLL) circuit 502 is provided to improve the system clock signal received from the memory controller, and a terminal 400D may be provided at the end of the bus 504A-B. By providing separate buses 504A-B all fed from register 500A, the maximum skew in the transfer of system clock signals received by different memory devices can be reduced. As shown, register 500A and phase locked loop circuit 502 may be provided simultaneously. Alternatively, the register 500A may be provided without the phase locked loop circuit 502, or with the phase locked loop circuit 502 provided and the register 500A provided.

As shown in FIG. 22, the clock/command/address signals and data signals of all memory devices in the memory module 200F can be provided from the memory controller to the register 500B, and the clock/command/address signals can be individually buffered and provided in on bus 604A-B, as described above with reference to FIG. 21 . In addition, register 500B may provide an independent data signal DATA, an independent data mask signal DM, and an independent data strobe signal DQS through an independent bus to each memory device 300M1-300M9. Additionally, a terminal 400E may be provided for each bus 604A-B. Although not shown in FIG. 22 , a phase locked loop (PLL) circuit may be provided to the system clock signal, as described above with reference to FIG. 21 .

As shown in FIG. 23, clock/command/address bus 112 is used to enter memory module 2000F between memory devices in rows of memory devices 300M1-300M9, providing a fly-by topology of clock/command/address bus 112. Such a topology may provide an advantageous layout for coupling memory controllers.

As described above, select mode register set operations according to embodiments of the present invention can be used to selectively adjust the timing of internal clock signals in different memory devices sharing the same clock/instruction/address bus. Additionally or alternatively, select mode register set operations according to embodiments of the present invention may be used to selectively set, adjust and/or change operating characteristics of memory devices sharing the same clock/instruction/address bus other than internal clock signal timing. For example, select mode register set operations according to embodiments of the present invention can be used to set different driver strengths for different memory devices sharing the same clock/instruction/address bus.

For example, each memory device 300M1 - 300M9 in memory module 200 may include a respective data I/O buffer 330 as described above with reference to FIGS. 7 and 8 . In addition, the data signal DATA of each memory device 300 may include a plurality of data bits DQ, and the internal data signal iDATA of each memory device 300 may include a respective plurality of internal data bits iDQ. Accordingly, data I/O buffer 330 may include a plurality of output drivers 150 provided to convert each internal data bit iDQ to a respective data bit DQ provided on a respective I/O pin 152 on the memory device. , for example, as shown in Figure 24.

More specifically, output driver 150 may have a basic driver circuit including transistors 130 and 140 , and an auxiliary driver circuit including transistors 132 , 134 , 142 and 144 . During a read operation, internal data bit iDQ with logic value "1" may turn on transistor 140 and turn off transistor 130, so that I/O pin 152 is coupled to ground voltage VSS through transistor 140, and data bit DQ has logic value " 0". During a read operation, internal data bit iDQ with logic value "0" turns off transistor 140 and turns on transistor 130, so that I/O pin 152 is coupled to supply voltage VDD through transistor 130, and data bit DQ has logic value "1" ". The basic driver circuit includes transistors 130 and 140 , which perform the logic function of output driver 150 . The auxiliary driver circuit includes transistors 132, 134, 142 and 144, which can be disabled by providing a signal CON of a logic value "0" and by providing an inverse signal /CON of a logic value "1", so that transistors 132 and 142 are turned off.

The strength of the output driver 150 can be increased by providing a logic value "1" signal CON and an inverse signal /CON providing a logic value "0" such that transistors 132 and 142 are turned on and the auxiliary driver circuit is enabled. With the auxiliary driver circuit enabled during a read operation, an internal data bit iDQ with a logic value of "1" may turn on transistors 140 and 144, and turn off transistors 130 and 134, so that I/O pin 152 passes through transistors 140 and 144 is coupled to ground voltage VSS, and data bit DQ has a logic value of "0". With the auxiliary driver circuit enabled during a read operation, an internal data bit iDQ with a logic value of "0" may turn off transistors 140 and 144, and turn on transistors 130 and 134, so that I/O pin 152 passes through transistors 130 and 134 is coupled to supply voltage VDD, and data bit DQ has a logic value of "1." With the auxiliary driver circuit enabled, the base and auxiliary driver circuits perform the logic functions of the output driver 150 in parallel, thus increasing the driver strength of the output driver 150 .

Select mode register set operations may thus be performed for each memory device 300M1 - 300M9 to set different output driver characteristics for different memory devices sharing the same clock/command/address bus 112 . As described above, during a mode register set operation, a select mode register set command may be provided via an address line of the clock/command/address bus 112, and an enable mode register set enable/disable signal may be provided to the applied mode register set command. memory device. Furthermore, the logic value of a single bit in the mode register set instruction can define whether all output drivers of the memory device should provide increased or decreased driver strength. Alternatively, a first select mode register set instruction operation may be executed for a first plurality of memory devices requiring a first output driver strength, and a second select mode register set instruction operation may be executed for a second plurality of memory devices requiring a second output driver strength. Multiple memory devices.

Still alternatively, select mode register operations may feed different driver strengths of output drivers in the same memory device. For example, a data signal DATA for a memory device may include eight data bits DQ, and each memory device may include eight respective output drivers. Thus, the eight bits of the select mode register set instruction of the memory device can define the driver strengths of the eight respective output drivers.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and content may be made without departing from the spirit and scope of the invention as defined by the appended claims. kind of change.

FIG. 25 is a block diagram of a memory system 1900 according to another embodiment of the present invention. Referring to FIG. 25, a memory system 1900 includes a memory controller 1910 and a memory module 1920 including a plurality of memory devices 1930M1 to 1930M9. The memory controller 1910 controls the memory devices 1930M1 to 1930M9 using a clock signal CK and a command address signal CA, and generates mode register setting enable/disable signals ID1 to ID9 that selectively control the memory devices 1930M1 to 1930M9.

In the first mode, the memory devices 1930M1 to 1930M9 are respectively set to different operation modes in response to the mode register setting enable/disable signals ID1 to ID9 and the command address signal CA. In the second mode, the memory devices 1930M1 to 1930M9 operate in a set operation mode in response to a predetermined command address signal CA.

Here, before the memory devices 1930M1 to 1930M9 operate normally, the first mode is a mode to set the memory devices 1930M1 to 1930M9 to a corresponding operation mode, and the second mode is a mode to normally operate the memory devices 1930M1 to 1930M9.

That is, in the first mode, the memory devices 1930M1 to 1930M9 are respectively set to corresponding operation modes in response to the command address signal CA. At that time, whether the operation mode of each memory device should be set depends on the activation of the corresponding mode register setting enable/disable signals ID1 to ID9.

In other words, if the corresponding mode register setting enable/disable signals ID1 to ID9 are activated, each memory device 1930M1 to 1930M9 is set to the corresponding operation mode in response to the command address signal CA. If the corresponding mode register setting enable/disable signals ID1 to ID9 are disabled, the memory devices 1930M1 to 1930M9 do not respond to the command address signal CA. Therefore, it is possible to set the operation modes of the memory devices 1930M1 to 1930M9 differently from each other by setting the enable/disable signals ID1 to ID9 using the mode register.

For example, when the command address signal CA is applied, if the mode register setting enable/disable signals ID1 to ID5 corresponding to the memory devices 1930M1 to 1930M5 are activated, and the mode register setting enable/disable signals corresponding to the memory devices 1930M6 to 1930M9 ID6 to ID9 are deactivated, then only the memory devices 1930M1 to 1930M5 are set to the operation mode in response to the command address signal CA, and the memory devices 1930M6 to 1930M9 do not respond to the command address signal CA.

Thereafter, if the mode register setting enable/disable signals ID1 to ID5 are deactivated, the mode register setting enable/disable signals ID6 to ID9 are activated, and the command address signal CA for setting different operation modes is applied, the memory devices 1930M6 to 1930M9 The operation mode of the memory devices 1930M1 to 1930M5 may be set to be different from the operation modes of the memory devices 1930M1 to 1930M5.

After the memory devices 1930M1 to 1930M9 are set to different operation modes in the first mode, in the second mode, the memory devices 1930M1 to 1930M9 are operated in the different operation modes by applying a predetermined command address signal CA.

According to an embodiment of the present invention, if the mode register setting enable/disable signals ID1 to ID5 corresponding to the memory devices 1930M1 to 1930M5 are activated, the memory devices 1930M1 to 1930M5 are set to the refresh mode in response to the command address signal CA. If the mode register setting enable/disable signals ID6 to ID9 corresponding to the memory devices 1930M6 to 1930M9 are activated, the memory devices 1930M6 to 1930M9 are set to a deep power down mode in response to the command address signal CA.

In deep power-down mode, the memory device's internal voltage supply is turned off, and the memory device's external voltage supply remains on. Therefore, in the memory device in the deep power down mode, no refresh operation is performed. That is, when the command address signal CA for setting the refresh mode is applied, the mode register setting enable/disable signals ID1 to ID5 corresponding to the memory devices 1930M1 to 1930M5 are activated, and the mode registers corresponding to the memory devices 1930M6 to 1930M9 are activated. The register setting enables/disables the signals ID6 to ID9 to be disabled.

Accordingly, in response to the command address signal CA applied to the memory devices 1930M1 to 1930M5, the memory devices 1930M1 to 1930M5 are set to the refresh mode, and the remaining memory devices 1930M6 to 1930M9 are not set to the refresh mode. Thereafter, if the mode register setting enable/disable signals ID1 to ID5 are deactivated, the mode register setting enable/disable signals ID6 to ID9 are activated, and the command address signal CA for setting the deep power-off mode is applied, the memory devices 1930M6 to The 1930M9 can be set to deep power down mode.

The internal configuration of each memory device set to the refresh mode or the deep power-down mode in response to the mode register setting enable/disable signals ID1 to ID9 and the command address signal CA is well known to those of ordinary skill in the art, and therefore, omitted its detailed description. In the second mode in which the memory module 1920 normally operates, if a command address signal CA for commanding a refresh operation is applied, the memory devices 1930M1 to 1930M5 perform a refresh operation, and the memory devices 1930M6 to 1930M9 operate in a deep power-down mode.

Here, it is possible to apply the command address signal CA for commanding a deep power down operation instead of the command address signal CA for commanding a refresh operation. That is, in the second mode, the command address signal CA for the memory devices operating in different operation modes can be arbitrarily set. Therefore, it is possible to reduce power consumption by setting a memory device storing data that should be saved to a refresh mode and a memory device storing data that can be erased to a deep power down mode.

The technical concept of the present invention is not limited to the memory module 1920 shown in FIG. 25, and the technical concept of the present invention can be applied to various memory module structures shown in FIGS. 18 to 23 according to an embodiment of the present invention. The command address signal CA generated from the memory control 1910 may be an MRS (Mode Register Set) command. This will be described in detail below with reference to FIG. 8B.

Typically, an MRS instruction includes an address code portion (A0 to A12) and two bank address portions (BA0 and BA1). A0 to A12 and BA0 and BA1 represent address codes and bank addresses, respectively, but A0 to A12 and BA0 and BA1 may represent address pins. The logical value of the address code, such as burst length and CAS waiting time, is determined according to the address code.

Whether the MRS cycle is the current cycle is determined according to the logical value of the memory bank address. The address code and the bank address together are referred to as "MRS key address code". The MRS instruction used in this embodiment further includes a third memory bank address BA2.

According to the third bank address BA2 of the MRS key address code of the MRS command, it is determined whether the memory controller 1910 sets the enable/disable signal ID for the active mode register. If the third bank address BA2 is low, the memory controller 1910 disables the mode register setting enable/disable signal ID. This is the same as in the conventional MRS instruction for the third bank address BA2 without the MRS key address code.

On the contrary, if the third bank address BA2 of the MRS key address code is high, the memory controller 1910 activates and outputs the mode register setting enable/disable signal ID. In this embodiment, if the third bank address BA2 of the command address signal CA (that is, the MRS command) is high, the memory devices 1930M1 to 1930M9 can be set to refresh mode or deep power-down mode according to address codes A0 to A12 . The MRS command can define multiple operating modes, as shown in FIG. 8B. For example, if the third bank address BA2 is low, the second bank address BA1 is saved so that it can be used later (RFU). If the first bank address BA0 is low, the mode register set (MRS) cycle is selected.

If the first bank address BA0 is high, the Extended Mode Register Set (EMRS) cycle is selected. In the MRS loop, address codes A9 to A12 are saved so that they can be used later (RFU), and address code A8 controls a delay locked loop (DLL) reset instruction. Address code A7 can control the test command TM, address codes A4 to A6 can control the CAS latency command, address code A3 can control the burst type BT command, and address codes A0 to A3 can control the burst length command.

As described above, the memory devices 1930M1 to 1930M9 of the memory system 1900 shown in FIG. 25 can respectively perform a refresh operation and a deep power-down operation in response to a predetermined command address signal CA. That is, in response to the same command address signal CA, the memory devices 1930M1 to 1930M9 can perform different operations. Each mode register setting enable/disable signal ID1 to ID9 can be input to one of the data pin, data mask pin and data strobe pin corresponding to one of the memory devices 1930M1 to 1930M9, as implemented in FIG. 8A example shown.

FIG. 26 is a block diagram of a memory system 2100 according to yet another embodiment of the present invention. Referring to FIG. 26, a memory system 2100 includes a first memory device M1 and a second memory device M2. In response to the command address signal CA, the first memory device M1 and the second memory device M2 can perform different operations. In more detail, in the first mode, the first memory device M1 may be set to an operation mode different from that of the second memory device M2 in response to the chip selection signal CS1 or CS2 and the predetermined command address signal CA.

The memory system 2100 further includes a memory controller 2110 for controlling operations of the first and second memory devices MI and M2 using a clock signal CK and a command address signal CA, and generating chip select signals CS1 and CS2. Similar to the memory devices 1930M1 to 1930M9 of the memory module 1920 shown in FIG. 25, in the memory system 2100 shown in FIG. 26, the first and second memory devices M1 and M2 are respectively set to different operating mode.

Typically, mobile devices include memory chips rather than memory modules. The memory system 2100 shown in FIG. 26 is an example of applying the technical concept of the present invention to a mobile device. Here, chip select signals CS1 and CS2 are used instead of the mode register setting enable/disable signal ID as shown in FIG. 25 . In the first mode, if the chip select signals CS1 and CS2 are activated, the first and second memory devices M1 and M2 are set to corresponding operation modes in response to the command address signal CA. If the chip select signals CS1 and CS2 are deactivated, the first and second memory devices M1 and M2 do not respond to the command address signal CA.

To describe in more detail, in the first mode, if the chip select signal CS1 is activated, the first memory device M1 is set in the refresh mode in response to the command address signal CA. At this time, if the chip select signal CS2 remains disabled. Also, in the command address signal CA, as described above, the third bank address BA2 is high, and the address codes A0 to A12 store information for controlling the refresh operation of the first memory device M1.

If the chip select signal CS1 is deactivated and the chip select signal CS2 applied to the second memory device M2 is activated, the second memory device M2 is set in a deep power down mode in response to the command address signal CA. Thus, since in the first mode, the operation modes of the first memory device M1 and the second memory device M2 are set to be different from each other, in the normal operation mode, in response to the same command address signal CA, the first and second Memory devices M1 and M2 are capable of performing different operations.

Therefore, it is possible to reduce power consumption by setting a memory device storing data that should be saved to a refresh mode, and setting a memory device storing data that can be erased to a deep power down mode. The first memory device M1 and the second memory device M2 directly receive the clock signal CK and the command address signal CA from the memory controller 2110 . However, the structure of the memory system in which the memory device operates in different operation modes in response to the command address signal CA is obvious to those skilled in the art, and is not limited by the memory system 2100 shown in FIG. 26 .

FIG. 27 is a block diagram of a memory system 2200 according to yet another embodiment of the present invention. In the memory system 2200, the first memory device M1 receives the clock signal CK and the command address signal CA directly from the memory controller 2210, and the second memory device M2 receives the clock signal CK and the command address signal CA through the first memory device M1. The memory system 2200 operates in the same manner as the memory system 2100 shown in FIG. 26, and thus, a detailed description thereof is omitted.

FIG. 28 is a block diagram of a memory system 2300 according to yet another embodiment of the present invention. The memory system 2300 is a case where the technical concept of the present invention described with reference to FIGS. 19 to 22 is applied to a plurality of memory modules. The memory system 2300 includes first memory modules MM11 and MM12, and second memory modules MM21 and MM22, where each memory module includes a plurality of memory devices.

In a normal operation mode, the first and second memory modules MM11, MM12, MM21, and MM22 can perform different operations in response to the command address signal CA. In response to activation of the first chip select signal CS1, the first memory modules MM11 and MM12 are set to a refresh mode according to the command address signal CA. At this time, the second chip select signal CS2 remains inactive.

Also, in the command address signal CA, as described above, the third bank address BA2 is high, and address codes A0 to A12 store information for controlling refresh operations of the first memory modules MM11 and MM12. Thereafter, if the first chip selection signal CS1 is inactive and the second chip selection signal CS2 applied to the second memory modules MM21 and MM22 is active, the second memory modules MM21 and MM22 are activated in response to the command address signal CA. Set to deep power down mode.

Thus, if the operation mode of the first memory modules MM11 and MM12 in the first mode is set to be different from the operation mode of the second memory modules MM21 and MM22, in the normal operation mode, in response to the same command address signal CA, the first The memory modules MM11 and MM12 perform operations different from the second memory modules MM21 and MM22.

Therefore, it is possible to reduce power consumption by setting a memory block storing data that should be saved to a refresh mode, and setting a memory block storing data that can be erased to a deep power down mode.

The memory system 2300 shown in FIG. 28 operates in the same manner as the memory systems 1900, 2100, and 2200 shown in FIGS. 25 to 27, and thus, a detailed description thereof is omitted.

Claims (77)

1, a kind of accumulator system comprises:

Instruction/address bus with a plurality of instruction/address lines;

First integrated circuit memory devices, it comprises the instruction/address pin of more than first on the instruction/address lines that is coupled to instruction/address bus, first mode register is configured to the information of the operation characteristic of area definition first memory device, and first the instruction decoder mode register that is configured to receive the enable signal response that first predetermined pins with first integrated circuit memory devices receives instruction is set, and the mode register of the inhibit signal response of refusal and the reception of first predetermined pins is provided with instruction, so that when first predetermined pins during the mode register setting operation received enable signal, the information that mode register is provided with instruction was stored in first mode register;

Second integrated circuit memory devices, it comprises the instruction/address pin of more than second on the instruction/address lines that is coupled to instruction/address bus, second mode register is configured to the information of the operation characteristic of area definition second memory device, and second the instruction decoder mode register that is configured to receive the enable signal response that second predetermined pins with second integrated circuit memory devices receives instruction is set, and the mode register of the inhibit signal response of refusal and the reception of second predetermined pins is provided with instruction, so that when second predetermined pins during the mode register setting operation received enable signal, the information that mode register is provided with instruction can be stored in second mode register; And

Be coupled to instruction/address bus Memory Controller, wherein during the first mode register setting operation, described Memory Controller is configured to by instruction/address bus, transmit the first mode register setting and instruct more than first and second instruction/address pin of first and second integrated circuit memory devices, described Memory Controller is further configured to during the first mode register setting operation, transmit first predetermined pins of first enable signal, and transmit second predetermined pins of first inhibit signal to second integrated circuit memory devices to first integrated circuit memory devices.

2, accumulator system according to claim 1, wherein during the first mode register setting operation, the information that first mode register is provided with instruction is written in first mode register, rather than during the first mode register setting operation, the information that first mode register is provided with instruction is written in second mode register.

3, accumulator system according to claim 2, wherein during the second mode register setting operation, described Memory Controller further is configured to by instruction/address bus, transmitting the second mode register setting instructs on more than first and second instruction/address pin of first and second integrated circuit memory devices, during the second mode register setting operation, described Memory Controller further is configured to transmit first predetermined pins of second inhibit signal to first integrated circuit memory devices, and transmit second predetermined pins of second enable signal to second integrated circuit memory devices, wherein during the second mode register setting operation, the information that second mode register is provided with instruction is written into second mode register, rather than during the second mode register setting operation, the information that second mode register is provided with instruction is written to the operation of first mode register.

4, accumulator system according to claim 1 further comprises:

The first data input/output bus, it comprises more than first the data I/O circuit that is coupling between described Memory Controller and described first integrated circuit memory devices, wherein during write operation, described Memory Controller is configured to provide first data-signal of the first memory cell array that is written to described first integrated circuit memory devices by the first data input/output bus; And

The second data input/output bus, it comprises more than second the data I/O circuit that is coupling between described Memory Controller and described second integrated circuit memory devices, wherein during write operation, described Memory Controller is configured to provide second data-signal of the second memory cell array that is written to described second integrated circuit memory devices by the second data input/output bus.

5, accumulator system according to claim 4, wherein said first integrated circuit memory devices comprises more than first the data I/O pin that is coupled to more than first data I/O circuit, wherein said second integrated circuit memory devices comprises more than second the data I/O pin that is coupled to more than second data I/O circuit, wherein said first predetermined pins comprises in more than first the data I/O pin, and wherein said second predetermined pins comprises one in more than second the data I/O pin.

6, accumulator system according to claim 1, wherein in read and write operating period, described first and second predetermined pins are inoperative.

7, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices comprise the first and second data strobe pins separately, the first and second data input/output (i/o) buffers separately, and first and second memory cell arrays separately, wherein during write operation, respond the data strobe signal that the described first and second data strobe pins separately receive, the first and second data input/output (i/o) buffers are configured to data are write in separately first and second memory cell arrays, and wherein first and second predetermined pins comprise the first and second data strobe pins separately.

8, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices comprise the first and second data mask pins separately, the first and second data input/output (i/o) buffers separately, and first and second memory cell arrays separately, wherein the first data input/output (i/o) buffer is configured to during write operation the stand-by shielded signal that the response first data mask pin receives data is write in the first memory cell array, and the activation shielded signal that the response first data mask pin receives during write operation is forbidden writing data in the first memory cell array, wherein the second data input/output (i/o) buffer is configured to during write operation the stand-by shielded signal that the response second data mask pin receives data is write in the second memory cell array, and the activation shielded signal that the response second data mask pin receives during write operation forbids writing data in the second memory cell array, and wherein first and second predetermined pins comprise the first and second data mask pins separately.

9, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices comprise that separately the first and second data input/output (i/o) buffers, first and second memory cell arrays separately and first and second internal clock signal generators separately are configured to clock signal of system generation first and second internal clock signals separately that the response storage controller produces

Wherein respond described internal clock signal separately, described first and second data input/output (i/o) buffers control read and write, first internal clock signal generator is further configured to responding the information of first mode register, adjust the timing of first internal clock signal relevant with system clock, and second internal clock signal generator be further configured to responding the information of second mode register, adjust the timing of second internal clock signal relevant with system clock.

10, accumulator system according to claim 1, wherein said first and second integrated circuit (IC) apparatus comprise more than first and second data I/O pin separately, first and second memory cell arrays separately, and be coupling in separately more than first and second data I/O pin and the first and second data input/output (i/o) buffers separately between first and second memory cell arrays separately, wherein first input/output (i/o) buffer is configured to during read operation, data are read more than first data I/O pin from the first memory cell array, wherein second input/output (i/o) buffer is configured to during read operation, data are read more than second data I/O pin from the second memory cell array, wherein first input/output (i/o) buffer comprises more than first output driver that is coupled to one of more than first correspondence in the data I/O pin, and wherein more than first output driver information of being configured to respond first mode register is adjusted its intensity, and wherein second input/output (i/o) buffer comprises more than second output driver that is coupled to one of more than second correspondence in the data I/O pin, and wherein more than second output driver information of being configured to respond second mode register is adjusted its intensity.

11, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are coupled in proper order along instruction/address bus.

12, accumulator system according to claim 11, wherein said instruction/address bus is from intersecting.

13, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are coupling between Memory Controller and the terminating circuit in proper order along instruction/address bus.

14, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are along instruction/address bus and parallel coupling, this instruction/address bus have between first and second integrated circuit memory devices, be provided, be used to instruct/supply of address bus.

15, accumulator system according to claim 1, wherein said first integrated circuit memory devices is along instruction/address bus, be coupling between the Memory Controller and first terminating circuit, and wherein said second integrated circuit memory devices is coupling between the Memory Controller and second terminating circuit along instruction/address bus.

16, accumulator system according to claim 1 further comprises:

Register, it is configured to instruction/address bus that the reception memorizer controller comes and carries, and this register comprises the impact damper of the instruction/address lines that is configured to drive described instruction/address bus.

17, accumulator system according to claim 16, wherein said register further is configured to receive data-signal from the Memory Controller of first and second integrated circuit (IC) apparatus, and register comprises the data buffer of the data-signal that is configured to drive first and second integrated circuit (IC) apparatus.

18, accumulator system according to claim 1 further comprises:

Be coupled to the system clock circuit of first and second integrated circuit (IC) apparatus; And

Be coupling in the phase-locked loop circuit between the clock signal of system output of system clock circuit and Memory Controller.

19, a kind of method of control store module, this memory module comprise a plurality of storage arrangements that are coupled to Memory Controller by identical instruction/address bus, and this method comprises:

During the mode register setting operation, by instruction/address bus, to each integrated circuit memory devices, the register that supplies a pattern is provided with instruction from Memory Controller;

Between the Memory Controller and first integrated circuit memory devices, pass through signal line, one of from the Memory Controller to the integrated circuit memory devices first, inhibit signal is provided, therefore during the mode register setting operation, forbid that the mode register of first integrated circuit memory devices is provided with the execution of instruction; And

Between the Memory Controller and second integrated circuit memory devices, pass through signal line, one of from the Memory Controller to the integrated circuit memory devices second, enable signal is provided, therefore during the mode register setting operation, the mode register that enables second integrated circuit memory devices is provided with the execution of instruction, wherein said inhibit signal is during the mode register setting operation, do not offer second integrated circuit memory devices, and wherein said enable signal does not offer first integrated circuit memory devices during the mode register setting operation.

20, method according to claim 19 further comprises:

During the second mode register setting operation,, to each integrated circuit memory devices, provide second mode register that instruction is set from Memory Controller by instruction/address bus;

Between the Memory Controller and first integrated circuit memory devices, pass through signal line, from Memory Controller to first integrated circuit memory devices, second enable signal is provided, therefore during the second mode register setting operation, second mode register that enables first integrated circuit memory devices is provided with the execution of instruction; And

Between the Memory Controller and second integrated circuit memory devices, pass through signal line, from Memory Controller to second integrated circuit memory devices, inhibit signal is provided, therefore during the second mode register setting operation, forbid that second mode register of second integrated circuit memory devices is provided with the execution of instruction, wherein said second enable signal is during the second mode register setting operation, do not offer second integrated circuit memory devices, and wherein said second inhibit signal does not offer first integrated circuit memory devices during the second mode register setting operation.

21, method according to claim 19, wherein said first integrated circuit memory devices comprises first mode register, and described second integrated circuit memory devices comprises second mode register, this method further comprises:

During the mode register setting operation, to the corresponding information of instruction be set with first mode register writes in second mode register of second integrated circuit memory devices, rather than during the mode register setting operation, will the corresponding information of instruction be set with mode register and write in first mode register.

22, method according to claim 19 further comprises:

During write operation,, first data-signal that write is offered the first memory cell array of first integrated circuit memory devices by the first data input/output bus; And

During write operation,, second data-signal that write is offered the second memory cell array of second integrated circuit memory devices by the second data input/output bus.

23, method according to claim 22, wherein said first data-signal is provided for more than first data I/O pin of first integrated circuit memory devices, wherein said second data-signal is provided for more than second data I/O pin of second integrated circuit memory devices, wherein said inhibit signal is provided in more than first the data I/O pin, and wherein said enable signal is provided for one in more than second the data I/O pin.

24, method according to claim 19, wherein said inhibit signal is provided for first predetermined pins of first integrated circuit memory devices, wherein said enable signal is provided for second predetermined pins of second integrated circuit memory devices, and wherein in read and write operating period, first and second predetermined pins are inoperative.

25, method according to claim 19, wherein said first and second integrated circuit memory devices comprise separately the first and second data strobe pins and first and second memory cell arrays separately, this method further comprises:

When first and second memory cell arrays that write data into separately, during write operation, provide data strobe signal to arrive separately the first and second data strobe pins, wherein said forbidding is provided for the first and second data strobe pins with enable signal.

26, method according to claim 19, wherein said first and second integrated circuit memory devices comprise first and second data mask pin and the memory cell arrays separately, and this method further comprises:

During first write operation, stand-by shielded signal is offered the first data mask pin, during first write operation, to enable to write data in the first memory cell array;

During second write operation, the shielded signal that activates is offered the first data mask pin, during second write operation, to forbid writing data in the first memory cell array;

During first write operation, the shielded signal that activates is offered the second data mask pin, during first write operation, to forbid writing data to the second memory cell array; And

During second write operation, stand-by shielded signal is offered the second data mask pin, during second write operation, to enable to write data to the second memory cell array;

Wherein will forbid offering the first and second data mask pins with enable signal.

27, method according to claim 19 further comprises:

Provide clock signal of system to first and second integrated circuit (IC) apparatus, responding system clock signal wherein, first integrated circuit memory devices produces first internal clock signal, responding system clock signal wherein, second integrated circuit memory devices produces second internal clock signal, and wherein the response modes register is provided with instruction, with respect to clock signal of system, adjusts the timing of second internal clock signal.

28, method according to claim 19 further comprises:

During read operation, by more than first output driver and more than first data I/O pin, from the first memory cell array reception data of first integrated circuit memory devices; And

During read operation, by more than second output driver and more than second data I/O pin, from the second memory cell array reception data of second integrated circuit memory devices; And

Wherein the response modes register is provided with instruction, adjusts the intensity of more than second output driver.

29, a kind of integrated circuit memory devices comprises:

Memory cell array;

Mode register is configured to store the operation characteristic information of define storage device of being used for;

Instruction decoder, be configured to during preference pattern register setting operation, the enable signal that receives on the predetermined pins of response integrated circuit memory devices, receive the preference pattern register instruction is set, and the inhibit signal that receives on the predetermined pins of response integrated circuit memory devices, refusal preference pattern register is provided with instruction, so that during preference pattern register setting operation, when the scheduled pin of enable signal received, the information that the preference pattern register is provided with instruction was stored in mode register; And

The data input/output (i/o) buffer is configured to according to the defined operation characteristic of the information of mode register stored, and during write operation, control writes data to memory cell array, and during read operation, sense data from memory cell array.

30, integrated circuit memory devices according to claim 29, wherein during the mode register setting operation, when the scheduled pin of inhibit signal received, the information that described preference pattern register is provided with instruction was not stored in the mode register.

31, integrated circuit memory devices according to claim 29 further comprises:

The data mask pin, wherein said data input/output (i/o) buffer is configured to during write operation, the stand-by shielded signal that response data shielding pin receives, write data in the memory cell array, and during the write operation, the shielded signal of the activation that response data shielding pin receives is forbidden writing data in the memory cell array, and wherein said predetermined pins comprises the data mask pin.

32, integrated circuit memory devices according to claim 29 further comprises:

A plurality of data I/O pins, wherein said data input/output (i/o) buffer is configured to during write operation, write data to memory cell array from data I/O pin, and during read operation, to data I/O pin, wherein said predetermined pins comprises in the data I/O pin from the memory cell array read data.

33, integrated circuit memory devices according to claim 29, wherein predetermined pins is inoperative in read and write operating period.

34, integrated circuit memory devices according to claim 29 further comprises:

The data strobe pin, wherein said data input/output (i/o) buffer is configured to during write operation, and the data strobe signal that the response data strobe pin receives write data in the memory cell array, and wherein said predetermined pins comprises the data strobe pin.

35, integrated circuit memory devices according to claim 29 further comprises:

Internal clock signal generator, the clock signal of system that its clock input that is configured to respond integrated circuit memory devices receives, produce internal clock signal, wherein said data input/output (i/o) buffer response internal clock signal, control writes and reads, this internal clock generator is further configured the information that instruction is set for the preference pattern register of response modes register-stored, with respect to clock signal of system, adjusts the timing of internal clock signal.

36, integrated circuit memory devices according to claim 29 further comprises:

A plurality of data I/O pins, wherein said data input/output (i/o) buffer is configured to during read operation, from the memory cell array reading of data to data I/O pin, wherein said data input/output (i/o) buffer comprises a plurality of output drivers, and each described output driver is coupled in the data I/O pin separately one, and the information that the wherein said output driver preference pattern register that is configured to the response modes register-stored is provided with instruction is adjusted its intensity.

37, a kind of method of operating integrated circuit memory devices, this method comprises:

During the first preference pattern register setting operation, the predetermined pins of response integrated circuit memory devices enable signal that receive, that have first logical value, receive the first preference pattern register instruction is set, consequently the corresponding information of instruction is set and is stored in the mode register with the first preference pattern register;

During the second preference pattern register setting operation, inhibit signal that receive, that have second logical value on the predetermined pins of response integrated circuit memory devices, refuse the second preference pattern register instruction is set, so that with the second preference pattern register the corresponding information of instruction is set and is not stored in the mode register, wherein first and second logical values are opposite logical values; And

According to the defined operation characteristic of mode register canned data, during write operation, control write data in the memory cell array of integrated circuit memory devices, with and/or during read operation, from the memory cell array sense data.

38, according to the described method of claim 37, wherein said predetermined pins comprises the data mask pin, and this method further comprises:

During first write operation, the shielded signal of the activation that response data shielding pin receives is forbidden writing in the memory cell array; And

During second write operation, the stand-by shielded signal that response data shielding pin receives enables to write in the memory cell array.

39, according to the described method of claim 37, wherein said predetermined pins comprises data I/O pin, and this method further comprises:

During write operation, write data to the memory cell array from data I/O pin; And

During read operation, from the memory cell array read data to data I/O pin.

40, according to the described method of claim 37, wherein said predetermined pins is inoperative in read and write operating period.

41, according to the described method of claim 37, wherein said predetermined pins comprises the data strobe pin, and this method further comprises:

During write operation, the data strobe signal that the response data strobe pin receives writes data in the memory cell array.

42, according to the described method of claim 37, further comprise:

The clock signal of system that the clock input of response integrated circuit memory devices is received produces internal clock signal, and wherein the data control that writes and/or read comprises the response internal clock signal, writes and/or sense data; And

The information of response modes register-stored with respect to clock signal of system, is adjusted the timing of internal clock signal.

43, according to the described method of claim 37, further comprise:

During read operation, pass through output driver, the output pin of data separately from the memory cell array reading of data to integrated circuit memory devices, wherein the output driver preference pattern register that is configured to the response modes register-stored information that instruction is set is adjusted its intensity.

44, a kind of operation comprises the method for the memory module of a plurality of integrated circuit memory devices, wherein said a plurality of storage arrangement is by same instruction/address bus, be coupled to Memory Controller, and wherein said a plurality of storage arrangement passes through data input/output bus separately, independently be coupled to Memory Controller, this method comprises:

Utilization is coupling in the first data input/output bus between Memory Controller and first memory device, and first the mode register of one of storage arrangement is set, and defines the operation characteristic of first memory device thus;

Utilization is coupling in the second data input/output bus between Memory Controller and second memory device, and second the mode register of one of storage arrangement is set, and defines the operation characteristic of second memory device thus;

By the first data input/output bus, write first data-signal in the memory cell array of first memory device; And

By the second data input/output bus, write second data-signal in the memory cell array of second memory device.

45, a kind of integrated circuit memory devices comprises:

Memory cell array;

A plurality of data I/O pins, it is configured to during data write operation, reception will be written to data the memory cell array from Memory Controller, this data I/O pin further is configured to provide data to Memory Controller from memory cell array during data read operation; And

Mode register, it is configured to store the information of operation characteristic of define storage device of being used for, and wherein said mode register is configured to utilize the data input/output bus to be provided with.

46, a kind of method of operational store module, this memory module comprise a plurality of storage arrangements that are coupled to Memory Controller by identical instruction/address bus, and this method comprises:

During the mode register setting operation,, instruction is set from Memory Controller receiving mode register at each integrated circuit memory devices by instruction/address bus;

By the signal line between the Memory Controller and first integrated circuit memory devices, receive inhibit signal from first the Memory Controller of one of integrated circuit memory devices, during the mode register setting operation, forbid that the mode register of first integrated circuit memory devices is provided with the execution of instruction thus; And

By the signal line between the Memory Controller and second integrated circuit memory devices, receive enable signal from second the Memory Controller of one of integrated circuit memory devices, thus during the mode register setting operation, the mode register that enables second integrated circuit memory devices is provided with the execution of instruction, wherein during the mode register setting operation, second integrated circuit memory devices does not receive inhibit signal, and wherein during the mode register setting operation, first integrated circuit memory devices does not receive enable signal.

47, according to the described method of claim 46, further comprise:

During the second mode register setting operation,, receive second mode register from the Memory Controller of each integrated circuit memory devices instruction is set by instruction/address bus;

By the signal line between the Memory Controller and first integrated circuit memory devices, receive second enable signal from the Memory Controller of first integrated circuit memory devices, during the second mode register setting operation, second mode register that enables first integrated circuit memory devices is provided with the execution of instruction thus; And

By the signal line between the Memory Controller and second integrated circuit memory devices, receive inhibit signal from the storage control of second integrated circuit memory devices, thus during the second mode register setting operation, forbid that second mode register of second integrated circuit memory devices is provided with the execution of instruction, wherein during the second mode register setting operation, second integrated circuit memory devices does not receive second enable signal, and wherein during the second mode register setting operation, first integrated circuit memory devices does not receive second inhibit signal.

48, according to the described method of claim 46, wherein said first integrated circuit memory devices comprises first mode register, and described second integrated circuit memory devices comprises second mode register, and this method further comprises:

During the mode register setting operation, to the corresponding information of instruction be set with first mode register is written in second mode register of second integrated circuit memory devices, rather than during the mode register setting operation, will the corresponding information of instruction be set with mode register and be written in first mode register.

49, according to the described method of claim 46, further comprise:

During write operation, by the first data input/output bus, reception will be written to first data-signal of the first memory cell array of first integrated circuit memory devices; And

During write operation, by the second data input/output bus, reception will be written to second data-signal in the second memory cell array of second integrated circuit memory devices.

50, according to the described method of claim 49, wherein said first data-signal is received by more than first data I/O pin of first integrated circuit memory devices, wherein said second data-signal is received by more than second data I/O pin of second integrated circuit memory devices, wherein said inhibit signal is by a reception in more than first the data I/O pin, and wherein said enable signal is by a reception in more than second the data I/O pin.

51, according to the described method of claim 46, wherein said inhibit signal is received by first predetermined pins of first integrated circuit memory devices, wherein said enable signal is received by second predetermined pins of second integrated circuit memory devices, and wherein first and second predetermined pins are inoperative in read and write operating period.

52, according to the described method of claim 46, wherein said first and second integrated circuit memory devices comprise separately the first and second data strobe pins and first and second memory cell arrays separately, this method further comprises:

During write operation, the data strobe signal that the response first and first data strobe pin separately receives writes data in first and second memory cell arrays separately, and wherein said forbidding received by the first and second data strobe pins with enable signal.

53, according to the described method of claim 46, wherein said first and first integrated circuit memory devices comprises first and second data mask pin and the memory cell arrays separately, and this method further comprises:

During first write operation, respond the stand-by shielded signal that the first data mask pin receives, enable to write data in the first memory cell array;

During second write operation, respond the shielded signal of the activation of first data mask pin reception, forbid writing data in the first memory cell array;

During first write operation, respond the stand-by shielded signal that the second data mask pin receives, forbid writing data in the second memory cell array; And

During second write operation, respond the shielded signal of the activation of second data mask pin reception, enable to write data in the second memory cell array;

Wherein forbid being received by the first and second data mask pins with enable signal.

54, according to the described method of claim 46, further comprise:

Provide clock signal of system to first and second integrated circuit (IC) apparatus;

Respond described clock signal of system, produce first internal clock signal at the first integrated circuit memory devices place;

Respond described clock signal of system, produce second internal clock signal at the second integrated circuit memory devices place;

Respond described mode register instruction is set,, adjust the timing of second internal clock signal with respect to clock signal of system.

55, according to the described method of claim 46, further comprise:

During read operation,, provide data to more than first data I/O pin from the first memory cell array of first integrated circuit memory devices by more than first output driver;

During read operation,, provide data to more than second data I/O pin from the second memory cell array of second integrated circuit memory devices by more than second output driver; And

Respond described mode register instruction is set, adjust the intensity of more than second output driver.

56, a kind of accumulator system comprises:

Memory module, it comprises a plurality of storage arrangements; And

Memory Controller, it utilizes clock signal and instruction address signal, and produce identification signal and be used for one corresponding operation of independent control store apparatus,

Wherein, in first pattern, the response identification signal, the operator scheme of storage arrangement is configured to different each other according to the instruction address signal, and

In second pattern, response predetermined instruction address signal, in the set operator scheme of first pattern, storage arrangement is correspondingly operated.

57, according to the described accumulator system of claim 56, if wherein identification signal activates, then described storage arrangement is set to described operator scheme respectively according to the instruction address signal, and, if identification signal is stopped using, then described storage arrangement does not respond described instruction address signal.

58, according to the described accumulator system of claim 56, if wherein identification signal is activated, then respond described instruction address signal, the part of described storage arrangement is configured to refresh mode, and other parts of described a plurality of storage arrangements are configured to degree of depth power-down mode.

59, according to the described accumulator system of claim 58, wherein the instruction address signal is the MRS instruction, be that mode register is provided with instruction, wherein the MRS instruction is provided with a kind of pattern, if wherein the 3rd bank-address in three of MRS key address code bank-address is low, then Memory Controller does not produce identification signal, and the MRS instruction is provided with a kind of pattern, if wherein the 3rd bank-address in three of MRS key address code bank-address is high, then Memory Controller produces described identification signal.

60,, wherein described identification signal is input in data pin, data mask pin and the data strobe pin of corresponding stored device according to the described accumulator system of claim 56.

61, according to the described accumulator system of claim 56, wherein first pattern is a kind of pattern, be used for before the storage arrangement normal running operator scheme of storage arrangement being set, and second pattern is a kind of pattern that is used for the normal running storage arrangement.

62, a kind of accumulator system comprises first memory device and second memory device, and wherein first and second storage arrangements are in normal manipulation mode, and the response instruction address signal is carried out different operations.

63, according to the accumulator system of claim 62, wherein, in first pattern, respond chip select signal and predetermined instruction address signal, the operator scheme of described first memory device is configured to be different from the operator scheme of described second memory device.

64, according to the described accumulator system of claim 63, wherein, in first pattern, if chip select signal activates, response instruction address signal then, described first and second storage arrangements are set to corresponding operator scheme respectively, and, if chip select signal is stopped using, then described first and second storage arrangements are the response instruction address signal not.

65, according to the described accumulator system of claim 63, if wherein chip select signal activates, response instruction address signal then, described first memory device is configured to refresh mode, and described second memory device is configured to degree of depth power-down mode.

66, according to the described accumulator system of claim 63, wherein the instruction address signal is the MRS instruction, be that mode register is provided with instruction, wherein the MRS instruction is provided with a kind of pattern, if wherein the 3rd bank-address in three of MRS key address code bank-address is low, then described Memory Controller does not produce identification signal, and the MRS instruction is provided with a kind of pattern, if wherein the 3rd bank-address in three of MRS key address code bank-address is high, then described Memory Controller produces identification signal.

67, according to the described accumulator system of claim 63, wherein said first pattern is a kind of pattern, is used for before the first and second storage arrangement normal runnings operator scheme of first and second storage arrangements being set.

68, according to the described accumulator system of claim 62, further comprise Memory Controller, be used to utilize clock signal and instruction address signal, control the operation of first and second storage arrangements, and produce chip select signal.

69, according to the described accumulator system of claim 68, wherein said first memory device is directly from Memory Controller receive clock signal and instruction address signal, and described second memory device is by the first memory device, receive clock signal and instruction address signal.

70, according to the described accumulator system of claim 68, wherein said first and second storage arrangements are directly from Memory Controller receive clock signal and instruction address signal.

71, a kind of accumulator system comprises a plurality of first memory modules and a plurality of second memory module, and each first and second memory module comprises a plurality of storage arrangements, wherein

In normal manipulation mode, the response instruction address signal, the first memory module is carried out the operation that is different from the second memory module.

72, according to the described accumulator system of claim 71, wherein, in first pattern, response chip select signal and predetermined instruction address signal, the operator scheme of first memory module is configured to be different from the operator scheme of second memory module.

73, according to the described accumulator system of claim 72, wherein, in first pattern, if chip select signal activates, response instruction address signal then, described first and second memory modules are set to corresponding operator scheme, and, if chip select signal is stopped using, described first and second memory modules are the response instruction address signal not.

74, according to the described accumulator system of claim 72, wherein, in first pattern, if chip select signal activates, the response instruction address signal, described first memory module is configured to refresh mode, and described second memory module is configured to degree of depth power-down mode.

75, according to the described accumulator system of claim 74, wherein the instruction address signal is the MRS instruction, be that mode register is provided with instruction, a kind of pattern wherein is set, if wherein the 3rd bank-address in three of MRS key address code bank-address is low, then described Memory Controller does not produce identification signal, and the MRS instruction is provided with a kind of pattern, if wherein the 3rd bank-address in three of MRS key address code bank-address is high, then described Memory Controller produces identification signal.

76, according to the described accumulator system of claim 74, wherein said first pattern is a kind of pattern, is used for before the first and second memory module normal runnings operator scheme of first and second memory modules being set.

77, according to the described accumulator system of claim 71, further comprise Memory Controller, be used to utilize clock signal and instruction address signal, control the operation of first and second memory modules, and produce chip select signal.

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