CN1713678A - Apparatus for convolutional interleaving and canceling interleave in asymmetric user line - Google Patents

Abstract

The invention discloses a device for realizing convolutional interleaving and deinterleaving in an asymmetrical digital subscriber line (ADSL), which includes a storage control circuit and a storage unit, first byte indication, input data, input data refresh indication, clock and other signals input storage control circuit; there are signals such as address, write data, and read-write control between it and the storage unit, and the storage unit outputs data signals and data refresh indication signals; the storage control circuit includes an address generation device, and the control circuit refreshes instructions according to the input data When interleaving, first write one byte, and then read one byte; when deinterleaving, first read one byte, and then write one byte; the address generating device controls the write and read address generation, and realizes writing and reading the first byte in a sequential manner. One codeword, write and read the remaining codewords in a convolutional fashion. The invention realizes the convolution interleaving and deinterleaving of the ADSL channel by hardware, the read-write address is directly generated by the hardware, the convolution process is simple, no table look-up is required, and the cost is low.

Description

A Realization Device of Convolutional Interleaving and Deinterleaving in Asymmetric Digital Subscriber Line

technical field

The invention is mainly used in the field of broadband access, and in particular relates to a processing device for "burst block errors" of an asymmetrical digital subscriber line (ADSL).

Background technique

The ADSL system can simultaneously transmit POTS (telephone service) or ISDN (integrated digital network service) and broadband data service on a pair of twisted pairs. The entire frequency band is divided into 256 DMT (discrete multi-tone) sub-channels at intervals of 4.3125Khz ( The ADSL+ protocol is divided into 512 DMT sub-channels).

The working environment of the twisted pair is relatively harsh, and it is susceptible to lightning or other interferences, resulting in transient spike signals. This spike signal can cause errors on the ADSL channel. If the channel introduces interleaving/deinterleaving links, the error correction capability will be enhanced. By interleaving the sequence of the data to be transmitted at the transmitter, the demodulated time slot output after reception is recombined through a reverse deinterleaving process to make it a sequence of the original order, so that the phase The adjacent burst errors are scattered to the range that the error correction decoding can correct. For example, for an ADSL downlink, the interleaving is completed in the computer room of the telecommunications department, the data is transmitted through the telephone line, and then the deinterleaving is completed at the user's home.

The software implementation method of interleaving and deinterleaving usually uses DSP devices. DSP uses the internal memory of the chip to complete the interleaving writing process, reading process, and deinterleaving writing process according to the ADSL symbol period according to the structure of the RS (Reed-Solomon) code word. process, reading process. The RS code word has a maximum of 255 bytes, and if a software method is used to realize N*D=255*128 interleaving and deinterleaving, 2*8*255*128=52.224kbits memory is required.

The software implementation method of interleaving and de-interleaving has some disadvantages. First, a dedicated DSP is necessary. Due to the increasing popularity of ADSL wired broadband access, the cost requirements are getting lower and lower. However, the DSP device or core technology is very complicated, and it is generally provided by a dedicated manufacturer. R&D and use costs are high, because the use of DSP devices in ADSL severely restricts the further reduction of the cost of ADSL chip products.

At the same time, the software method realizes interleaving and deinterleaving, which not only occupies memory resources, but also occupies the resources of the DSP itself. Since the ADSL connection has been established to send and receive data, the memory space used for interleaving and deinterleaving cannot be released. It has been used for interleaving and deinterleaving, and the resources used by DSP are limited. If it is frequently used for scheduling interleaving and deinterleaving, the time for processing other tasks is relatively reduced.

Interleaving and deinterleaving are also done using hardware, such as using shift register method, dual-port RAM (static random access memory) method or DRAM (dynamic random access memory) method,

If a shift register is used, each bit requires a D flip-flop. As the number of bytes increases and the interleaving depth increases, a large number of D flip-flops are required. If N=255, D=128 interleaving requires 52.224 K D flip-flops, such a huge D flip-flop is not worth the loss due to interleaving and de-interleaving, which is not conducive to system integration and testing of the chip.

In GA-HDTV (high-definition television), dynamic RAM is used to realize interleaving and deinterleaving. The interleaving delay realized by this method is j (data block label) * 4 * 52, and the delay is fixed, and any byte cannot be realized. D-1 delay, wherein the interleaving depth D=2 ^m , D can be 1, 2, 4, 8, 16, 32, 64, 128. This implementation method has poor flexibility and can only be used in the field of high-definition television, and cannot be used in the occasions of variable bytes and variable interleaving depth in the ADSL field.

In some treatises, the method of interleaving and deinterleaving also has a convolution interleaving method, and the realization of convolution is to determine the address through a look-up table method. This method is complicated to control, cumbersome, and not easy to implement with hardware.

Contents of the invention

The technical problem to be solved by the present invention is to provide a device for implementing convolutional interleaving and deinterleaving in an asymmetric digital subscriber line, which can realize the interleaving of the ADSL downstream channel and the deinterleaving of the ADSL upstream channel by hardware methods, and does not need to look up the table to determine the address .

In order to solve the above technical problems, the present invention provides a device for implementing convolutional interleaving and deinterleaving in an asymmetric digital subscriber line, including a storage control circuit and a storage unit, characterized in that:

The input signal of the storage control circuit includes a first byte indication signal, an input data signal, an input data refresh indication signal and a clock signal; the connection signal between it and the storage unit includes an address signal, a write data signal and a read-write control signal , the storage unit output signal includes an output data signal and an output data refresh indication signal;

The storage control circuit includes an address generating device, and the control circuit is used to write a byte in the storage unit first during interleaving and then read a byte according to the input data refresh instruction; First read a byte in the storage unit, and then write a byte; wherein the address generation device is used to control the generation of write and read addresses during interleaving or deinterleaving, so as to realize writing and reading the first byte in a sequential manner. One codeword, and the remaining codewords are written and read in a convolutional fashion.

Further, the address generation device of the above-mentioned realization device may include an N*D counter, a write row counter and a write column counter that generate a write address by splicing together, and a read row counter and a read column counter that generate a read address by splicing together. The number parameter N and the interleaving depth parameter D are divided into N rows and D columns, where:

The initial value of the N*D counter is 0, the maximum value is the product of N and D, D=2 ^m , when the first byte indication signal is valid, assign the low m bits of the counter as the initial value to the Write column and read column counters, assign the remaining high bits after the m bits are removed from the counters to the write row and read row counters as initial values, and complete the loop plus N, reset when the accumulation reaches the maximum value, and recount;

When the write column counter is interleaved, its output value is determined by the assigned initial value; when deinterleaving, each time a byte is written, the count value is cyclically increased by 1, and after reaching the maximum value D-1, it is reset to 0 and counted again ;

When the write line counter is interleaved, every time a byte is written, the count value is increased by 1, and after reaching the maximum value N-1, it is reset to 0 and counted again; when de-interleaving, each time a line is written, the count value is increased by 1 ;

When the read-column counter is interleaved, every time a byte is read, the count value is increased by 1, and after reaching the maximum value D-1, it is reset to 0 and counted again; when de-interleaving, its output value is determined by the assigned initial value ;

When the read line counter is interleaved, the count value is increased by 1 every time a line is read; when deinterleaving, each time a byte is read, the count value is increased by 1 cyclically, and after reaching the maximum value N-1, it is reset to 0 and counted again .

Further, the above implementing device may have the following features: the values of the write row and read row counters are used as the low bits of the address signal, and the values of the write column and read column counters are used as the high bits of the address signal.

Further, the above-mentioned implementing device may have the following characteristics: the storage unit is implemented with a single-port random access memory (RAM); in order to further facilitate the guarantee of the timing relationship, the connection signal between the storage control circuit and the single-port random access memory may also include a clock signal, and the single-port random access memory is an 8-bit synchronous random access memory with a clock signal.

Further, in order to make the device of the present invention applicable to occasions of variable byte and variable interleaving depth. The byte number parameter N and the interleaving depth parameter D may be provided by signals input to the RAM control circuit.

As can be seen from the above, the device of the present invention can realize the interleaving and deinterleaving of the ADSL channel by a hardware method, directly generate the read-write address of the RAM by the hardware, and the convolution process is simple, without looking up a table, and adopting a single-port RAM to realize can save area and make the control simple. RAM can be easily integrated into the chip to reduce costs. Further, when determining the read-write address, the first byte address of the RS codeword can be obtained from the N*D counter, and the read-write control of the RAM is directly performed by the "bit spelling operation" of the number of bits in the row and column counters. Obtained, do not need complicated control and special consideration; The present invention can also realize the variable (1 to 255) of byte quantity, the convolutional interleaving of variable interleaving depth (1 to 128), the writing and reading of interleaving and the reading and writing of deinterleaving are carried out Real-time operation can realize the delay of j (RS code byte label) * (D-1) of the byte.

Adopting the present invention and cooperating with other ADSL channel data processing, such as scrambling code, RS coding and other hardware implementations, can completely solve the data flow processing of ADSL receiving and transmitting channels, and at the same time have high efficiency and low power consumption.

Description of drawings

FIG. 1 is a circuit diagram of hardware implementation of an interleaving/deinterleaving device according to an embodiment of the present invention.

FIG. 2 shows the writing process of interleaving and the reading process of deinterleaving when N=5 and D=2 according to the embodiment of the present invention.

FIG. 3 shows the reading process of interleaving and the writing process of deinterleaving when N=5 and D=2 according to the embodiment of the present invention.

Detailed ways

The smallest information unit in an ADSL channel is an 8-bit byte, and the information unit for interleaving and deinterleaving is an RS codeword. According to actual needs, generally dozens of bytes (up to 255 bytes) are the smallest interleaving and deinterleaving information. The unit, according to the different interleaving depth D, completes the interleaving and deinterleaving of multiple RS codewords.

As shown in FIG. 1 , the ADSL interleaving device/deinterleaving device of this embodiment is mainly composed of a RAM control circuit 1 and a RAM storage unit 2 .

The signals input to the RAM control circuit 1 include global signals such as the clock signal clk, the reset signal reset, and the enable signal enable; inputs such as the first byte indication signal rsbyte_first, the input data signal rsbyte_input[7:0], and the input data refresh indication signal rsinput_valid Data and control signals; and interleaving and deinterleaving parameter signals such as the byte number signal n[7:0] of the RS codeword and the interleaving depth signal d[6:0].

The RAM control circuit 1 mainly includes an N*D counter 11, a write-row counter 12, a write-column counter 13, a read-row counter 14, and a read-column counter 15. These counters are mainly used to generate write addresses and read addresses of the RAM.

The connection signals between the RAM control circuit 1 and the RAM storage unit 2 include: address signal address[14:0], write data signal wrdata[7:0], read and write control signal write_ctrl, RAM enable control signal ram_en and clock signal clk.

RAM storage unit 2 is a single-port synchronous RAM with an 8-bit clock signal. Synchronous RAM is selected for implementation because the timing relationship is easy to guarantee. The RAM storage unit is based on the actual input parameters n[7:0], d[6:0], Divided into n rows (maximum value 255), d columns (maximum value 128).

Signals output from the RAM storage unit 2 include an output data signal Output_byte[7:0] and an output data refresh signal output_vaild.

The specific implementation scheme of the device in this embodiment will be described below by taking interleaving as an example.

When interleaving a continuous data stream, it is assumed that the number of bytes of RS codewords is N (N=5 in this embodiment), and the interleaving depth is D (D=2 in this embodiment). The interleaving process of N*D bytes is to first write a byte in the RAM storage unit, then read a byte from the RAM storage unit, then write a byte, and then read a byte until N* D bytes are written and read. By controlling the write and read addresses, the order of the bytes is disrupted, so that the bytes of multiple codewords are interleaved together. The beat of writing and reading is controlled by the clock signal clk, while writing or reading is controlled by the signal of the read and write control line.

FIG. 2 shows the second interleaving writing process of this embodiment. The RS codewords RS0 and RS1 labeled "0" and "1" are written in the first interleaving, which respectively contain 10 bytes of B00~B04, B10~B14, and the RS codewords written in the second interleaving The codewords RS2 and RS3 respectively include 10 bytes of B20~B24, B30~B34. FIG. 3 shows the second interleaving reading process of this embodiment, and what is read are multiple groups of N bytes of interleaved data. The following describes how each hardware works:

N*D counter

Since the N and D selected by ADSL may be different each time the link is connected, the number of bits of the interleaving N*D counter must be determined first, and the RAM storage unit is evenly divided into 0 and 1 by controlling the row and column addresses. , 2, 3...N-1 rows and 0, 1, 2, 3...D-1 columns. This embodiment is divided into 5 rows and 2 columns.

The N*D counter is a "byte sum" counter that determines the number of bytes that need to be interleaved. The initial value of the counter is zero, and the maximum value is the product of the actual input parameters N and D. When receiving the first byte indication pulse signal (that is, the RS code word refresh), assign an initial value to each counter according to the table below, and complete the loop plus N. The accumulation process is: N*D counter=N*D counter+N, When reaching the maximum value, reset to 0 and start counting again, and its cycle period is N*D bytes.

Table 1: Counter initial value D[6:0] parameters 0 2 4 64 Write column counter initial value 0 N*D(0) N*D(1:0)  … N*D(5:0) Write row counter initial value N*D(7:0) N*D(8:1) N*D(9:2)  … N*D(13:6) Read column counter initial value 0 N*D(0) N*D(1:0)  … N*D(5:0) Read line counter initial value N*D(7:0) N*D(8:1) N*D(9:2) ... N*D(13:6)

It can be seen from the above table that when D = 2 ^m , when the initial value is assigned, the low m bits of the N*D counter are assigned to the write column counter and the read column counter, and the remaining high bits after the m bits are removed from the counter are used as the initial value assigned to the write row counter and read row counter. In this embodiment D=2, when preparing to write B00～B04, each bit of the N*D counter is 0, and the initial values assigned to the counters for writing rows, writing columns, reading rows, and reading columns are all zero; preparing to write B10～B14 When the value of the N*D counter is 5, the lowest bit "1" is assigned to the write column and read column counters, that is, the initial value is 1, corresponding to the second column, and the 9th to 2nd bits "00000010" are assigned to Write line and read line counters, that is, the initial value is 2, corresponding to the third line. When receiving the next first byte indication pulse signal, the N*D counter reaches the maximum value of 10 and is directly reset to zero.

RAM storage unit read and write control

In the interleaving process, first write a byte when the input data refresh indication signal is valid, then read a byte, and generate an output data refresh pulse indication signal, and continue to cycle like this until an N*D word is completed In the writing and reading process of the section, the address control of the RAM is as follows:

Write address control (interleaved write process)

RAM_address[14:0] = write column counter value bits spell row counter value

Read address control (interleaved read process)

RAM_address[14:0] = read column counter value bit spell read row counter value

Write row counter, write column counter and write mode

The function of the write row counter is to control the write address (lower address) of the RAM, and complete the cycle plus 1 according to the input data refresh instruction signal, that is: write row counter=write row counter+1, and the maximum value is the actual input interleaving parameter n[7 :0], when the count reaches the maximum value N-1, it will be reset to 0.

The write column counter is also used to control the write address (high address) of the RAM. It is directly obtained from the low bits of the N*D counter according to the refresh of the RS code word, that is, it is obtained by assigning an initial value.

Under the control of the data write address by the write row and write column counters, two write modes can be implemented in the interleaved write process: sequential mode write and convolution mode write.

The first RS code word (N bytes) used for interleaving is written in a sequential manner, and the sequential writing process is performed column by column. Please refer to Figure 2. When writing the B00 byte of the first RS codeword, the initial values of the N*D counter, the write row counter, and the write column counter are all zero, so the B00 byte is written to the first row of the first row. Then, the value of the write column counter remains unchanged, and each time a byte is written to the RAM storage unit, the write row counter is incremented by 1, so that the B01, B02, B03, and B04 bytes are respectively written into the first column of the first column. 2. In the third, fourth and fifth rows, after writing N bytes, the write column counter is incremented by 1 according to the first byte indication signal.

Convolution writing is used for the second RS codeword, the third RS codeword, ... until the Dth RS codeword, and the interleaving convolution writing process is also written by column. The initial values of the write row counter and the write column counter are determined by the N*D counter, and the write position of the first byte of each RS codeword is not necessarily the first byte of each column.

Please refer to Figure 2. After writing the B04 byte, the N*D counter adds N according to the first byte of the RS code word, and its value becomes 5. As mentioned above, after assigning the initial value according to the N*D counter, write the column counter The value is 1, pointing to the second column, and the write row counter value is 2, pointing to the third row, so according to B10 bytes, it will be written in the second column and third row, and then the value of the write column counter remains unchanged, and every time it is written to RAM One byte, add 1 to the write row counter value, and write B11 and B12 in the fourth and fifth rows of the second column. At this time, since the write row counter has reached the maximum value of 4, after receiving the next input data refresh signal, the counter Reset, start counting from 0, at this time a convolution process occurs, write B13 to the first row of the second column, write B14 to the second row of the second column, and complete an interleaving writing process. The N*D counter is reset and the next write is started.

The second interleaving writing process is the same as the first time, and the storage positions of each byte of the obtained RS2 and RS3 codewords in the RAM storage unit are shown in Figure 2.

Read row counter, read column counter and read mode

The function of the read row counter is to control the read address (lower address) of the RAM. After being assigned the initial value, each time a row is read (that is, after the column counter = D-1), the loop is added by 1, that is, the read row counter = read row Counter +1.

The role of the read column counter is also to control the read address (high address) of the RAM. Its maximum value is the actual input d[6:0] value, and each time a byte is read, add 1, that is, read column counter = read column counter + 1. When the counter reaches the maximum value D-1, reset to 0.

Under the control of the data read address by the read row and read column counters, two read modes can be realized in the interleaved read process: sequential read and convolution read.

The N bytes used for the first group are read sequentially. At this time, the initial values of the read row counter and the read column counter are both 0, and the interleaved sequential read process is performed by row. Every time a word is read from RAM Section, read column counter value plus 1, after reading D bytes, read row counter plus 1, read column counter reset to 0, until N bytes are read sequentially.

Please refer to Figures 2 and 3, taking the second write and read process as an example, after writing the B20 byte of the first RS codeword, one byte should be read, at this time, the read column counter and read row counter start from N *The initial value assigned by the D counter is all zero, so the read address is the first row and the first column, that is, to read B20, then the read row counter remains unchanged, the read column counter adds 1, and the read address is the first row and the second column, Therefore, after writing B21, the read data is B13 written in the last interleave (refer to Figure 2 at the same time), then the read column counter is reset to 0, the row is read, the read row counter is incremented by 1, and the read address is updated to the first The first column of the second row, after writing B22, the read data is B21. By analogy, it can be known that the first group of N bytes read are B20, B13, B21, B14, and B22 in sequence.

The convolution method is used to read the second group of N bytes, the third group of N bytes...until the D-th group of N bytes, the convolution method reading process is also performed by row, read row counter and read column The initial value of the counter is determined by the N*D counter. Every time a byte is read from the RAM, the read column counter value is increased by 1. When the counter value is equal to D-1, the counter is reset to 0. After reading a line, read the row counter plus 1. Starting from the second group, the first byte read is related to the number of N.

As shown in Figure 3, when reading the second set of data for the second time, the initial value of the read column counter is 1 from the N*D counter, and the initial value of the read row counter is 2 from the N*D counter, so Starting from the second column of the third row, the first byte read is B30, and the other bytes of the second group of N bytes are the fourth row (B23, B31), and the fifth row (B24, B32), thus Complete an interleaved read process.

Figure 3 shows the bytes read out for the 1st and 2nd time and the read position, where the B13-1 read in the second column of the first row and the second column in the second row are read for the first time The read B14-1 indicates that it is the third byte and the fourth byte of the previous codeword of the RS0 codeword.

Deinterleaving is the inverse process of interleaving. When a continuous data stream is deinterleaved, it is assumed that the number of bytes of the RS codeword is N (the present embodiment N=5), and the interleaving depth is D (the present embodiment D=5). 2). The deinterleaving process of N*D bytes is to first read a byte in the RAM storage unit, then write a byte from the RAM storage unit, then read a byte, and then write a byte until N *D bytes read and write completed. By controlling the read and write addresses, the recombination of bytes after interleaving is completed, and the codeword before interleaving is restored. The beat of reading and writing is controlled by the clock signal clk, while reading or writing is controlled by the signal of the read and write control line.

FIG. 3 shows the second deinterleave writing process of this embodiment, and the interleaved N-byte groups of data are written. FIG. 2 shows the secondary deinterleaving and reading process of this embodiment. Read the codewords RS0 and RS1 for the first time, read the codewords RS2 and RS3 for the second time, and restore the codewords.

The device in Fig. 1 is still used for deinterleaving in this embodiment, and in the working mode of each hardware:

The working mode of the N*D counter is exactly the same as that during interleaving, and the initial value assigned to each counter according to the first byte indication signal and the division of the RAM storage units are also the same, and will not be repeated here.

The combination of read and write addresses of RAM storage units is the same as that of interleaving. The counter values of read and write rows control the low bits of read and write addresses, and the counter values of read and write columns control the high bits of read and write addresses. However, in the deinterleaving process, when the input data refresh indication signal is valid, a byte is first read, and an output data refresh pulse indication signal is generated, and then a byte is written, and so on.

The read row counter, read column counter and read mode during deinterleaving are respectively corresponding to the write row counter, write column counter and write mode during interleaving. Wherein, the read line counter completes cycle increment by 1 according to the input data refresh indication signal, the maximum value is N-1, and resets to 0 when the count reaches the maximum value. The read column counter value is used to control the high bit of the RAM read address, and is directly obtained from the low bit of the N*D counter according to the first byte indication signal. In the reading process of de-interleaving, the first RS codeword is read in a sequential manner, and it is carried out by column. The initial values of the row and column counters are all zero, and the column counter is increased by 1 after reading N bytes. From Fig. 2, read the first column in the first reading process to get B00-B04 in turn, and recover the code word RS0. The convolution method is used to write codewords other than the first one. The convolution reading process is also performed by column. The initial value of the read address is determined by the N*D counter. Every time a byte is read, the row counter is incremented by 1 to reach When the maximum value is N-1, reset to zero and start counting again. After reading N bytes, the column counter adds 1 when assigning the initial value. In Fig. 2, read B11, B12, B13 and B14 sequentially from B10 in the third row and second column, and recover the code word RS1.

The write row counter, write column counter, and write mode during deinterleaving correspond to the read row counter, read column counter, and read mode during interleaving, respectively. Wherein, after writing one line, the writing line counter is cycled and incremented by 1. The maximum value of the write column counter is D-1, and every time a byte is written, the cycle increases by 1. When the counter reaches the maximum value, it is reset to 0 and counted again. In the writing process of de-interleaving, the first group of N bytes is written in a sequential manner, which is carried out by row. The initial values of the row and column counters are both zero, and each time a byte is written, the value of the column counter is written. Add 1, after writing D bytes, add 1 to the write line counter until N bytes are written in sequence. The convolution method is used when writing the second group and subsequent groups of bytes, and it is also performed by row. The initial value of the write row counter and write column counter is determined by the N*D counter. Every time a byte is written, the write column counter value Add 1. When the counter value is equal to D-1, reset to 0 and count again. After writing a line, add 1 to the write line counter. Starting from the second group, the first byte written is related to the value of N. In Figure 3, the first byte of the second group is written from the second column of the third row, such as B10 and B30.

Please refer to Figures 2 and 3. The first read and second write processes of deinterleaving in the figure are interleaved. The read operation is performed first, and B00 is read from the first row and first column of the first write result, and then Perform a write operation, write B20 in the first row and first column, according to the above read and write rules, read B01, write B13, read B02, write B21, read B03, write B14, read B04, write B22, at this time, Start to read and write the second group of N-byte data, starting from the second column of the third row, because B30 is not written, read B10, then write B30 at this position, then read B11, write B23, Read B12, write B31, read B13 (written above), write B24, read B14, write B32. It can be seen that the two codewords RS0 and RS1 before interleaving are read out.

Claims (6)

1, the implement device of convolutional interleave and deinterleaving in a kind of ADSL (Asymmetric Digital Subscriber Line) comprises storage control circuit and memory cell, it is characterized in that:

The input signal of described storage control circuit comprises first byte index signal, input data signal, input Refresh Data index signal and clock signal; It comprises address signal, write data signal and read-write control signal with the signal that is connected between described memory cell, and described memory cell output signal comprises outputting data signals and dateout refresh instructing signal;

Described storage control circuit comprises address generating device, and this control circuit is used in described memory cell writing a byte earlier according to described input Refresh Data indication when interweaving, and reads a byte then; When deinterleaving, then earlier read a byte, write a byte then in described memory cell; Address generating device wherein is used for interweaving or the generation of address is write, read in deinterleaving time control, realizes writing in a sequential manner and reading first code word, writes and read remaining code word in the convolution mode.

2, implement device as claimed in claim 1, it is characterized in that, described address generating device comprises that N*D counter, amalgamation generate writing linage-counter and writing column counter of write address, amalgamation generates reads reading linage-counter and reading column counter of address, described memory cell is divided into the capable D row of N according to byte quantity parameter N and interleave depth parameter D, wherein:

The initial value of described N*D counter is 0, and maximum is the product of N and D, D=2 ^mWhen described first byte index signal is effective, the low m position of this counter composed to described as initial value write row and read column counter, this counter is removed a high position remaining behind the m position to be composed to described as initial value and writes row and read linage-counter, and finish circulation and add N, reset when being added to maximum, again counting;

The described column counter of writing determines its output valve by the initial value of giving when interweaving; When deinterleaving, whenever write a byte, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again;

The described linage-counter of writing whenever writes a byte when interweaving, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again; When deinterleaving, whenever write delegation, count value adds 1;

The described column counter of reading whenever reads a byte when interweaving, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again; When deinterleaving, determine its output valve by the initial value of giving;

The described linage-counter of reading whenever runs through delegation when interweaving, count value adds 1; When deinterleaving, whenever read a byte, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again.

3, implement device as claimed in claim 2 is characterized in that, the described value of writing row and reading linage-counter is the low level as described address signal, and the described value of writing row and reading column counter is the high position as described address signal.

4, implement device as claimed in claim 1 is characterized in that, described memory cell realizes with the random asccess memory of single port.

5, implement device as claimed in claim 4 is characterized in that, described storage control circuit also comprises clock signal with the signal that is connected between the single port random asccess memory, and described single port random asccess memory is the 8 bit synchronous random asccess memory that have clock signal.

6, implement device as claimed in claim 1 is characterized in that, described byte quantity parameter N and interleave depth parameter D are provided by the signal of importing storage control circuit.

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