CN1705233B - Injection-locked frequency division circuit and its frequency division method - Google Patents
Injection-locked frequency division circuit and its frequency division method Download PDFInfo
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Abstract
一种注入锁定式分频电路,其包含有一选取模块,用来产生一控制信号;一偏压模块,耦接于该选取模块,用来接收一原始信号,以依据该控制信号产生一偏压信号;以及一振荡模块,耦接于该偏压模块,用来接收该偏压信号以产生一目标信号;其中该目标信号的频率与该原始信号的频率之间是具有一比率关系。
An injection-locked frequency division circuit includes a selection module for generating a control signal; a bias module coupled to the selection module for receiving an original signal to generate a bias signal according to the control signal; and an oscillation module coupled to the bias module for receiving the bias signal to generate a target signal; wherein the frequency of the target signal has a ratio relationship with the frequency of the original signal.
Description
技术领域technical field
本发明涉及一种分频电路与其分频方法,特别涉及一种藉由控制偏压电流来扩大带宽的注入锁定式分频电路与其分频方法。The invention relates to a frequency division circuit and its frequency division method, in particular to an injection-locked frequency division circuit and its frequency division method which expands the bandwidth by controlling the bias current.
背景技术Background technique
分频电路(frequency divider)是频率合成器(frequency synthesizer)中一个非常重要的部分,用以对一原始脉波进行分频来产生一目标脉波,其中该目标脉波的频率与该原始脉波的频率是对应一分频比率。如业界所熟知,传统来说分频电路是由多个分频单元彼此串接(cascade)而成,其中经常采用触发器(flip-flop)为其主要元件,但由于触发器(flip-flop)本身是一数字元件,其一般来说是由一预设低电压(例如0V)与一预设高电压(例如5V)来驱动,因此,对于分频电路中的每一个触发器来说,在充放电荷的时候需要消耗很大的功率,也因此在操作频率很高的时候,传统分频电路的功率消耗也随之增加。The frequency divider is a very important part of the frequency synthesizer (frequency synthesizer), which is used to divide an original pulse wave to generate a target pulse wave, wherein the frequency of the target pulse wave is the same as the original pulse wave The frequency of the wave is corresponding to a frequency division ratio. As is well known in the industry, traditionally a frequency division circuit is formed by a plurality of frequency division units connected in series (cascade), in which a flip-flop is often used as its main component, but due to the flip-flop ) itself is a digital element, which is generally driven by a preset low voltage (such as 0V) and a preset high voltage (such as 5V). Therefore, for each flip-flop in the frequency division circuit, It needs to consume a lot of power when charging and discharging. Therefore, when the operating frequency is high, the power consumption of the traditional frequency division circuit also increases.
因此,注入锁定式分频电路(injection-locked frequency divider)遂应运而生,如Rategh等人于“Superharmonic Injection-LockedFrequency Dividers”,IEEE Journal of Solid-State Circuits,Vol.34,No.6,June 1999中所述,注入锁定式分频电路是为模拟式的分频电路,其直接处理传送过来的原始模拟信号,并输出一个分频过后的模拟信号。一般来说,注入锁定式分频电路是由一振荡模块及一偏压模块所组成。该偏压模块是用来接收由前级电路(例如频率合成器中的压控振荡器)所传送过来、欲进行分频的原始信号,并将之注入该振荡模块。注入锁定式分频电路在经过适当的设计后,即可自该振荡模块中撷取出分频后的目标信号,其中该目标信号的振荡频率及该原始信号的振荡频率是锁定于一特定的分频比率,而该分频比率则取决于电路特性。Therefore, injection-locked frequency divider (injection-locked frequency divider) came into being, such as Rategh et al. in "Superharmonic Injection-Locked Frequency Dividers", IEEE Journal of Solid-State Circuits, Vol.34, No.6, June As described in 1999, the injection-locked frequency division circuit is an analog frequency division circuit, which directly processes the original analog signal transmitted and outputs a frequency-divided analog signal. Generally, an injection-locked frequency division circuit is composed of an oscillation module and a bias voltage module. The bias voltage module is used to receive the original signal to be frequency-divided transmitted by the previous stage circuit (such as the voltage-controlled oscillator in the frequency synthesizer), and inject it into the oscillation module. After the injection-locked frequency division circuit is properly designed, the frequency-divided target signal can be extracted from the oscillation module, wherein the oscillation frequency of the target signal and the oscillation frequency of the original signal are locked to a specific frequency division. The frequency ratio depends on the circuit characteristics.
虽然注入锁定式分频电路拥有可在高频运作的优点,且可直接处理模拟信号来节省功率消耗,但是由于注入锁定式分频电路的电路设计必须要适当地匹配原始信号的振荡频率与振荡模块的振荡频率(亦即其中心频率)才能够正常地执行分频运作,因此注入锁定式分频电路的工作带宽通常都相当地窄。Although the injection-locked frequency division circuit has the advantages of operating at high frequencies and can directly process analog signals to save power consumption, the circuit design of the injection-locked frequency division circuit must properly match the oscillation frequency and oscillation of the original signal. Only the oscillation frequency of the module (that is, its center frequency) can normally perform the frequency division operation, so the working bandwidth of the injection-locked frequency division circuit is usually quite narrow.
发明内容Contents of the invention
因此,本发明的主要目的在于提供一种藉由控制偏压电流来扩大带宽的注入锁定式分频电路与其分频方法。Therefore, the main purpose of the present invention is to provide an injection-locked frequency division circuit and a frequency division method thereof for enlarging the bandwidth by controlling the bias current.
依据本发明的实施例,是揭露一种注入锁定式分频电路,其包含有一选取模块,用来产生一控制信号;一偏压模块,耦接于该选取模块,用来接收一原始信号,以依据该控制信号产生一偏压信号;以及一振荡模块,耦接于该偏压模块,用来接收该偏压信号以产生一目标信号;其中该目标信号的频率与该原始信号的频率之间是具有一比率关系。According to an embodiment of the present invention, an injection-locked frequency division circuit is disclosed, which includes a selection module for generating a control signal; a bias module coupled to the selection module for receiving an original signal, to generate a bias signal according to the control signal; and an oscillation module, coupled to the bias module, for receiving the bias signal to generate a target signal; wherein the frequency of the target signal is different from the frequency of the original signal There is a ratio relationship between them.
依据本发明的实施例,亦揭露一种分频方法,其包含有输入一原始信号;输入一控制信号;利用一偏压模块,依据该原始信号及该控制信号产生一偏压信号;利用一振荡模块,依据该偏压信号产生一目标信号;以及改变该控制信号以改变该目标信号的频率,其中该目标信号的频率与该原始信号的频率之间是具有一比率关系。According to an embodiment of the present invention, a frequency division method is also disclosed, which includes inputting an original signal; inputting a control signal; using a bias module to generate a bias signal according to the original signal and the control signal; using a The oscillation module generates a target signal according to the bias signal; and changes the control signal to change the frequency of the target signal, wherein the frequency of the target signal has a ratio relationship with the frequency of the original signal.
附图说明Description of drawings
图1为本发明一实施例的注入锁定式分频电路的示意图。FIG. 1 is a schematic diagram of an injection-locked frequency division circuit according to an embodiment of the present invention.
图2为本发明另一实施例的注入锁定式分频电路的示意图。FIG. 2 is a schematic diagram of an injection-locked frequency division circuit according to another embodiment of the present invention.
图3为本发明又一实施例的注入锁定式分频电路的示意图。FIG. 3 is a schematic diagram of an injection-locked frequency division circuit according to another embodiment of the present invention.
附图符号说明:Explanation of reference symbols:
50、50′、50″分频电路50, 50', 50" frequency division circuit
60、60′、60″振荡模块60, 60', 60" Oscillator Module
70、70a、70b、70c、70d、70e偏压模块70, 70a, 70b, 70c, 70d, 70e Bias Module
80输入信号源80 input signal sources
90选取模块90 selection modules
92偏压电压产生器。92 bias voltage generator.
具体实施方式Detailed ways
请参阅图1,图1为依据本发明一实施例的除以三(divided-by-3)注入锁定式分频电路(injection-locked frequency divider)50的示意图。在本实施例中,注入锁定式分频电路50包含有一振荡模块60、一偏压模块70、以及一选取模块90。偏压模块70是用来接收自一输入信号源80(可为频率合成器的压控振荡器或者其他需要进行分频动作的信号源)所传来的原始信号,并依据该原始信号注入电流至振荡模块60,以在振荡模块60产生分频后的目标信号,其中该目标信号的振荡频率及该原始信号的振荡频率是锁定于一特定的分频比率,而该分频比率则取决于电路特性。除此之外,偏压模块70亦会依据选取模块90所传送过来的控制信号,决定注入至振荡模块60的偏压电流量。如熟习此项技术者所广泛悉知,由于振荡模块60的振荡频率是可由所输入的偏压电流量来决定,则藉由以上所述的控制机制可调整注入锁定式分频电路50的操作频带。如此一来,本实施例的注入锁定式分频电路50即可具有较大的操作带宽。Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a divided-by-3 injection-locked frequency divider circuit (injection-locked frequency divider) 50 according to an embodiment of the present invention. In this embodiment, the injection-locked frequency division circuit 50 includes an
在本实施例中,振荡器60是为一由三个反向器所组成的环形振荡器(ring oscillator),环形振荡器的组态及操作原理是为熟习此项技术者所广泛悉知,故不在此赘述。偏压模块70中则包含有多个子偏压模块70a、70b、70c、70d、70e,分别透过电芯片M12、M13、M14、M15、M16耦接于一由一电流源IB及一电芯片M11所组成的偏压电流产生器92,而分别形成多个电流镜组态(current mirror configuration),以分别在每一子偏压模块70a、70b、70c、70d、70e上复制出一偏压电流。而每一子偏压模块70a、70b、70c、70d、70e亦包含有一控制开关(如图1所示的电芯片M17、M18、M19、M20、M21),分别由选取模块90所产生的控制信号C1、C2、C3、C4、C5来控制其开闭,也就是说,当一控制开关处于开启状态时,其所对应的子偏压模块即处于致能状态。如此一来,选取模块90即可藉由所产生的控制信号C1、C2、C3、C4、C5的不同组合来控制注入振荡模块60的偏压电流量,以进一步控制注入锁定式分频电路50进行将自输入信号源80所输入的原始信号进行分频操作时的操作频带。换句话说,选取模块90即能够改变控制信号C1、C2、C3、C4、C5的组合以改变该目标信号的振荡频率,而进一步改变注入锁定式分频电路50的操作频带。In this embodiment, the
以本实施例来说,由于振荡模块60为一由三反向器所组成的环形振荡器,故由输入信号源80所产生的原始信号及由振荡模块60所取出的目标信号的振荡频率之间的分频比率是为3∶1,也就是说,图1中的输入端A与输出端B上的信号的振荡频率会具有一特定比例关系3∶1。如前所述,由于振荡模块60的振荡频率是可由所输入的偏压电流量来决定,故当注入振荡模块60的偏压电流量由选取模块90控制于不同的大小时,振荡器60的中心频率即会随之而有不同的数值,进而可使注入锁定式分频电路50适用于对不同振荡频率的原始信号进行分频,也就是说,本实施例的注入锁定式分频电路50可经由子偏压模块70a、70b、70c、70d、70e的辅助而具有较大的操作带宽。In this embodiment, since the oscillating
子偏压模块70a、70b、70c、70d、70e中用来构成电流镜的电芯片M12、M13、M14、M15、M16可具有相同的元件特性,例如对应相同的通道宽度/长度比(W/L ratio,aspect ratio),所以选取模块90可经由控制子偏压模块70a、70b、70c、70d、70e的开启个数来达到控制偏压电流的目的。然而,子偏压模块70a、70b、70c、70d、70e中用来构成电流镜的电芯片M12、M13、M14、M15、M16亦可具有不同的元件特性,例如对应不同的通道宽度/长度比,举例来说,电芯片M12、M13、M14、M15、M16的通道宽度/长度比可具有以下比率:1∶2∶4∶8∶16,如此则藉由不同的控制信号组合,可达到更大范围的操作带宽。请注意,图1中仅显示五个偏压模块70a、70b、70c、70d、70e以便于说明,然而,本发明注入锁定式分频电路50并未限制子偏压模块的个数。The electrical chips M12, M13, M14, M15, M16 used to form the current mirror in the sub-bias modules 70a, 70b, 70c, 70d, 70e can have the same element characteristics, such as corresponding to the same channel width/length ratio (W/ L ratio, aspect ratio), so the
请参阅图2,图2中显示本发明一实施例的除以四(divided-by-4)注入锁定式分频电路50′的示意图。图2中的注入锁定式分频电路50′与图1中的注入锁定式分频电路50十分相似,然而图2中的振荡模块60′是使用一差动式(differential mode)环形振荡器,差动式环形振荡器的电路组态及操作方式是为熟习此项技术者所广泛悉知,故不在此赘述。而图2中的注入锁定式分频电路50′的操作原理是与图1中的注入锁定式分频电路50相同,故不重复说明。Please refer to FIG. 2 , which shows a schematic diagram of a divided-by-4 injection-locked frequency dividing circuit 50 ′ according to an embodiment of the present invention. The injection-locked
请参阅图3,图3中显示本发明一实施例的除以二(divided-by-2)注入锁定式分频电路50″示意图。图3中的注入锁定式分频电路50″与图1中的注入锁定式分频电路50十分相似,然而图3中的振荡模块60″是使用一LC共振腔式(LC tank)振荡器,LC共振腔式振荡器的电路组态及操作方式是为熟习此项技术者所广泛悉知,故不在此赘述。而图3中的注入锁定式分频电路50″的操作原理是与图1中的注入锁定式分频电路50相同,故不重覆说明。Please refer to FIG. 3 , which shows an embodiment of the present invention divided by two (divided-by-2) injection-locked frequency division circuit 50 "schematic diagram. Injection-locked frequency division circuit 50 " in Fig. 3 and Fig. 1 The injection-locked frequency division circuit 50 is very similar to the one shown in FIG. It is widely known by those skilled in the art, so it will not be repeated here. And the operation principle of the injection-locked frequency division circuit 50 "in Fig. 3 is the same as that of the injection-locked frequency division circuit 50 in Fig. 1, so it will not be repeated illustrate.
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明专利的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.
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| CN105322961A (en) * | 2015-12-11 | 2016-02-10 | 上海交通大学 | Injection locking type dual-mode prescaler with low power consumption and wide locking range |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953010A (en) * | 1987-03-09 | 1990-08-28 | Plessey Overseas Limited | FM demodulator including injection locked oscillator/divider |
| CN1081032A (en) * | 1992-01-13 | 1994-01-19 | 日本电气株式会社 | frequency synthesizer |
| US20030025566A1 (en) * | 2001-08-01 | 2003-02-06 | Ar Card | Automatic gain control for a voltage controlled oscillator |
| US6781471B2 (en) * | 2002-04-10 | 2004-08-24 | Airoha Technology Corp. | Low phase noise voltage controlled oscillator circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953010A (en) * | 1987-03-09 | 1990-08-28 | Plessey Overseas Limited | FM demodulator including injection locked oscillator/divider |
| CN1081032A (en) * | 1992-01-13 | 1994-01-19 | 日本电气株式会社 | frequency synthesizer |
| US20030025566A1 (en) * | 2001-08-01 | 2003-02-06 | Ar Card | Automatic gain control for a voltage controlled oscillator |
| US6781471B2 (en) * | 2002-04-10 | 2004-08-24 | Airoha Technology Corp. | Low phase noise voltage controlled oscillator circuit |
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