CN1702969B - Delay chain virtually independent of temperature - Google Patents

Abstract

A delay chain substantially independent of temperature and a method and apparatus for generating a temperature compensated signal, such as a sense amplifier for providing a signal having a delay over a range of delay times and over a range of temperatures to a memory array. A variable signal is generated in response to a start signal. The clock signal generates an additional load of impedance to couple to the variable signal, such as to generate a temperature compensation signal via the control circuit.

Description

Delay chain virtually independent of temperature

technical field

The present invention relates generally to a clock integrated circuit, and more particularly to an integrated circuit having a signal delayed in a delay time range and a temperature range.

Background technique

A variety of integrated circuits with different functions all have high-speed clocks, which require precise timing. For example, in some memory devices, the sense amplifier senses data within one clock cycle, so the data output time corresponding to the read data must be precisely controlled. However, the precise delay of signals generated by integrated circuits over a range of temperatures is an important issue because of the changing behavior of semiconductors at different temperatures.

One approach to address temperature variations is to use a design methodology: "worst-case" simulation. For example, methods that underestimate the state of the circuit can lead to more expensive redundant designs. What is more urgently needed is to make the integrated circuit meet the timing requirements without redundant and excessively expensive designs.

Contents of the invention

According to the object of the present invention, a method for generating a temperature compensation signal in an integrated circuit is proposed. The variable signal has variable characteristic values such as voltage or current. At the first point in time, a certain part of the integrated circuit generates the variable signal corresponding to the start signal. A clock signal is generated in the integrated circuit, and the clock signal acts on multiple loads of the integrated circuit. The additional impedance of a plurality of loads is coupled to this portion of the circuit with a variable signal corresponding to the clock signal. When the variable characteristic value of the variable signal reaches the reference level, the integrated circuit generates a signal at the second time point. The characteristics of the signal are determined by a delay time range and a temperature range between the first time point and the second time point.

In various embodiments, the clock signal is used to generate the temperature compensation signal via the control circuit, and the clock signal causes the additional impedance of the composite load to be coupled with the part of the integrated circuit in turn with a variable signal.

According to another object of the present invention, an integrated circuit device is provided. The integrated circuit device has a circuit for carrying a variable signal with a variable characteristic value, a clock circuit, a composite impedance and an output. The circuit loads the variable signal corresponding to the start signal at the first time point. The clock circuit is, for example, a ring oscillator for generating a clock signal. The composite impedance is coupled to the clock circuit and the circuit, and a sum impedance increases corresponding to the clock signal. The output terminal is coupled to the circuit and outputs a signal at the second time point. The characteristic of the signal is determined by the delay time range between the first time point and the second time point and the delay phenomenon in the temperature range.

According to another object of the present invention, a method of manufacturing an integrated circuit is proposed. First, a semiconductor substrate is provided. A circuit is formed corresponding to the initial signal at the first time point to load a variable signal with a variable characteristic value. Then, a clock circuit is formed on the semiconductor substrate to generate clock signals. Afterwards, a composite impedance is formed on the semiconductor substrate to be coupled to the clock circuit and the circuit, and the composite impedance has a total impedance that increases corresponding to the clock signal. Next, an output end coupled to the circuit is formed on the semiconductor substrate, and the output end outputs a signal at a second time point. The characteristic of the signal is determined by the delay time range between the first time point and the second time point and the delay phenomenon of a temperature range.

In various embodiments, the signal provides timing to a sense amplifier. The sense amplifier is coupled to a memory array, both of which are included in some embodiments of the present invention.

In many embodiments, the correlation of temperature to a variable signal is evident, eg, generated by an inverter, coupled to a fixed load, and changing rapidly as temperature drops. To compensate for this temperature dependence, a clock signal is used to couple the additional impedance to the variable signal. The generation speed of the clock signal becomes faster as the temperature drops and becomes slower as the temperature rises. As the temperature drops, the clock signal is generated faster and the additional impedance coupled to the variable signal speeds up. As the temperature rises, the clock signal is generated at a slower rate, and the speed at which the additional impedance is coupled to the variable signal decreases. The complex impedance is precisely chosen such that the delay phenomenon is substantially constant over a temperature range of at least 120 degrees. In some embodiments, the delay does not vary by more than 1 nanosecond over a temperature range of at least 120 degrees Celsius. In one embodiment, the circuit generates a signal after a delay of 10 nanoseconds corresponding to the initial signal, and the signal does not vary by more than 2 nanoseconds in a temperature range of at least 160 degrees Celsius.

Whether multiple signal edges of the clock signal are continuous or discontinuous falling edges or rising edges depends on the nature of the N-type or P-type transistor and the setting of the circuit itself. The control circuit receives multiple signal edges of the clock signal and outputs a control signal, and the control signal increases the total impedance of the composite impedance corresponding to each signal edge of the clock signal. In some embodiments, the control signal is connected to an NMOS transistor electrically connected to the additional impedance and the variable signal. In one embodiment, the variable characteristic value of the variable signal rises to a reference level, and the initial value of the variable signal is low level, such as grounded. In some embodiments, the control signal is connected to a PMOS transistor electrically connected to an additional impedance and a variable signal. In one embodiment, when the variable characteristic value of the variable signal drops to the reference level, the initial value of the variable signal is a high level, such as the voltage of a power supply.

In some embodiments, the level of the variable signal is detected by a level detector and compared with a reference level, and a signal is generated after the variable signal reaches the reference level.

According to another object of the present invention, a method for generating a temperature-compensated output in an integrated circuit is provided. Corresponding to a start signal of the integrated circuit at the first time point, trigger the first circuit of the integrated circuit to execute the main function of the first circuit and generate the output signal of the main function, and trigger the second circuit of the integrated circuit to generate at the second time point second signal. The second signal has a delay phenomenon in a delay time range between the first time point and the second time point. This delay phenomenon is not related to the output of the main function. The main function output signal is allowed to pass through other circuits in the integrated circuit after a delay phenomenon.

According to another object of the present invention, there is provided an integrated circuit with a plurality of circuits. The first circuit corresponds to the start signal at the first time point to execute the main function and generate the output signal of the main function. The second circuit generates a second signal at a second time point corresponding to the start signal. The second signal has a delay phenomenon within a delay time range between the first time point and the second time point. This delay phenomenon is not related to the timing of the output of the main function. The third circuit is coupled to the first circuit and the second circuit, and receives the main function output signal and the second signal. The third circuit allows the main function output signal to pass through other circuits in the integrated circuit without delay.

In some embodiments, the delay phenomenon is controlled by a clock signal triggered corresponding to the start signal, so that the delay phenomenon is not correlated with the output of the main function.

Description of drawings

The diagram in Fig. 1 is a schematic block diagram of a circuit for correcting signal timing and a task function circuit.

Figure 2 is a schematic block diagram of an integrated circuit with a memory array and circuitry to correct signal timing.

FIG. 3 is a schematic block diagram of a circuit for correcting signal timing.

The drawing in Figure 4 is a circuit diagram for simplifying the clock circuit.

The diagram in Fig. 5 is a circuit diagram of a control circuit for controlling the additional impedance by means of a clock signal.

Fig. 6 is a schematic diagram of a composite impedance added to a variable signal according to a control circuit.

The diagram in Fig. 7 is a waveform timing diagram of the clock circuit and the control circuit.

Figures 8A and 8B are voltage trace diagrams of variable signals at different temperatures and delay phenomena in a delay time range and temperature range.

FIG. 9 is a flow chart of an embodiment for generating a delay phenomenon in a delay time range and a temperature range.

[Description of main component labels]

120: Task function circuit

130: temperature compensation circuit

140: circuit

205: memory integrated circuit

210: Address Transfer Detector

220: temperature compensation circuit

230: Sense Amplifier

240: address decoder

250: storage array

310: clock circuit

320: control circuit

325: Composite load

330, 340, Z0610, Z1620, Z2630, Z3640, Z4650: load

350: Level Detector

430: NOR gate

440, 450, 460, 470: inverter

515, 525, 526, 535, 536, 545, 546, 555, 556: p-type transistors

517, 527, 537, 547, 557, 611, 612, 613, 621, 622, 623, 631, 632, 633, 641, 642, 643, 651, 652, 653, 654: n-type transistors

512, 514, 522, 524, 532, 534, 542, 544, 552, 554, 582, 585, 588, 591, 680: inverter

581, 584, 587, 590: NAND gates

Detailed ways

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Please refer to FIG. 1 , which is a schematic block diagram of the temperature compensation circuit 130 and the task function circuit 120 . The task function circuit 120 includes a plurality of circuits, which are used to make the integrated circuit behave as a whole or a specific function block. Both the temperature compensation circuit 130 and the task function circuit 120 receive the start signal 110 . After receiving the start signal 110 , the temperature compensation circuit 130 generates a temperature compensation signal 135 with an accuracy of n nanoseconds, regardless of the ambient temperature within a wide temperature range, such as -45°C to 125°C. The circuit 140 treats the time output signal as an activation signal and generates an output signal 145 that is referenced to the task function output signal 125 . The circuit 140 also amplifies the task output signal 125 to generate an output signal 145 . Therefore, the various embodiments can achieve equivalent performance in any integrated circuit, so that the output and input signals of the temperature compensation circuit of the integrated circuit follow a fixed and clear delay relationship regardless of the surrounding temperature state.

Please refer to FIG. 2 , which is a schematic block diagram of the memory integrated circuit 205 . The memory array 250 receives a plurality of signals output from the address decoder 240 to access specific units or blocks in the memory array 250 . The sense amplifier 230 reads the stored values in the memory array 250 . The temperature compensation circuit 220 must correctly clock the sense amplifier 230 so that the amplitude of the bit line voltage generated by the memory array 250 is precisely timed regardless of the surrounding temperature conditions. The temperature compensation circuit adjusts the increasing speed of the additional impedance according to the speed of the clock, and maintains the timing of the sense amplifier in a specific time range and a temperature range.

Please refer to FIG. 3 , which is a schematic block diagram of a temperature compensation circuit. Clock circuit 310 generates a clock to define the rate at which the additional impedance of composite load 325 increases to variable signal 370 . The control circuit 320 receives the clock generated by the clock circuit 310 and generates a temperature compensation signal to select the additional impedance of the composite load 325 added to the variable signal 370 . In addition to load 330 and load N 340 listed, composite load 325 includes any additional loads to match the output of control circuit 320 . For example, in one embodiment, the control circuit 320 selects 5 feasible loads, and the composite load 325 includes 5 loads. The more loads in the composite load 325, the more precise the clock control of the delay phenomenon is. The start signal 305 , preferably a timing signal, is coupled to the clock circuit 310 , the control circuit 320 and the composite load 325 , and causes the output signal 355 to start to be generated with a delay in a delay time range and a temperature range. The level detector 350 generates an output signal 355 after the variable signal 370 reaches a reference level 358 provided by the level detector 350 .

Please refer to FIG. 4, which shows a simplified circuit diagram of the clock circuit. The clock circuit is, for example, a ring oscillator as shown. The NOR gate 430, the inverter 440, the inverter 450, the inverter 460 and the inverter 470 are connected in series, such that the output terminal of the first inverter is coupled to the input terminal of the second inverter. The output terminal of the last inverter 470 is coupled to the input terminal of the NOR gate 430 . The number of inverters can be varied to adjust the speed of the clock circuit. An increase in the number of inverters slows down the clock circuit, and a decrease in the number of inverters speeds up the clock circuit. In the embodiment discussed, the ring oscillator provides two signals, clock A 410 at the input of inverter 470 and clock B 420 at the output of inverter 470. Because clock A 410 and clock B 420 come from the input and output of the inverter, respectively, clock A 410 and clock B 420 are almost complementary signals to each other, although clock B 420 is relatively different from clock A 410 due to the processing of inverter 470. There is an associated transmission delay phenomenon.

Please refer to FIG. 5, which is a circuit diagram of a control circuit for controlling the additional impedance by a clock signal. The control circuit in this example includes 5 levels. Other embodiments include different levels, such as controlling the number of corresponding impedances to increase to add variable signals.

The first stage includes p-type transistor 515 , n-type transistor 517 and inverters 512 and 514 . The gate of the p-type transistor 515 is coupled to the clock A 410, its first current-carrying terminal is coupled to the supply voltage VD570, and its second current-carrying terminal is coupled to the terminal 518. The gate of the n-type transistor 517 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 518 , and its second current-carrying terminal is coupled to the ground 580 . The inverter 512 and the inverter 514 are coupled to form a latch circuit, and the latch circuit is coupled to terminals 518 and 519 . Terminal 518 provides signal P1B and terminal 519 provides signal P1.

The second stage includes p-type transistors 525 and 526 , n-type transistor 527 and inverters 522 and 524 . The gate of the p-type transistor 525 is coupled to the clock B 420, its first current-carrying terminal is coupled to the supply voltage VD 570, and its second current-carrying terminal is coupled to the current-loading terminal of the p-type transistor 526. The gate of the p-type transistor 526 is coupled to the terminal 519 , the first current-carrying terminal thereof is coupled to the current-carrying terminal of the p-type transistor 525 , and the second current-carrying terminal thereof is coupled to the terminal 528 . The gate of the n-type transistor 527 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 528 , and its second current-carrying terminal is coupled to the ground 580 . The inverter 522 and the inverter 524 are coupled to form a latch circuit, and the latch circuit is coupled to terminals 528 and 529 . Terminal 528 provides signal P2B and terminal 529 provides signal P2.

The third stage includes p-type transistors 535 and 536 , n-type transistor 537 and inverters 532 and 534 . The gate of the p-type transistor 535 is coupled to the clock A 410, its first current-carrying terminal is coupled to the supply voltage VD 570, and its second current-carrying terminal is coupled to the current-carrying terminal of the p-type transistor 536. The gate of the p-type transistor 536 is coupled to the terminal 529 , the first current-carrying terminal thereof is coupled to the current-carrying terminal of the p-type transistor 535 , and the second current-carrying terminal thereof is coupled to the terminal 538 . The gate of the n-type transistor 537 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 538 , and its second current-carrying terminal is coupled to the ground 580 . The inverter 532 and the inverter 534 are coupled to form a latch circuit, and the latch circuit is coupled to terminals 538 and 539 . Terminal 538 provides signal P3B and terminal 539 provides signal P3.

The fourth stage includes p-type transistors 545 and 546 , n-type transistor 547 and inverters 542 and 544 . The gate of the p-type transistor 545 is coupled to the clock B 420, its first current-carrying terminal is coupled to the supply voltage VD 570, and its second current-carrying terminal is coupled to the current-carrying terminal of the p-type transistor 546. The gate of the p-type transistor 546 is coupled to the terminal 539 , the first current-carrying terminal thereof is coupled to the current-carrying terminal of the p-type transistor 545 , and the second current-carrying terminal thereof is coupled to the terminal 548 . The gate of the n-type transistor 547 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 548 , and its second current-carrying terminal is coupled to the ground 580 . The inverter 542 and the inverter 544 are coupled to form a latch circuit, and the latch circuit is coupled to terminals 548 and 549 . Terminal 548 provides signal P4B and terminal 549 provides signal P4.

The fifth stage includes p-type transistors 555 and 556 , n-type transistor 557 and inverters 552 and 554 . The gate of the p-type transistor 555 is coupled to the clock A 410, its first current-carrying terminal is coupled to the supply voltage VD 570, and its second current-carrying terminal is coupled to the current-carrying terminal of the p-type transistor 556. The gate of the p-type transistor 556 is coupled to the terminal 549 , the first current-carrying terminal thereof is coupled to the current-carrying terminal of the p-type transistor 555 , and the second current-carrying terminal thereof is coupled to the terminal 558 . The gate of the n-type transistor 557 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 558 , and its second current-carrying terminal is coupled to the ground 580 . The inverter 552 and the inverter 554 are coupled to form a latch circuit, and the latch circuit is coupled to terminals 558 and 559 . Terminal 558 provides signal P3B and terminal 539 provides signal P3.

The following describes the combined logic circuit. The NAND gate 581 receives the signal P1B 518 and the signal P2 529, and its output terminal is coupled to the input terminal of the inverter 582. Inverter 582 outputs signal Q2 583. The NAND gate 584 receives the signal P2B 528 and the signal P3 539, and its output terminal is coupled to the input terminal of the inverter 585. Inverter 585 outputs signal Q3 586. The NAND gate 587 receives the signal P3B 538 and the signal P4 549, and the output end is coupled to the output end of the inverter 588. Inverter 588 outputs signal Q4 589. The NAND gate 590 receives the signal P4B 548 and the signal P5 559, and the output end is coupled to the input end of the inverter 591. Inverter 591 outputs signal Q5 592.

Please refer to FIG. 6, which is a circuit diagram of a complex impedance added to a variable signal according to a control circuit. The composite impedance in this example includes 5 levels of impedance. Other embodiments include different amounts of impedance, such as increasing impedance for variable signals for better control.

The inverter 680 generates a variable signal at the output terminal 682 corresponding to the start signal 305, and makes it rise from low level to high level. In another embodiment, the inverter 680 outputs a variable signal corresponding to the start signal 305 , and makes it drop from a high level to a low level.

The first stage impedance includes n-type transistors 611, 612 and 613 and a load Z0 610. The gate of the n-type transistor 611 is coupled to the signal P1 519, the first current-carrying terminal thereof is coupled to the output terminal 690, and the second current-carrying terminal thereof is coupled to the terminal 682. The gate of the n-type transistor 612 is coupled to the signal P1B 518 , its first current-carrying terminal is coupled to the output terminal 690 , and its second current-carrying terminal is coupled to the terminal 605 . The gate of the n-type transistor 613 is coupled to the start signal 305 , its first current-carrying terminal is coupled to the terminal 605 , and its second current-carrying terminal is coupled to the ground 580 . A load Z0 610 is coupled between terminals 605 and 615.

The second stage impedance includes n-type transistors 621, 622 and 623 and a load Z1 620. The gate of the n-type transistor 621 is coupled to the signal Q2 583, the first current-carrying terminal thereof is coupled to the output terminal 615, and the second current-carrying terminal thereof is coupled between the terminals 682. The gate of the n-type transistor 622 is coupled to the signal P2B528 , the first current-carrying terminal thereof is coupled to the terminal 615 , and the second current-carrying terminal thereof is coupled to the terminal 625 . The gate of the n-type transistor 623 is coupled to the start signal 305 , the first current-carrying terminal thereof is coupled to the terminal 625 , and the second current-carrying terminal thereof is coupled to the ground 580 . The load Z1620 is coupled to terminals 625 and 635 .

The third stage impedance includes n-type transistors 631, 632 and 633 and a load Z2 630. The gate of the n-type transistor 631 is coupled to the signal Q3 586, the first current-carrying terminal thereof is coupled to the output terminal 635, and the second current-carrying terminal thereof is coupled to the terminal 682. The gate of the n-type transistor 632 is coupled to the signal P3B 538, the first current carrying terminal thereof is coupled to the terminal 635, and the second current carrying terminal thereof is coupled to the terminal 645. The gate of the n-type transistor 633 is coupled to the start signal 305 , the first current-carrying terminal thereof is coupled to the terminal 645 , and the second current-carrying terminal thereof is coupled to the ground 580 . The load Z2 630 is coupled between the terminals 645 and 655.

The fourth stage impedance includes n-type transistors 641, 642 and 643 and a load Z3 640. The gate of the n-type transistor 641 is coupled to the signal Q4 589, the first current-carrying terminal thereof is coupled to the output terminal 655, and the second current-carrying terminal thereof is coupled to the terminal 682. The gate of the n-type transistor 642 is coupled to the signal P4B 548, the first current carrying terminal thereof is coupled to the terminal 655, and the second current carrying terminal thereof is coupled to the terminal 665. The gate of the n-type transistor 643 is coupled to the start signal 305 , the first current-carrying terminal thereof is coupled to the terminal 665 , and the second current-carrying terminal thereof is coupled to the ground 580 . A load Z3 640 is coupled between terminals 665 and 675.

The fifth stage impedance includes n-type transistors 651, 652, 653 and 654, and a load Z4 650. The gate of the n-type transistor 651 is coupled to the signal Q5 592, its first current-carrying terminal is coupled to the output terminal 675, and its second current-carrying terminal is coupled to the terminal 682. The gate of the n-type transistor 652 is coupled to the signal P5B 558 , the first current-carrying terminal thereof is coupled to the terminal 675 , and the second current-carrying terminal thereof is coupled to the terminal 685 . The gate of the n-type transistor 653 is coupled to the start signal 305 , the first current-carrying terminal thereof is coupled to the terminal 685 , and the second current-carrying terminal thereof is coupled to the ground 580 . The gate of the n-type transistor 654 is coupled to the start signal P5B 558, the first current carrying terminal thereof is coupled to the terminal 695, and the second current carrying terminal thereof is coupled to the terminal 682. The load Z4 650 is coupled between the terminal 685 and the terminal 695.

Please refer to FIG. 7, which is a waveform timing diagram of the clock circuit and the control circuit. Clock A 410 and clock B 420 come from the input and output of an inverter in a ring oscillator, respectively. Thus, clock A 410 and clock B 420 are almost complementary signals to each other. The control circuit operates in response to the start signal.

Please refer to Figure 5 and Figure 7 at the same time, the latch circuit composed of inverters 512 and 514, inverters 522 and 524, inverters 532 and 534, inverters 542 and 544, and inverters 552 and 554 At the beginning, the low level values are respectively stored in the endpoint 518 P1B, the endpoint 528 P2B, the endpoint 538 P3B, the endpoint 548 P4B and the endpoint 558 P5B. After the start signal 305 turns on the n-type transistors 517 , 527 , 537 , 547 and 557 , these low-level values are stored. The start signal 305 also stores a high level value at the endpoint P1 519, the endpoint P2 529, the endpoint P3 539, the endpoint P4 549 and the endpoint P5 559. Then, on the first falling edge of the clock A 410, the p-type transistor 515 is turned on and stores a high level value at the terminal 518 P1B, and stores a low level value at the terminal 519 P1. The falling edge of clock A 410 also turns on p-type transistors 535 and 555. However, the terminals 538P3B and 558P5B still maintain a low level, because the high level of the terminal 529P2 cuts off the transistor 536 interposed therebetween, and the high level of the terminal 549P4 makes the transistor 556 therebetween cut off.

Following the first falling edge of the clock B 420, the p-type transistor 525 is turned on, and the terminal 528 P2B stores a high level and the terminal 529 P2 stores a low level. After the previous falling edge of the clock A 410, the intervening p-type transistor 526 is turned on due to the low level stored at the terminal 519P1. The falling edge of clock B 420 also turns on p-type transistor 545. However, because the high level of the terminal 539P3 turns off the intervening p-type transistor 546, the terminal 548P4B remains low.

Following the second falling edge of the clock A 410, the p-type transistor 535 is turned on, and the terminal 538 P3B stores a high level and the terminal 539 P3 stores a low level. After the previous falling edge of the clock B 420, the intervening p-type transistor 536 is turned on due to the low level stored at the terminal 529P2. The falling edge of clock A 410 also turns on p-type transistor 555. However, because the high level of the terminal 549P4 turns off the intervening p-type transistor 556, the terminal 558P5B remains low.

Following the second falling edge of the clock B 420, the p-type transistor 545 is turned on, and the terminal 548P4B stores a high level and the terminal 549P4 stores a low level. After the previous falling edge of the clock A 410, the intervening p-type transistor 546 is turned on due to the low level stored at the terminal 539P3.

Following the third falling edge of the clock A 410, the p-type transistor 555 is turned on, and the high level of the terminal 558P5B and the low level of the terminal 559P5 are stored. After the previous falling edge of the clock B 420, the intervening p-type transistor 556 is turned on due to the low level stored at the terminal 549P4.

Thus, with each falling clock edge between the falling edges of clock A 410 and clock B 420, the additional latch element of the control circuit changes its stored value.

The combined logic circuit generates signals 583 Q2, 586 Q3, 589 Q4 and 592 Q5 which are high for half the period of the clock signal. The signal 583 Q2 generated by the NAND gate 581 and the inverter 582 rises to a high level after the signal 518 P1B rises to a high level, and falls to a low level after the signal P2 529 falls to a low level. The signal 586 Q3 generated by the NAND gate 584 and the inverter 585 rises to a high level after the signal 528 P2B rises to a high level, and falls to a low level after the signal P3 539 falls to a low level. Signal 589 Q4 generated by NAND gate 587 and inverter 588 is raised to high level after signal 538 P3B is raised to high level, and is lowered to low level after signal P4 549 is lowered to low level. The signal 592 Q5 generated by the NAND gate 590 and the inverter 591 rises to a high level after the signal 548 P4B rises to a high level, and falls to a low level after the signal P5559 falls to a low level.

Referring to FIG. 6 , each additional latch element in the control circuit changes its stored value, so that an additional impedance is coupled to the variable signal at the terminal 682 of the inverter 680 . Because the control circuit is at the beginning, the terminal 519 P1 is high level, and the Q2 583, Q3 586, Q4 589, Q5 592, Q2 583 and P5B 558 are low level. The n-type transistor 611 is initially turned on, and the n-type transistors 621 , 631 , 641 , 651 and 654 are initially turned off. Therefore, loads Z0 610 , Z1 620 , Z2 630 , Z3 640 and Z4 650 are not coupled to the variable signal at terminal 682 . As a result, the variable signal initially rises relatively quickly.

As additional loads are coupled to the variable signal, the rate of rise of the variable signal thus decreases. Thus, with each falling clock signal edge between the falling edges of clock A 410 and clock B 420, an additional load is coupled to the variable signal. With the first falling edge of the clock A 410, the terminal 518 P1B stores a high level, and the terminal 519 P1 stores a low level. N-type transistor 611 is turned off, and n-type transistors 612 and 621 are turned on. Load Z0 610 is coupled to the variable signal and is also part of the circuit path between terminal 682 and output 690 via n-type transistors 621 and 612.

With the first falling edge of the clock B 420, the terminal 528P2B stores a low level, and the terminal 529P2 stores a low level. N-type transistor 621 is turned off, and n-type transistors 622 and 631 are turned on. The load Z1 620 is coupled to the variable signal and is also part of the electrical path between the terminal 682 and the output terminal 690 through the n-type transistors 631 and 622.

Along with the second falling edge of the clock A 410, the terminal 538P3B stores a high level, and the terminal 539P3 stores a low level. N-type transistor 631 is turned off, and n-type transistors 632 and 641 are turned on. Load Z2 630 is coupled to the variable signal and is also part of the circuit path between terminal 682 and output 690 via n-type transistors 641 and 632.

Along with the second falling edge of the clock B 420, the terminal 584P4B stores a high level, and the terminal 549P4 stores a low level. N-type transistor 641 is turned off, and n-type transistors 642 and 651 are turned on. Load Z3 640 is coupled to the variable signal and is also part of the electrical path between terminal 682 and output 690 via n-type transistors 651 and 642.

Along with the third falling edge of the clock A 410, the terminal 558P5B stores a high level, and the terminal 559P5 stores a low level. N-type transistor 651 is turned off, and n-type transistors 652 and 654 are turned on. Load Z4 650 is coupled to the variable signal and is also part of the circuit path between terminal 682 and output 690 via n-type transistors 654 and 652.

Please refer to FIG. 8A and FIG. 8B , which are diagrams showing voltage traces of variable signals at different temperatures and delay phenomena in a delay time range and temperature range. Fig. 8A shows the curves generated by the variable signal at three different temperatures. The ambient temperature corresponding to the curve 810 is -45 degrees Celsius. The ambient temperature corresponding to the curve 820 is 25 degrees Celsius. The ambient temperature corresponding to the curve 830 is 125 degrees Celsius. Curves 810 , 820 and 830 substantially intersect at point 840 . The time period for determining the delay phenomenon starts from the start signal and ends at the intersection of multiple curves corresponding to different ambient temperatures. Figure 8B shows the output curves 850 and 860 of the level detector. When the variable signal reaches a reference value at the corresponding temperature, the level detector generates an output signal. In Figures 8A and 8B, the time interval ends at point 840, and the state of the level detector output at point 840 transitions for about 70 nanoseconds.

FIG. 9 is a flow chart of an embodiment for generating a delay phenomenon in a delay time range and a temperature range. In step 910, a start signal is received. In step 920, a variable signal is generated. In step 930, a signal edge of a clock signal is generated. In step 940, an additional impedance is coupled to the main function block. In steps 920, 930 and 940, the main function block acts after receiving the start signal. Therefore, the time at which the temperature compensation signal is generated is independent of the time at which the output signal is generated by the main function block. In step 960, wait for the variable signal to reach a reference level. At step 970, a signal is generated following the initial signal with a delay in the delay time range and temperature range. In step 980, after the initial signal, a signal is generated in a temperature independent delay phenomenon, for example, a sense amplifier generates a signal. At step 990, the temperature compensation function is stopped.

In summary, although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Changes and modifications, so the protection scope of the present invention should be defined by the scope of the appended claims.

Claims (47)

1. a method that produces temperature compensation signal is used for being used for this integrated circuit when using integrated circuit, and this method comprises

The initial signal of corresponding very first time point produces a variable signal in the part of this integrated circuit, and this variable signal has the alterable features value;

At this integrated circuit clocking;

This clock signal is used for a plurality of loads of this integrated circuit;

To should clock signal, couple the additional impedance of described a plurality of loads this part with this variable signal to this circuit; And

When this alterable features value that should variable signal is risen to reference level, maybe when this alterable features value that should variable signal is dropped to this reference level, produce signal at second time point at this integrated circuit, the characteristic of this signal be by between this very first time point and this second time point time of delay scope and one of temperature range delay phenomenon determined.

2. method according to claim 1, wherein this signal provides sequential to induction amplifier.

3. method according to claim 1, wherein this Generation of Clock Signal speed is to accelerate along with decrease of temperature.

4. method according to claim 1, wherein this Generation of Clock Signal speed is to slow down along with the rising of temperature.

5. method according to claim 1, wherein when temperature descended, this Generation of Clock Signal speed rose, and the speed that this additional impedance is coupled to this clock signal rises.

6. method according to claim 1, wherein when temperature rose, this Generation of Clock Signal speed descended, and this additional impedance is coupled to the speed decline to this clock signal.

7. method according to claim 1, wherein should time of delay scope when the temperature range of 120 degree Celsius at least, be to be no more than a nanosecond.

8. method according to claim 1, wherein this alterable features value of this variable signal is to rise to this reference level.

9. method according to claim 1, wherein this alterable features value of this variable signal is a magnitude of voltage, this magnitude of voltage is to rise to this reference level.

10. method according to claim 1, wherein this alterable features value of this variable signal is to drop to this reference level.

11. method according to claim 1, wherein this alterable features value of this variable signal is a magnitude of voltage, and this magnitude of voltage is to drop to this reference level.

12. an integrated circuit (IC) apparatus comprises:

Circuit is used for producing a variable signal at the corresponding initial signal of very first time point, and this variable signal has an alterable features value;

Clock circuit is used for clocking;

A plurality of impedances couple with this clock circuit and this circuit, and described a plurality of impedances have a joiny impedance, and this joiny impedance corresponds to this clock signal and increases; And

Output is coupled to this circuit, and this output is exported a signal, the characteristic of this signal be by between this point and one second time point very first time one time of delay scope and the delay phenomenon that caused of a temperature range with the decision characteristic.

13. device according to claim 12, wherein this clock circuit comprises circular type shaker.

14. device according to claim 12, wherein when temperature descended, this clock circuit produced speeding up of this clock signal.

15. device according to claim 12, wherein when temperature rose, the speed that this clock circuit produces this clock signal slowed down.

16. device according to claim 12, wherein when temperature descended, the speed that this clock circuit produces this clock signal rose the rising that gathers way of this joiny impedance of described a plurality of impedances.

17. device according to claim 12, wherein when temperature rose, the speed that this clock circuit produces this clock signal descended the decline that gathers way of this joiny impedance of described a plurality of impedances.

18. device according to claim 12, wherein should time of delay this delay phenomenon of scope when the temperature range of 120 degree Celsius at least, be to be no more than a nanosecond.

19. device according to claim 12, wherein this device also comprises:

Control circuit, with this clock circuit and described a plurality of impedance coupling, when this clock circuit receives this clock signal and exports a plurality of control signals, described a plurality of control signals are along this joiny impedance that increases described a plurality of impedances to signal that should clock signal.

20. device according to claim 12, wherein this device also comprises:

Control circuit, this control circuit are to be coupled to this clock circuit and described a plurality of impedance, and this clock circuit receives this clock signal and exports a plurality of temperature compensation signals increases this joiny impedances of described a plurality of impedances with corresponding each this temperature compensation signal,

Wherein, a plurality of nmos pass transistors that this control signal conducting electrically connects this variable signal and described a plurality of impedance, this signal is to produce after this alterable features value of this variable signal rises to reference level.

21. device according to claim 12, wherein this device also comprises:

Control circuit, this control circuit is to be coupled to this clock circuit and described a plurality of impedance, this clock circuit is to receive this clock signal and export a plurality of control signals, described a plurality of control signals be to should clock signal to increase this joiny impedance of described a plurality of impedances.

Wherein, a plurality of PMOS transistors that this control signal conducting electrically connects this variable signal and described a plurality of impedance, this signal is to produce after this alterable features value of this variable signal drops to reference level.

22. device according to claim 12, wherein this device also comprises:

Level detector couples with described a plurality of impedances and this output, and this level detector is used for producing this signal when this alterable features value of this variable signal rises to reference level.

23. device according to claim 22, wherein, this alterable features value is to be a variable voltage.

24. device according to claim 12, wherein this device also comprises:

Level detector couples with described a plurality of impedances and this output, and this level detector is used for producing this signal when this change characteristic of this variable signal drops to reference level.

25. device according to claim 24, wherein, this alterable features value is to be a variable voltage.

26. device according to claim 12, wherein this device also comprises:

Storage array; And

Induction amplifier, this induction amplifier system couples with this storage array;

Wherein, this output is coupled to this induction amplifier, to provide sequential to this induction amplifier.

27. a method of making integrated circuit (IC) apparatus comprises:

Semiconductor substrate is provided;

Form circuit, the very first time corresponding to initial signal load one variable signal, this variable signal is to have the alterable features value;

On this semiconductor substrate, form clock circuit with clocking;

Form a plurality of impedances on this semiconductor substrate, described a plurality of impedances are to couple with this clock circuit and this circuit, and described a plurality of impedances are to have a joiny impedance to increase corresponding to this clock signal; And

On this semiconductor substrate, form output, this output is to be coupled to this circuit, this output is in the second time point output signal, the characteristic of this signal be since between this very first time point and this second time point one time of delay scope and a delay phenomenon of a temperature range determine.

28. method according to claim 27, this method also comprises:

Select described a plurality of impedance to make this of scope of this delay phenomenon is constant in this temperature range time of delay, and the minimum value of this temperature range is to be 120 degree.

29. method according to claim 27, this method also comprises:

Select described a plurality of impedance to make this of scope of this delay phenomenon, be to be no more than for 1 nanosecond in the change of this temperature range time of delay, and the minimum value of this temperature range is to be 120 degree.

30. method according to claim 27, wherein this clock circuit comprises circular type shaker.

31. method according to claim 27, wherein to produce the speed of this clock signal be to accelerate along with decrease of temperature to this clock circuit.

32. method according to claim 27, wherein to produce the speed of this clock signal be to reduce along with the rising of temperature to this clock circuit.

33. method according to claim 27, wherein when temperature descended, this clock circuit produced speeding up of this clock signal, the quickening that gathers way of this joiny impedance of described a plurality of impedances.

34. method according to claim 27, wherein when temperature rose, the speed that this clock circuit produces this clock signal slowed down, and gathering way of this joiny impedance of described a plurality of impedances slowed down.

35. method according to claim 27, wherein this delay phenomenon this time of delay scope change when this temperature ranges of at least 120 degree, be no more than for 1 nanosecond.

36. method according to claim 27, this method also comprises:

Form control circuit, this control circuit is and this clock circuit and described a plurality of impedance coupling, this control circuit receives this clock signal and exports a plurality of temperature compensation signals, and described a plurality of temperature compensation signals are along to increase this joiny impedance of described a plurality of impedances to each signal that should clock signal.

37. method according to claim 27, this method also comprises:

Form control circuit, this control circuit is and this clock circuit and described a plurality of impedance coupling, this control circuit receives a clock signal and exports a plurality of temperature compensation signals, and described a plurality of temperature compensation signals are along to increase this joiny impedance of described a plurality of impedances to each signal that should clock signal;

Wherein, this control signal is the nmos pass transistor that conducting electrically connects described a plurality of impedance and this variable signal, and this signal is to produce when this alterable features value of this variable signal rises to reference level.

38. method according to claim 27, this method also comprises:

Form control circuit, this control circuit is to be coupled to this clock circuit and described a plurality of impedance, this clock circuit receive clock signal and export a plurality of temperature compensation signals, described a plurality of temperature compensation signals are that corresponding each this temperature compensation signal is to increase this joiny impedance of described a plurality of impedances;

Wherein, this control signal is the PMOS transistor that conducting electrically connects described a plurality of impedance and this variable signal, and this signal is to produce when this alterable features value of this variable signal drops to reference level.

39. method according to claim 27, this method also comprises:

Form level detector, this level detector is to be coupled to described a plurality of impedance and this output, and this level detector is to produce this signal after this alterable features value of this variable signal rises to reference level.

40. according to the described method of claim 39, wherein, this alterable features value is to be variable voltage.

41. method according to claim 27, this method also comprises:

Form level detector, this level detector is to be coupled to described a plurality of impedance and this output, and this level detector is to produce this signal after this alterable features value of this variable signal drops to reference level.

42. according to the described method of claim 41, wherein, this alterable features value is to be variable voltage.

43. method according to claim 27, this method also comprises:

Form storage array; And

Form induction amplifier, this induction amplifier is to be coupled to this storage array;

Wherein, this output is coupled to this sensing amplifier, to provide sequential to this induction amplifier.

44. a method that produces the temperature-compensating output of integrated circuit, this method comprises:

Put the initial signal of an integrated circuit corresponding to the very first time, trigger first circuit (120 of this integrated circuit; 240-250) to carry out the principal function of this first circuit, reach and produce the principal function output signal;

Trigger the second circuit (130 of this integrated circuit; 210-220) to produce secondary signal in second time point, this secondary signal is that scope time of delay between this very first time point and this second time point produces delay phenomenon, and wherein this delay phenomenon is irrelevant with this principal function output; And

Allow this principal function output signal behind this delay phenomenon, by other circuit (140 of this integrated circuit; 230).

45. according to the described method of claim 44, wherein be by to should the start signal triggers clock signal to control this delay phenomenon, so that this delay phenomenon and the output of this principal function are irrelevant.

46. an integrated circuit (IC) apparatus comprises:

First circuit (120; 240-250), corresponding to the initial signal of very first time point, carry out the principal function of this first circuit and produce the principal function output signal;

Second circuit (130; 210-220), to should initial signal producing secondary signal in second time point, this secondary signal is that scope time of delay between this very first time point and this second time point produces delay phenomenon, and wherein this delay phenomenon is irrelevant with this principal function output; And

Tertiary circuit (140; 230), this tertiary circuit is to be coupled to this first circuit and this second circuit, and this tertiary circuit is to receive this principal function output signal and this secondary signal, and allows this principal function output signal other circuit by this integrated circuit behind this delay phenomenon.

47. according to the described device of claim 46, this device also comprises:

Clock circuit is used for clocking, and this clock signal is to should initial signal being triggered, and wherein is that this clock signal control lag phenomenon of mat is so that this delay phenomenon and the output of this principal function are irrelevant.

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