CN1702588A - voltage regulator - Google Patents

Abstract

The present invention discloses a voltage regulating device, comprising: an operational amplifier, comprising a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the operational amplifier is connected to a reference voltage; a current mirror, comprising a reference terminal and a mirror terminal; and a first transistor, wherein the gate terminal of the first transistor is connected to the output terminal of the operational amplifier, the source terminal is connected to the reference terminal of the current mirror, and the drain terminal is connected to the positive input terminal of the operational amplifier.

Description

voltage regulator

technical field

The present invention relates to a voltage regulating circuit, in particular to a voltage regulating circuit capable of adjusting the output voltage.

Background technique

A voltage regulator (Power Regulator) usually provides a power output based on a reference voltage source (Reference Voltage) and compares it with an operational amplifier (Operational Amplifier). Please refer to FIG. 1 , which is a circuit diagram of a voltage regulating device 1 in the prior art. The voltage regulating device 1 includes an operational amplifier 2 whose output terminal is connected to the gate of a PMOS transistor _P1 , the negative input terminal is connected to a reference voltage V _BG , the positive input terminal is connected to a resistor R at node B, and the drain of a PMOS transistor _P2 The pole is connected to the output terminal of the operational amplifier and the gate of the PMOS transistor _P1 ; wherein the source of the PMOS transistor _P1 is connected to a voltage source Vdd, and the drain is connected to the ground terminal through a node B in series with a resistor R, and the PMOS transistor _P2 Used to reset (Reset) voltage regulator circuit.

When the operational amplifier 2 receives the reference voltage V _BG at its negative input terminal, it will pull up the voltage V _A (the voltage on the resistor R) at the positive input terminal of the operational amplifier to be the same as the reference voltage V _BG , so that The voltage at its output terminal decreases and generates a voltage difference with Vdd to drive the PMOS transistor P ₁ to conduct and generate a current I ₁ to obtain the output voltage V _OUT =I ₁ ×R, and the value of the output voltage V _OUT It is the same as the voltage VA input to the positive input terminal of the operational amplifier, and VBG=VA, so the output voltage V _OUT is the same as the reference voltage V _BG .

In this circuit, a MOS transistor with a fixed band gap is usually used to provide the reference voltage V _BG . The advantage is that the power provided is relatively stable, but it cannot provide a large current; Provide a larger current at the output terminal, and use the operational amplifier 2 as a unit gain buffer (Unit Gain Buffer), compare V _BG and _VA to drive the MOS transistor, and provide an output voltage VOUT, but its The final limit is V _BG =V _OUT .

Please refer to FIG. 2 , which is a circuit diagram of another voltage regulating device 10 in the prior art. The voltage regulating device 10 includes an operational amplifier 12 whose output terminal is connected to the gate of a PMOS transistor _P1 , the negative input terminal is connected to a reference voltage V _BG , the positive input terminal is connected to two resistors _R1 and _R2 at node B, and a PMOS transistor The drain of _P2 is connected to the output terminal of the operational amplifier and the gate of the PMOS transistor _P1 , wherein the gate of the PMOS transistor _P1 is connected to the output terminal of the operational amplifier, and the source is sequentially connected in series with a resistor _R1 and A resistor _R2 is connected to the ground terminal, and the serial connection point B of the resistor _R1 and the resistor _R2 is coupled to the positive input terminal of the operational amplifier.

When the operational amplifier 12 receives the reference voltage V _BG at its negative input terminal, it will pull up the voltage V _A at the positive input terminal of the operational amplifier to be the same as the reference voltage V _BG , so that the output terminal output is zero, To drive the PMOS transistor P ₁ to turn on, generate a current I ₁ , and obtain an output voltage V _OUT =I ₁ ×(R ₁ +R ₂ ), and the voltage V _B at the serial connection of the resistors R ₁ and R ₂ =I ₁ ×R ₂ =V _A , and V _A is equal to V _BG , that is, V _A =V _BG =I ₁ ×R ₂ , I ₁ =V _BG /R ₂ , so the output voltage V _OUT =I ₁ ×(R ₁ +R ₂ )=V _BG ×(R ₁ +R ₂ )/R ₂ .

In this circuit, the problem that the output voltage of the above-mentioned known technology is finally limited to V _BG =V _OUT can be effectively solved. The output voltage V _OUT is generated by adjusting the resistance of R ₁ and R ₂ , but the resistance of R ₁ and R ₂ is in the chip In order to achieve its accuracy, resistors made of polysilicon are generally used to obtain a better ratio of resistor combinations. Usually, the resistance values of R ₁ and R ₂ will reach about several thousand ohms, and R ₁ will form a large load for negative feedback. In some cases, the system may even fail, and the output terminal will be connected to many different circuits, which will cause the load in the negative feedback loop to be variable and unstable, thus causing system instability.

Therefore, how to effectively provide a stable power output without increasing the load of the negative feedback loop in the known technology voltage regulating device, so as to make the system more stable, is a problem we want to improve.

Contents of the invention

Therefore, the present invention provides a voltage regulation circuit for providing a stable output voltage.

The invention provides a voltage regulating circuit, which can adjust the output voltage through the width/length ratio of the transistor channel in the current mirror and the resistance, and improve the loop gain of the negative feedback loop.

The invention discloses a voltage regulating device, comprising: an operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the operational amplifier is connected to a reference voltage V _BG ; a current mirror, comprising a A reference terminal and a mirror terminal, the reference terminal is connected in series with a first transistor, a first resistor _R1 to the ground terminal, and the mirror terminal is connected in series with a second resistor _R2 to the ground terminal; the first transistor, the first The gate terminal of the transistor is connected to the output terminal of the operational amplifier, the source terminal is connected to the reference terminal of the current mirror, and the drain terminal is connected to the positive input terminal of the operational amplifier and the first resistor R ₁ ; and a second transistor, the source terminal of which is connected to a The voltage source and the drain are connected to the output terminal of the operational amplifier and the gate of the first transistor.

Therefore, when the operational amplifier compares the reference voltage with the voltage on the first resistor R ₁ , the operational amplifier outputs the difference between the two to drive the first transistor to generate the reference current I ₁ of the current mirror, and maps the reference current I ₁ to mirror terminal to obtain a mirror current I ₂ , and the output terminal of the voltage regulator is the mirror terminal of the current mirror connected in series with the second resistor R ₂ , so that a stable output voltage V _OUT =I amplified by the current mirror can be obtained ₂ ×R ₂ ＝V _BG ×(R ₂ *(W/L) _{reference terminal} /R ₁ *(W/L) _{mirror terminal} ), where (W/L) _{reference terminal} and (W/L) _{mirror terminal} are respectively The channel width/length ratio of the reference and mirror transistors.

By adding a current mirror to the voltage regulator circuit, the resistor originally connected to the circuit of the operational amplifier is connected to the mirror terminal of the current mirror. Therefore, the size of the mirror current can be determined by adjusting the ratio of the transistor channel width/length or resistance , and then determine the magnitude of the output voltage, which can solve the decrease of the loop gain and the instability of the circuit caused by the resistance connected to the negative loop in the known technology.

Description of drawings

Fig. 1 is the circuit diagram of the voltage regulating device of known technology;

Fig. 2 is a circuit diagram of another voltage regulating device of the known technology; and

FIG. 3 is a circuit diagram of a voltage regulating device according to a preferred embodiment of the present invention.

Description of main component symbols

I ₁ reference current I ₂ mirror current

V _BG reference voltage V _OUT voltage regulator circuit output terminal

V _A op amp positive input node voltage

V _B node voltage (where resistors R ₁ and R ₂ are connected in series in Figure 2)

1, 10, 20 voltage regulator

2, 12, 22 operational amplifiers

R ₁ , R ₂ resistance

P ₁ , P ₂ , P ₃ , P ₄ PMOS transistors

Detailed ways

Please refer to FIG. 3 , which shows a voltage regulating circuit of the present invention. A voltage regulating device 20 at least includes a current mirror 24, an operational amplifier 22, a first resistor R ₁ , a second resistor R ₂ , a first PMOS transistor P ₁ , and a second PMOS transistor P ₂ . The reference terminal of the current mirror 24 is sequentially connected to the first PMOS transistor _P1 , the first resistor _R1 is connected to the ground terminal, and its mirror terminal is connected in series to the second resistor R2 to the ground terminal, wherein the current mirror 24 is composed of two common gates Composed of PMOS transistors P3 and P4, the sources of the transistors P3 and P4 are commonly connected to a voltage source Vdd, and the drain of the transistor P3 is simultaneously coupled to its own gate and connected to the source of the first PMOS transistor P1 At the node C, the drain of the transistor P4 is connected in series with the second resistor R2 through the node D to the ground terminal, and the node D is the output terminal of the voltage regulating device 20 .

Operational amplifier 22, its negative input terminal is connected to a reference voltage VBG, its positive input terminal is connected to the first resistor R1 and the drain of the first PMOS transistor P1, and its output terminal is connected to the gate of the first PMOS transistor P1 and the second PMOS transistor P2 The drain of the operational amplifier 22, wherein the output signal of the output terminal of the operational amplifier 22 is used to drive the first PMOS transistor P1, and the drain of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1 for reset (Reset) voltage regulation device.

When the operational amplifier 22 compares the reference voltage VBG at its negative input terminal with the voltage VA at the positive input terminal (i.e. the voltage on the resistor R1), it will pull up the voltage VA at the positive input terminal to be the same as the reference voltage VBG, so that the input and output terminals of the operational amplifier 22 The voltage decreases and generates a voltage difference with Vdd to drive the first PMOS transistor P1 to turn on, to generate the reference current I1 of the current mirror 24, and a voltage VB=I1×R1=VA will be obtained at the node B, and the voltage VA and VBG The same, that is, VBG=VA=I1×R1, I1=VBG/R1, wherein the reference current I1 is the current when the PMOS transistor P3 in the current mirror is turned on, and the mirror current I2 in the current mirror belongs to the conduction of another PMOS transistor _P4 The passing current is proportional to the reference current I1, that is, I2=I1×(W/L) _P4 /(W/L) _P3 (W/L is the channel width/length ratio of the transistor), which can be adjusted by adjusting the two The channel width/length ratio of the transistors P3 and P4 can amplify the current I2, and the current I2 is a key factor for determining the output voltage.

The output terminal of the voltage regulator 20 is the place D where the mirror terminal of the current mirror 24 is connected in series with the second resistor R2, so the output voltage is the voltage on the resistor R2, and its value is determined by the resistance value of R2 and the magnitude of the current I2, thus the voltage can be obtained The value of the output voltage of the regulator VOUT=I2×R2=I1×(W/L) _P4 /(W/L) _P3 ×R2=VBG×(R2*(W/L) _P4 /R1*(W/L) _P3 ), that is, we can enlarge or reduce the current I2 by adjusting the ratio of the channel width/length of the transistors P ₃ and P ₄ to make the output voltage greater or less than the reference voltage VBG, or adjust the resistors R1 and R2 to enlarge or reduce the output voltage value V _OUT .

Advantages of the present invention:

a. In the known technology, many different circuits are externally connected to its output terminal and the resistance in the negative feedback loop formed by the operational amplifier will cause the reduction and instability of the loop gain; however, the present invention utilizes adding a current mirror to the voltage regulator device In the middle, the output terminal of the voltage regulator and the resistance in the circuit are moved to the mirror terminal of the current mirror in series with , so that we can still determine the output voltage value by adjusting the ratio of the resistors R1 and R2, and the output terminal is connected to the resistor R2 and There is no direct connection relationship between the current mirror connection and the negative feedback circuit formed by the operational amplifier, and its external circuit and impedance value no longer affect the loop gain, and also solve the problems of the known technology.

b. The current mirror added by the present invention is in the voltage regulating device circuit, so that we can change the mirror current I2 by adjusting the channel width/length ratio of the two transistors in the current mirror, and then determine the output voltage of the voltage regulating device circuit size, and the output voltage obtained through the current mirror is a stable voltage.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is as defined by the appended claims.

Claims (9)

1. voltage regulating device includes:

One operational amplifier, this operational amplifier includes a positive input terminal, a negative input end and an output terminal, wherein the negative input end of this operational amplifier connects a reference voltage;

One current mirror, this current mirror include a reference edge and a mirror image end; And

One the first transistor, the gate terminal of this first transistor is connected with the output terminal of this operational amplifier, and source terminal is connected to the reference edge of this current mirror, and drain electrode end is connected to the positive input terminal of this operational amplifier.

2. voltage regulating device as claimed in claim 1, wherein also include a transistor seconds, wherein the source terminal of this transistor seconds connects a voltage source, and drain electrode end is connected to the gate terminal of positive input terminal and this first transistor of this operational amplifier, in order to this voltage adjusting device of resetting.

3. voltage regulating device as claimed in claim 2, wherein this first transistor and this transistor seconds are the P-type mos transistor.

4. voltage regulating device as claimed in claim 1 wherein also includes one first resistance, and this first resistance is connected between the drain electrode end and earth terminal of this first transistor.

5. voltage regulating device as claimed in claim 1, wherein this current mirror has one the 3rd transistor and one the 4th transistor, the 3rd transistorized gate terminal is connected with the 4th transistorized gate terminal, the 3rd transistorized source terminal is connected with the 4th transistorized source terminal and is connected to this voltage source again, the 3rd transistor drain end is connected with the source terminal of this transistor seconds, and the 3rd transistor drain end coupling knot is to the 3rd transistorized gate terminal.

6. voltage regulating device as claimed in claim 5, wherein the 3rd transistor and the 4th transistor are the P-type mos transistor.

7. voltage regulating device as claimed in claim 5 wherein can pass through adjustment the 3rd and the 4th transistorized raceway groove width/length ratio, and obtains the output voltage of different these voltage regulating devices.

8. voltage regulating device as claimed in claim 1 wherein also comprises one second resistance, and this second resistance is connected between the 4th transistor drain end and the earth terminal.

9. voltage regulating device as claimed in claim 1, wherein also comprise this first resistance and this second resistance, this first resistance is connected between the drain electrode end and earth terminal of this first transistor, this second resistance is connected between the 4th transistor drain end and the earth terminal, can by adjust this first with the resistance value ratio of this second resistance, and obtain the output voltage of different these voltage regulating devices.

Images