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CN1791300B - Multi-layered circuit board and manufacturing method of multi-layered circuit board - Google Patents

Multi-layered circuit board and manufacturing method of multi-layered circuit board Download PDF

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Publication number
CN1791300B
CN1791300B CN2005101301562A CN200510130156A CN1791300B CN 1791300 B CN1791300 B CN 1791300B CN 2005101301562 A CN2005101301562 A CN 2005101301562A CN 200510130156 A CN200510130156 A CN 200510130156A CN 1791300 B CN1791300 B CN 1791300B
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Prior art keywords
conductive layer
hole
detection
circuit board
multilayer circuit
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CN1791300A (en
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金谷保彦
入江明
长沢胜浩
结城彻
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Via Mechanics Ltd
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Hitachi Via Mechanics Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0268Marks, test patterns or identification means for electrical inspection or testing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/092Exposing inner circuit layers or metal planes at the walls of high aspect ratio holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718Clearance holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845Stepped hole, via, edge, bump or conductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0242Cutting around hole, e.g. for disconnecting land or Plated Through-Hole [PTH] or for partly removing a PTH
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/163Monitoring a manufacturing process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17Post-manufacturing processes
    • H05K2203/175Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047Drilling of holes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322Composite web or sheet
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

提供了一种多层电路板及其制造方法,其使得能够适当地安装电子部件并且不会妨碍所述电子部件的性能。要安装在多层电路板的表面上的电子部件的电源端子(引脚)插入到被镀通孔中以与第一导电层连接。检测部提供在第一导电层的背部的第二导电层上,所述检测部具有与所述通孔同轴地形成并且直径大于所述通孔的直径的检测孔。一具有大直径的孔从所述背部沿着所述通孔借助于工具、同时在第二导电层和所述工具之间施加电压而形成。所述孔的深度基于使所述工具与检测孔电导通而设置。通孔的不必要的镀层可以通过大孔去除。

Figure 200510130156

Provided are a multilayer circuit board and a method of manufacturing the same, which enable proper mounting of electronic components without hindering the performance of the electronic components. Power supply terminals (pins) of electronic components to be mounted on the surface of the multilayer circuit board are inserted into the plated through holes to be connected with the first conductive layer. A detection portion is provided on the second conductive layer on the back of the first conductive layer, the detection portion having a detection hole formed coaxially with the through hole and having a diameter larger than that of the through hole. A hole with a large diameter is formed from the back along the through hole by means of a tool while applying a voltage between the second conductive layer and the tool. The depth of the hole is set based on electrically conducting the tool with the detection hole. Unnecessary plating of through holes can be removed through large holes.

Figure 200510130156

Description

多层电路板及其制造方法 Multilayer circuit board and its manufacturing method

技术领域technical field

本发明涉及一种多层电路板,其通过将由导电层和绝缘层组成的多个基板叠加为一体而形成,并且涉及该多层电路板的制造方法。 The present invention relates to a multilayer circuit board formed by stacking a plurality of substrates composed of conductive layers and insulating layers into one body, and to a method for manufacturing the multilayer circuit board. the

背景技术Background technique

常规情况下,为了钻一通过多层电路板的孔,已经存在一种检测要被机加工的点的表面高度以及基于该检测高度将该孔钻到指定深度的技术,如在日本专利公开号2001-341052中所公开的。其提高了要被机加工的孔的深度的精度。但是,由于多层电路板的厚度的变化,通过此方法不总是有可能稳定地形成用于连接上和下导电层的盲孔。 Conventionally, in order to drill a hole through a multilayer circuit board, there has been a technique of detecting the surface height of a point to be machined and drilling the hole to a specified depth based on the detected height, as described in Japanese Patent Laid-Open No. published in 2001-341052. It improves the accuracy of the depth of the hole to be machined. However, due to variations in the thickness of the multilayer circuit board, it is not always possible to stably form blind holes for connecting upper and lower conductive layers by this method. the

随后,已经提供了一种预先在每个层压的导电层中提供测量区域、在钻孔之前暴露每个测量区域、以及在确认高度方向上工具的位置时钻孔的技术,如在日本专利公开号2004-63771中所公开的。其允许用于连接上和下导电层的盲孔被稳定地形成。 Subsequently, there has been proposed a technique of providing a measurement area in advance in each laminated conductive layer, exposing each measurement area before drilling, and drilling a hole while confirming the position of the tool in the height direction, as in Japanese Patent Disclosed in Publication No. 2004-63771. It allows blind holes for connecting upper and lower conductive layers to be stably formed. the

顺便而言,电子部件如IC封装的电源端子(电源引脚),例如一引脚,在将该IC封装安装在多层电路板上时与所需导电层连接如下。即,达到所需导电层的孔是从多层基板的表面钻的并且镀被执行以在该孔的内面上形成镀层。随后,电源端子(引脚)或者类似物被插入该孔并且焊接被执行从而以所述镀孔为媒介将电源端子(引脚)与所需导电层电连接。 Incidentally, a power supply terminal (power supply pin) of an electronic part such as an IC package, for example a pin, is connected to a required conductive layer when the IC package is mounted on a multilayer circuit board as follows. That is, a hole to reach a desired conductive layer is drilled from the surface of the multilayer substrate and plating is performed to form a plated layer on the inner face of the hole. Then, a power supply terminal (pin) or the like is inserted into the hole and soldering is performed to electrically connect the power supply terminal (pin) with a desired conductive layer through the plated hole. the

图4是常规多层电路板的截面图。 Fig. 4 is a sectional view of a conventional multilayer circuit board. the

图中所示的多层电路板1形成如下。即,多层电路板1是通过顺序地层压由彼此组合的导电层2a和绝缘层2b组成的第三基板2,由彼此组合的导电层3a和3c和绝缘层3b组成的第二基板3,由彼此组合的导电层4a和绝缘层4b组成的第一基板4,以及由彼此组合的导 电层5a和绝缘层5b组成的表面基板5,借助于粘合剂以及通过热处理将它们彼此组合而形成的。这里,尽管电路图案形成在导电层3a,3c和4a即内部层压层上,存在电路图案被形成以及没有电路图案被形成在表面导电层5a和背部导电层2a上的情况。在第二基板3的情况中,导电层3a以通过镀而形成在连接孔6上的镀层7为媒介与导电层3c’电连接。 The multilayer circuit board 1 shown in the figure is formed as follows. That is, the multilayer circuit board 1 is formed by sequentially laminating the third substrate 2 composed of the conductive layer 2a and the insulating layer 2b combined with each other, the second substrate 3 composed of the conductive layers 3a and 3c and the insulating layer 3b combined with each other, The first substrate 4 composed of the conductive layer 4a and the insulating layer 4b combined with each other, and the surface substrate 5 composed of the conductive layer 5a and the insulating layer 5b combined with each other are formed by combining them with each other by means of an adhesive and by heat treatment. Forming. Here, although circuit patterns are formed on the conductive layers 3a, 3c, and 4a, ie, the inner laminate layer, there are cases where circuit patterns are formed and no circuit patterns are formed on the surface conductive layer 5a and the back conductive layer 2a. In the case of the second substrate 3, the conductive layer 3a is electrically connected to the conductive layer 3c' via the plating layer 7 formed on the connection hole 6 by plating. the

接下来,用于将电子部件的电源端子,如引脚与所需导电层(图4情形中的第一导电层4a)连接的孔8是从用于安装电子部件如IC封装的侧(下文中称为表面侧)来钻的。另外,如果有必要,钻一用于将表面导电层5a和/或背部导电层2a与内导电层3a和3c连接的连接孔。 Next, holes 8 for connecting power supply terminals of electronic components such as pins to the desired conductive layer (first conductive layer 4a in the case of FIG. In this paper, it is called the surface side) to drill. In addition, if necessary, a connection hole for connecting the surface conductive layer 5a and/or the back conductive layer 2a with the inner conductive layers 3a and 3c is drilled. the

随后,紧接着在电路图案形成在表面侧的导电层5a以及与表面侧相对的背侧的导电层2a上时,或者在没有电路图案形成在导电层5a和2a上时通过蚀刻来形成电路图案之后,通过对电源馈送连接孔(图4中未示)的内部进行镀来形成镀层9,所述电源馈送连接孔将表面导电层5a和/或背部导电层2a与内导电层3a和3c连接。 Subsequently, the circuit pattern is formed by etching immediately after the circuit pattern is formed on the conductive layer 5 a on the surface side and the conductive layer 2 a on the back side opposite to the surface side, or when no circuit pattern is formed on the conductive layers 5 a and 2 a Thereafter, the plated layer 9 is formed by plating the inside of the power feed connection hole (not shown in FIG. 4 ) connecting the surface conductive layer 5a and/or the back conductive layer 2a with the inner conductive layers 3a and 3c . the

尽管所述镀在正常情况下是在足够的控制下进行的,存在孔8底部处的镀层9的厚度变得太厚、或者孔8底部处的镀层9的直径与入口侧的相比变小的情况,如图中所示。当这样形成镀层9时,存在电源端子的边缘不能插入所需深度并且电子部件出现在多层电路板1的表面之上的情况。如果电子部件出现在多层电路板的表面之上,则电源端子(引脚)容易由于震动等被损坏,从而降低其可靠性。另外,出现这样的问题,即如果作为结合电子部件的产品的多层电路板的外部尺度变大,其可能不被存储在使用该多层电路板的电子设备内。 Although the plating is normally carried out under sufficient control, there is a case where the thickness of the plating layer 9 at the bottom of the hole 8 becomes too thick, or the diameter of the plating layer 9 at the bottom of the hole 8 becomes smaller compared with that on the inlet side situation, as shown in the figure. When the plating layer 9 is thus formed, there are cases where the edges of the power supply terminals cannot be inserted to a desired depth and electronic components appear above the surface of the multilayer circuit board 1 . If the electronic parts are present on the surface of the multilayer circuit board, power supply terminals (pins) are easily damaged by vibration or the like, thereby reducing their reliability. In addition, there arises a problem that if the external dimensions of a multilayer circuit board as a product incorporating electronic components become large, it may not be stored in an electronic device using the multilayer circuit board. the

在此情形中,可以设想通过形成孔8作为通孔而避免镀层厚度的分散或者局部增加。但是如果此通孔接近于背侧的电路图案而形成,存在这样的情形,即电子部件由于噪声而导致误操作,所述噪声是由 它们之一者对另一者导致的电磁效应的结果。因此,在镀之后、在用于定位电源端子的孔8被形成为通孔时去除不必要的镀层是必要的。 In this case, it is conceivable to avoid dispersion or local increase in plating thickness by forming the hole 8 as a through hole. But if this via hole is formed close to the circuit pattern on the back side, there are cases where electronic parts cause malfunction due to noise that is the result of electromagnetic effect caused by one of them to the other. Therefore, it is necessary to remove unnecessary plating when the holes 8 for positioning the power supply terminals are formed as through holes after plating. the

但是,通过日本专利公开号2004-63771的技术不能精确地去除不必要的镀层,因为在去除不必要的镀层时,工具通过镀层与所需导电层电导通。 However, unnecessary plating cannot be accurately removed by the technique of Japanese Patent Laid-Open No. 2004-63771 because the tool is electrically connected to a desired conductive layer through the plating when removing the unnecessary plating. the

因此,本发明的一个目的是提供一种多层电路板及其制造方法,其使电子部件能够被适当地安装并且不会妨碍电子部件的性能。该目的可通过组合在本发明独立权利要求中描述的特征来实现。其从属权利要求规定本发明的优选实施例。 Accordingly, an object of the present invention is to provide a multilayer circuit board and a method of manufacturing the same, which enable electronic components to be properly mounted without hindering the performance of the electronic components. This object is achieved by combining the features described in the independent claims of the invention. The dependent claims define preferred embodiments of the invention. the

发明内容Contents of the invention

为了解决上面提到的问题,根据本发明的第一方面,提供了一种多层电路板,其通过层压和组合由导电层和绝缘层组成的多个基板而形成,具有:通孔,其从多层电路板的表面穿通到其背面,同时与设置在位于所述表面上的基板的表面上的表面导电层接触,以及与位于表面导电层之下和之内的第一导电层接触;导电镀层,镀在该通孔的内周面上,以将表面导电层与第一导电层电连接;检测部,设置在第二导电层上,相对于第一导电层,所述第二导电层位于背面侧,并且具有检测孔,其与所述通孔同轴地形成并且其直径大于所述通孔的直径;以及大孔,其直径大于所述通孔的直径,其与所述通孔同轴地沿着所述通孔从所述背面到至少第二导电层形成,其中通过形成所述大孔,检测部的检测孔的部分被暴露于大孔。 In order to solve the above-mentioned problems, according to a first aspect of the present invention, there is provided a multilayer circuit board formed by laminating and combining a plurality of substrates composed of conductive layers and insulating layers, having: through holes, It penetrates from the surface of the multilayer circuit board to its back surface while making contact with the surface conductive layer provided on the surface of the substrate located on said surface, and with the first conductive layer located below and within the surface conductive layer ; The conductive plating layer is plated on the inner peripheral surface of the through hole to electrically connect the surface conductive layer with the first conductive layer; the detection part is arranged on the second conductive layer, and the second conductive layer is opposite to the first conductive layer. The conductive layer is located on the back side, and has a detection hole formed coaxially with the through hole and having a diameter larger than that of the through hole; A through hole is formed coaxially along the through hole from the back surface to at least the second conductive layer, wherein by forming the large hole, a portion of the detection hole of the detection portion is exposed to the large hole. the

从而,由于用于连接电子部件的电源端子的连接孔被形成为被镀通孔,并且达到检测孔的所述孔从多层电路板的背部沿着通孔得以形成,如以上所述,因此形成在通孔上的镀层可以被确切地去除。因此,变得有可能提供允许电子部件被适当地安装并且不会妨碍电子部件的工作的多层电路板。 Thus, since the connection hole for connecting the power supply terminal of the electronic part is formed as a plated through hole, and the hole reaching the detection hole is formed along the through hole from the back of the multilayer circuit board, as described above, Plating formed on the through hole can be definitely removed. Therefore, it becomes possible to provide a multilayer circuit board that allows electronic components to be properly mounted and does not hinder the operation of the electronic components. the

作为多层电路板,这样的一个被使用,其具有:通孔,从多层电路板的表面穿通到其背面,同时与设置在位于所述表面上的基板的表面上的表面导电层接触,以及与位于表面导电层之下和之内的第一导电层接触;导电镀层,镀在所述通孔的内周面上,以将表面导电层与第一导电层电连接;以及检测部,设置在第二导电层上,从第一导电层,所述第二导电层位于背面侧,并且具有检测孔,其与通孔同轴地形成并且其直径大于通孔的直径,(例如如图1中所示)。 As a multilayer circuit board, such one is used, which has: a through hole penetrating from the surface of the multilayer circuit board to its back side while being in contact with a surface conductive layer provided on the surface of the substrate located on said surface, and in contact with the first conductive layer located under and within the surface conductive layer; a conductive plating layer plated on the inner peripheral surface of the through hole to electrically connect the surface conductive layer with the first conductive layer; and the detection part, Provided on the second conductive layer, from the first conductive layer, the second conductive layer is located on the back side, and has a detection hole, which is formed coaxially with the through hole and whose diameter is larger than the diameter of the through hole, (for example, as shown in shown in 1). the

所述多层电路板是中间产品,并且最终其变为其中形成大孔的多层电路板(见图3)。尽管其为中间产品,其作为产品从基板制造者被运送并且其在产品制造者处被制造为最终产品。 The multilayer circuit board is an intermediate product, and eventually it becomes a multilayer circuit board in which large holes are formed (see FIG. 3 ). Although it is an intermediate product, it is shipped as a product from a substrate manufacturer and it is manufactured as a final product at the product manufacturer. the

优选地,第一导电层是与具有表面导电层的表面基板相邻的第二基板的表面侧的导电层;并且第二导电层是与第二基板背侧相邻的第三基板的表面侧的导电层。 Preferably, the first conductive layer is the conductive layer on the surface side of the second substrate adjacent to the surface substrate having the surface conductive layer; and the second conductive layer is the surface side of the third substrate adjacent to the backside of the second substrate the conductive layer. the

根据本发明的第二方面,提供了一种制造多层电路板的方法,所述多层电路板是通过层压由导电层和绝缘层组成的多个基板形成的,通过它形成用于插入待安装在多层电路板上的电子部件的电源端子的连接孔,所述多层电路板具有在该多层电路板表面上的第一导电层,所述方法具有步骤:在第二导电层上形成具有检测孔的检测部,相对于第一导电层,所述第二导电层在背面侧;形成通孔,其从多层电路板的表面穿通到背面,同时与设置在位于所述表面的基板的表面上的表面导电层接触,以及与位于内部的第一导电层接触,并且通过具有比检测孔的直径小的直径而不与检测孔接触;镀所述通孔的内表面;以及从多层电路板的背侧沿着通孔、通过具有比检测孔直径大的直径的工具、同时在所述工具和其上提供有检测部的第二导电层之间施加预定电压、基于检测孔的检测另外钻一具有大直径和预定深度的孔,其中连接孔是通过表面导电层和第一导电层之间的通孔而形成的,其中所述镀被留在其内周面上;其中第一导电层是与具有表面导 电层的表面基板相邻的第二基板的表面侧的导电层;并且第二导电层是与第二基板背侧相邻的第三基板表面侧的导电层。 According to a second aspect of the present invention, there is provided a method of manufacturing a multilayer circuit board formed by laminating a plurality of substrates composed of conductive layers and insulating layers, by which a Connection holes for power supply terminals of electronic components to be mounted on a multilayer circuit board having a first conductive layer on the surface of the multilayer circuit board, the method having the steps of: A detection part with a detection hole is formed on the upper surface, and the second conductive layer is on the back side relative to the first conductive layer; a through hole is formed, which penetrates from the surface of the multilayer circuit board to the back surface, and at the same time is arranged on the surface of the multilayer circuit board. contacting the surface conductive layer on the surface of the substrate, and contacting the first conductive layer located inside, and not contacting the detection hole by having a diameter smaller than that of the detection hole; plating the inner surface of the through hole; and From the backside of the multilayer circuit board along the through hole, through a tool having a diameter larger than that of the detection hole, while applying a predetermined voltage between the tool and the second conductive layer on which the detection part is provided, based on the detection Detection of holes additionally drilling a hole having a large diameter and a predetermined depth, wherein the connection hole is formed through a through hole between the surface conductive layer and the first conductive layer, wherein the plating is left on the inner peripheral surface thereof; Wherein the first conductive layer is a conductive layer on the surface side of the second substrate adjacent to the surface substrate having the surface conductive layer; and the second conductive layer is a conductive layer on the surface side of the third substrate adjacent to the back side of the second substrate. layer. the

从而,允许电子部件被适当地安装并且不会妨碍电子部件的工作的多层电路板可以通过如下容易地形成:通过所述另外步骤沿着所述通孔从多层电路板的背部精确地到所述预定深度形成具有大直径的孔,以及通过精确地去除不必要的镀层,同时将用于连接电子部件的电源端子的连接孔形成为被镀通孔。 Thereby, a multilayer circuit board that allows electronic components to be properly mounted and does not hinder the operation of the electronic components can be easily formed by precisely extending from the back of the multilayer circuit board to the through hole through the additional step. The predetermined depth forms a hole having a large diameter, and simultaneously forms a connection hole for connecting a power supply terminal of an electronic part as a plated through hole by precisely removing unnecessary plating. the

所述另外步骤中的预定深度可以是基于电压成为预先设置的值或者以下时工具的位置而确定的深度。 The predetermined depth in the additional step may be a depth determined based on a position of the tool when the voltage becomes a preset value or less. the

因此可以精确地检测具有大直径以及由所述工具来钻的孔的深度,以及通过钻孔直到在所述工具和其上提供有检测部的第二导电层之间施加的电压变为预设值或以下时,稳定地形成具有大直径以及预定深度的孔。 It is therefore possible to accurately detect the depth of a hole having a large diameter and being drilled by the tool, and by drilling until the voltage applied between the tool and the second conductive layer on which the detection portion is provided becomes preset value or below, a hole having a large diameter and a predetermined depth is stably formed. the

多层电路板的制造方法还包括步骤:在所述连接通孔旁,在与具有检测部的第二导电层连接的位置钻一检测通孔,以及镀所述检测通孔的内面,其中在所述另外步骤中,所述预定电压以检测通孔的镀为媒介施加在具有检测部的第二导电层与该工具之间。 The manufacturing method of the multilayer circuit board further includes the steps of: beside the connection through hole, drilling a detection through hole at a position connected to the second conductive layer having the detection part, and plating the inner surface of the detection through hole, wherein In the further step, the predetermined voltage is applied between the second conductive layer having the detection portion and the tool via the plating of the detection via hole. the

经由镀所述检测通孔,通过设置测量探头等,具有检测部的第二导电层与该工具之间的电压可以被容易地测量,并且具有预定深度和大直径的孔可以被容易并精确地形成,而不需要用于暴露第二导电层的所需机加工。 By plating the detection through hole, the voltage between the second conductive layer having the detection portion and the tool can be easily measured by providing a measuring probe or the like, and a hole having a predetermined depth and a large diameter can be easily and accurately measured. formed without the required machining for exposing the second conductive layer. the

附图说明Description of drawings

图1是机加工过程期间被应用了本发明的多层电路板的截面图。 FIG. 1 is a cross-sectional view of a multilayer circuit board to which the present invention is applied during a machining process. the

图2是其上提供有检测部的本发明基板的平面图。 Fig. 2 is a plan view of a substrate of the present invention on which a detection portion is provided. the

图3是在安装电子部件之前刚刚被应用了本发明的多层电路板的截面图。 FIG. 3 is a cross-sectional view of a multilayer circuit board to which the present invention is applied immediately before electronic parts are mounted. the

图4是常规多层电路板的截面图。 Fig. 4 is a sectional view of a conventional multilayer circuit board. the

具体实施方式Detailed ways

现在将基于附图中所示的优选实施例来描述本发明,其不是旨在限制本发明而是示例本发明。所述实施例中描述的所有特征及其组合对本发明不必是基本的。 The invention will now be described based on preferred embodiments shown in the drawings, which are not intended to limit the invention but illustrate the invention. All features and combinations thereof described in the embodiments are not necessarily essential to the invention. the

图1是机加工过程期间被应用了本发明的多层电路板的截面图,图2是其上提供有检测部的基板的平面图以及图3是刚好在安装电子部件之前被应用了本发明的多层电路板的截面图。与图4中的那些相同的部分或者相同的功能将以相同的参考数字来标注,并且这里将省略对其的重复说明。 1 is a cross-sectional view of a multilayer circuit board to which the present invention is applied during a machining process, FIG. 2 is a plan view of a substrate on which a detection portion is provided, and FIG. 3 is a multilayer circuit board to which the present invention is applied just before mounting electronic components. A cross-sectional view of a multilayer circuit board. The same parts or the same functions as those in FIG. 4 will be denoted by the same reference numerals, and repeated description thereof will be omitted here. the

尽管在被形成为产品的时间点,图1所示的多层基板变得与图4中所示的多层电路板基本相同,但其与图4中所示的多层电路板的不同之处在于,用于插入电源端子的常规盲孔(图4中的孔8)被形成为通孔(其直径与孔8的直径相同),在于检测通孔23是新提供的并且在于提供了垫(pad)2ap1,2ap2以及5ap,即导电层。即,此多层基板1从其上安装电子部件的表面侧按顺序具有表面基板5、第一基板4、第二基板3以及在背部的第三基板2,这些基板被层压为一体。表面基板5具有用于连接孔的表面导电层5c,其与用于绝缘层5b的表面上的电路图案的表面导电层5a一起形成,并且第一基板4具有第一导电层4a,其形成在绝缘层4b的表面侧并且与所述连接孔连接。第二基板3具有形成在绝缘层3b的表面侧的第一导电层3c’和第二导电层3c,以及形成在绝缘层3b的背侧的导电层3a。导电层3c’和3a通过具有镀层7的连接孔6彼此电连接。第三基板2具有绝缘层2b的背部上的导电层2a。 Although the multilayer substrate shown in FIG. 1 becomes substantially the same as the multilayer circuit board shown in FIG. In that a conventional blind hole (hole 8 in FIG. 4 ) for inserting a power terminal is formed as a through hole (with the same diameter as hole 8 ), in that a detection through hole 23 is newly provided and in that a pad (pad) 2ap1, 2ap2 and 5ap, namely the conductive layer. That is, this multilayer substrate 1 has a surface substrate 5, a first substrate 4, a second substrate 3, and a third substrate 2 on the back in order from the surface side on which electronic components are mounted, and these substrates are laminated as one. The surface substrate 5 has a surface conductive layer 5c for connection holes formed together with a surface conductive layer 5a for circuit patterns on the surface of the insulating layer 5b, and the first substrate 4 has a first conductive layer 4a formed on the surface of the insulating layer 5b. The surface side of the insulating layer 4b is also connected to the connection hole. The second substrate 3 has a first conductive layer 3c' and a second conductive layer 3c formed on the surface side of the insulating layer 3b, and a conductive layer 3a formed on the back side of the insulating layer 3b. The conductive layers 3c' and 3a are electrically connected to each other through the connection hole 6 having the plating layer 7. As shown in FIG. The third substrate 2 has a conductive layer 2a on the back of an insulating layer 2b. the

注意,用于所述连接孔的表面导电层5c可以具有在其上形成的电路图案,或者可以类似于垫而专用于连接孔。其也可以是通过后面描述的镀过程形成的导电层。 Note that the surface conductive layer 5c for the connection hole may have a circuit pattern formed thereon, or may be dedicated to the connection hole like a pad. It may also be a conductive layer formed by a plating process described later. the

这将被按顺序说明。 This will be explained in order. the

如图1中所示,从多层电路板1的表面穿通到背部的通孔20被形成为与表面导电层5c和与连接孔连接的第一导电层4a接触,并且通孔的其内周面被镀,以形成镀层21。 As shown in FIG. 1, a through hole 20 penetrating from the surface of the multilayer circuit board 1 to the back is formed so as to be in contact with the surface conductive layer 5c and the first conductive layer 4a connected to the connection hole, and the inner periphery of the through hole The surface is plated to form a plated layer 21. the

如图2中所示,用于定位电子部件电源端子的通孔20(图4中的孔8)的轴线被假定为是O。具有与轴线O同轴并且其直径大于通孔20的检测孔22的检测部35通过设置在绝缘层4b的背侧并且接近于第一导电层4a的基板3的第二导电层3c形成。 As shown in FIG. 2 , the axis of the through hole 20 (hole 8 in FIG. 4 ) for positioning the power supply terminal of the electronic component is assumed to be O. As shown in FIG. The detecting portion 35 having the detecting hole 22 coaxial with the axis O and having a larger diameter than the through hole 20 is formed by the second conductive layer 3c of the substrate 3 disposed on the back side of the insulating layer 4b and close to the first conductive layer 4a. the

另外,垫,即导电层2ap1,2ap2以及5ap被提供在表面基板5和背部基板2上,以通孔20的轴线和以稍后描述的检测通孔的轴线为中心,如图1所示。 In addition, pads, that is, conductive layers 2ap1, 2ap2, and 5ap are provided on the surface substrate 5 and the back substrate 2, centering on the axis of the via hole 20 and the axis of the detection via hole described later, as shown in FIG. the

接下来,用于制造本发明的多层电路板的步骤将被说明。 Next, steps for manufacturing the multilayer circuit board of the present invention will be described. the

步骤1:用于插入和定位要在所述表面上设置的电子部件的电源端子(引脚)的通孔20被钻。与导电层3c连接的检测通孔23也被钻。注意,检测通孔23被设置在第二导电层3c内的任一位置。 Step 1: Through-holes 20 for inserting and positioning power terminals (pins) of electronic components to be provided on the surface are drilled. The detection vias 23 connected to the conductive layer 3c are also drilled. Note that the detection via hole 23 is provided at any position within the second conductive layer 3c. the

步骤2:分别通过镀过程,镀层21被形成在通孔20的内面上,以及镀层24被形成在检测通孔23的内面上。 Step 2: The plating layer 21 is formed on the inner surface of the through hole 20 and the plating layer 24 is formed on the inner surface of the detection through hole 23 through the plating process, respectively. the

步骤3:通过其直径比检测孔22的直径大的工具30、同时在工具30和镀层24即导电层3c之间施加例如5V的预设电压,从背侧沿着通孔20(轴线O)来执行钻。当工具30与导电层3c之间的电压变为例如2V的预设电压或以下时,判断工具30已经达到导电层3c的位置,即与导电层3c接触。随后,如果例如导电层3c接近于导电层4a,所述钻在该时刻停止。另外,例如与电路图案的设置有关,当检测部35被设置在背侧的导电层3a而不是导电层3c上时,所述钻从所述位置被进一步执行预设的距离。 Step 3: through the tool 30 whose diameter is larger than the diameter of the detection hole 22, and simultaneously apply a preset voltage of, for example, 5V between the tool 30 and the plating layer 24, that is, the conductive layer 3c, from the back side along the through hole 20 (axis O) to perform drilling. When the voltage between the tool 30 and the conductive layer 3c becomes a predetermined voltage such as 2V or below, it is judged that the tool 30 has reached the position of the conductive layer 3c, ie is in contact with the conductive layer 3c. Then, if eg the conductive layer 3c is close to the conductive layer 4a, the drill is stopped at that moment. In addition, for example, in connection with the arrangement of the circuit pattern, when the detection part 35 is arranged on the conductive layer 3a instead of the conductive layer 3c on the back side, the drilling is carried out further by a preset distance from the position. the

由于工具30的直径大于镀层21的外直径,由工具30从背表面沿着通孔20(轴线O)穿得具有大直径的孔32,如图3所示。孔32被钻到使工具30与通过导电层3c形成的检测孔23电导通的深度。因此, 通孔20的镀层21被稳定地去除直到导电层3c的下面或者略微在检测部35所处的导电层3c之上的位置。 Since the diameter of the tool 30 is larger than the outer diameter of the plating layer 21 , a hole 32 with a large diameter is pierced by the tool 30 from the back surface along the through hole 20 (axis O), as shown in FIG. 3 . The hole 32 is drilled to a depth such that the tool 30 is electrically connected to the detection hole 23 formed through the conductive layer 3c. Therefore, the plated layer 21 of the through hole 20 is stably removed up to a position below the conductive layer 3c or slightly above the conductive layer 3c where the detecting portion 35 is located. the

多层电路板1被以与以下常规方法相同的方式被制造。 The multilayer circuit board 1 is manufactured in the same manner as the following conventional method. the

步骤4:电源端子(引脚)被插入到其中形成有镀层21的通孔20中以定位电子部件。 Step 4: The power terminal (pin) is inserted into the through-hole 20 in which the plating layer 21 is formed to position the electronic part. the

步骤5:借助于焊接将电源端子与镀层21,即导电层4a连接。 Step 5: Connect the power supply terminal to the plating layer 21, ie, the conductive layer 4a, by means of soldering. the

注意,当没有电路图案形成在导电层2a和5a上时,在结束步骤2之后通过蚀刻等将电路图案形成在导电层2a和5a上。 Note that when no circuit patterns are formed on the conductive layers 2a and 5a, circuit patterns are formed on the conductive layers 2a and 5a by etching or the like after step 2 is ended. the

这里将说明检测部35被提供的导电层的位置。理想的是将检测部35设置在与电源端子所连接到的导电层最接近的导电层上,以从电源端子所连接到的导电层精确地去除背侧的镀层21。但是,存在电源端子的边缘和提供有检测部35的导电层中的任一者对另一者导致电磁效应的情况。在另一面,如果检测部35与电源端子所连接到的导电层分离以防止电磁效应,则变得难以精确地去除镀层21,因为基板的厚度依赖于层压条件而变化。因此,理想的是根据产品来决定其中设置有检测部35的导电层。 Here, the position of the conductive layer where the detection section 35 is provided will be described. It is desirable to dispose the detecting portion 35 on the conductive layer closest to the conductive layer to which the power supply terminal is connected to accurately remove the plating layer 21 on the back side from the conductive layer to which the power supply terminal is connected. However, there are cases where either one of the edge of the power supply terminal and the conductive layer provided with the detection portion 35 causes an electromagnetic effect on the other. On the other hand, if the detection part 35 is separated from the conductive layer to which the power terminal is connected to prevent electromagnetic effects, it becomes difficult to remove the plating layer 21 precisely because the thickness of the substrate varies depending on lamination conditions. Therefore, it is desirable to decide the conductive layer in which the detection part 35 is provided according to the product. the

注意,即使电子部件的电源端子(引脚)的长度比从表面到第一导电层4a的深度长,并且具有在将电子部件的电源端子(引脚)与例如导电层4a连接时达到导电层3c的长度,由工具30所穿的孔32具有比被镀通孔20的直径明显大的直径。因此,插入到镀层21中的电源端子将不与具有大直径的导电层3c接触,并且将不接近以施加电磁影响。另外,即使由于毛细现象,步骤5中的某个量的熔融焊料渗透到通孔20的镀层21与电源端子之间的窄间隙中,其不会到达具有大直径的孔32。另外,即使很小量的焊料达到大孔32的上端,该焊料将不会到达导电层3c,因为电源端子与大孔之间的间隙是大的并且毛细现象停止。 Note that even if the length of the power supply terminal (pin) of the electronic part is longer than the depth from the surface to the first conductive layer 4a, and there is a possibility of reaching the conductive layer when connecting the power supply terminal (pin) of the electronic part with, for example, the conductive layer 4a The length of 3c, the hole 32 pierced by the tool 30 has a diameter that is significantly larger than the diameter of the plated through hole 20 . Therefore, the power terminal inserted into the plated layer 21 will not be in contact with the conductive layer 3c having a large diameter, and will not come close to exert electromagnetic influence. In addition, even if a certain amount of molten solder in step 5 permeates into the narrow gap between the plating layer 21 of the through hole 20 and the power supply terminal due to capillary phenomenon, it does not reach the hole 32 having a large diameter. In addition, even if a very small amount of solder reaches the upper end of the large hole 32, the solder will not reach the conductive layer 3c because the gap between the power supply terminal and the large hole is large and capillarity stops. the

与导电层3c连接的检测通孔23被提供在本实施例中,使导电层 3c不需要例如通过钻来暴露,并且在测量工具30与导电层3c之间的电压时测量探头可以容易地加以设置。 The detection via 23 connected with the conductive layer 3c is provided in this embodiment, so that the conductive layer 3c does not need to be exposed, for example, by drilling, and the measuring probe can be easily added when measuring the voltage between the tool 30 and the conductive layer 3c. set up. the

注意,通过在用于安装多层电路板1的机加工台上提供用于自动定位要与检测通孔23(镀层24)接触的电压检测探头的装置,工作效率可进一步提高。 Note that work efficiency can be further improved by providing means for automatically positioning the voltage detection probe to be in contact with the detection through hole 23 (plating layer 24 ) on the machining table for mounting the multilayer circuit board 1 . the

另外,由于垫2ap1,2ap2以及5ap被提供在本实施例中,镀层21和24可以被稳定地形成。注意,垫2ap1,2ap2以及5ap可以不总被提供。另外,如果其上提供有检测部35的导电层3c例如通过暴露它而导电,则没有必要提供检测通孔23。 In addition, since the pads 2ap1, 2ap2, and 5ap are provided in this embodiment, the plating layers 21 and 24 can be stably formed. Note that pads 2ap1, 2ap2 and 5ap may not always be provided. In addition, if the conductive layer 3 c on which the detection portion 35 is provided is made conductive, for example, by exposing it, it is not necessary to provide the detection via hole 23 . the

尽管已经通过示例的实施例描述了本发明,应当理解的是本领域技术人员可以在本发明的精神和范围内进行许多改变和替换。根据所附权利要求的限定,显而易见的是具有这样的修改的实施例也属于本发明的范围。 Although the invention has been described by way of example embodiments, it should be understood that those skilled in the art can make many changes and substitutions within the spirit and scope of the invention. It is evident that embodiments with such modifications also fall within the scope of the invention as defined in the appended claims. the

Claims (3)

1.一种制造多层电路板的方法,所述多层电路板是通过层压和组合由导电层和绝缘层组成的多个基板形成的,所述多层电路板中形成有用于插入待安装在所述多层电路板的表面上的电子部件的电源端子以便与第一导电层连接的连接孔,包括步骤:1. A method of manufacturing a multilayer circuit board formed by laminating and combining a plurality of substrates composed of conductive layers and insulating layers, in which is formed a The connection hole for the power supply terminal of the electronic component installed on the surface of the multilayer circuit board so as to be connected with the first conductive layer includes the steps of: 在第二导电层上形成具有检测孔的检测部,相对于所述第一导电层,所述第二导电层在背面侧;A detection portion having a detection hole is formed on a second conductive layer, the second conductive layer is on the back side relative to the first conductive layer; 形成通孔,其从所述多层电路板的所述表面穿通到所述背面,同时与表面导电层接触,以及与位于内部的所述第一导电层接触,并且通过具有比所述检测孔的直径小的直径而不与所述检测孔接触,其中所述表面导电层设置在位于所述表面的基板的表面上;forming a through hole penetrating from the surface to the back surface of the multilayer circuit board while being in contact with the surface conductive layer, and in contact with the first conductive layer located inside, and by having a diameter smaller than that of the detection hole, wherein the surface conductive layer is provided on the surface of the substrate located on the surface; 对所述通孔的内表面施镀;以及plating the inner surface of the through hole; and 从所述多层电路板的背侧沿着所述通孔、借助于具有比所述检测孔的直径大的直径的工具、同时在所述工具和其上提供有所述检测部的所述第二导电层之间施加预定电压、基于所述检测孔的检测另外钻一具有大直径和预定深度的孔;Along the through hole from the back side of the multilayer circuit board, by means of a tool having a diameter larger than that of the detection hole, while providing the tool and the detection portion thereon. Applying a predetermined voltage between the second conductive layers, additionally drilling a hole with a large diameter and a predetermined depth based on the detection of the detection hole; 其中所述连接孔是通过所述表面导电层和所述第一导电层之间的所述通孔形成的,其中镀层被留在其所述内表面上;wherein said connection hole is formed through said via hole between said surface conductive layer and said first conductive layer, wherein plating is left on said inner surface thereof; 其中所述第一导电层是与具有所述表面导电层的表面基板相邻的第二基板的表面侧的导电层;并且wherein said first conductive layer is a conductive layer on a surface side of a second substrate adjacent to a surface substrate having said surface conductive layer; and 所述第二导电层是与所述第二基板背侧相邻的第三基板表面侧的导电层。The second conductive layer is a conductive layer on the surface side of the third substrate adjacent to the backside of the second substrate. 2.如权利要求1所述的多层电路板的制造方法,其中所述预定深度是基于所述电压变为预先设置的值或者预先设置的值以下时所述工具的位置而确定的深度。2. The method of manufacturing a multilayer circuit board according to claim 1, wherein the predetermined depth is a depth determined based on a position of the tool when the voltage becomes a preset value or less. 3.如权利要求1所述的多层电路板的制造方法,还包括步骤:3. The manufacture method of multilayer circuit board as claimed in claim 1, also comprises the step: 在所述通孔旁,在与具有所述检测部的所述第二导电层连接的位置钻一检测通孔;以及Next to the through hole, drilling a detection through hole at a position connected to the second conductive layer having the detection part; and 对所述检测通孔的内面施镀;其中Plating the inner surface of the detection through hole; wherein 借助于所述检测通孔的镀层,所述预定电压被施加在具有所述检测部的所述第二导电层与所述工具之间。The predetermined voltage is applied between the second conductive layer having the detection portion and the tool by means of the plating of the detection through hole.
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