CN1787385A - Data bus converting device and its RS coder decoder - Google Patents

Abstract

A data bus conversion device and its RS codec of the present invention, wherein the data bus conversion device includes two RS codecs simultaneously implemented in the system, and the two RS codecs are P-way interleaved RS (n1, k1) composite code and RS (n2, k2) code, the two RS codecs all use a P*m1 bit-wide data bus, and the input and output interfaces are the same; through the insertion and removal of bit 0, realize The mutual conversion between the P*m1 and T*m2 bit buses avoids the generation of incomplete symbols, thereby realizing the application of the traditional RS codec in the forward error correction device in the communication field.

Description

A data bus conversion device and its RS codec

technical field

The invention relates to a data bus conversion device in the communication field and a forward error correction device thereof, in particular to an RS (Reed-Solomon) code encoding and decoding device.

Background technique:

RS code is the abbreviation of Reed-Solomon code, which was first proposed by Reed and Solomon in 1960 respectively, and it is a linear block cyclic code on Galos field GF(2 ^m ). A code group (also called code word) contains n code elements, k information code elements (called information group), nk check code elements (called check group), generally RS[n, k] Indicates that nk errors can be detected and can be corrected An error is a kind of multi-ary code with strong error correction ability. It is widely used in computer error correction systems, especially storage systems, such as optical discs, magnetic disks, and magnetic tapes. In recent years, RS codes have also been widely used in optical transmission systems.

The current RS encoding and decoding device is only for one RS code, and the input and output bus width is the same as the number of bits of the symbol. However, in practical application systems, it is usually required to realize two or more RS codes at the same time. One of them is the standard RS code or its shortened code, and the other or more are multiple interleaved compound codes. For example, 16-way interleaved RS (255, 239) and RS (2720, 2550), 8-way interleaved RS (31, 26) and RS (155, 131), 8-way interleaved RS (15, 11) and RS (80, 59 )wait. The total number of bits of a variety of RS codewords implemented simultaneously in the same system is the same, but the number of bits of a symbol is different, and the number of bits of an information group may also be different. Generally, the minimum number of bits in the information group shall prevail, and those exceeding this value shall be filled with 0. For example, 16-way interleaved RS (255, 239) and RS (2720, 2550), the total number of bits of both is 32640, but the number of information group bits of the former is 16*239*8=30592, and the number of information group bits of the latter The number is 2550*12=30600. In order to achieve compatibility between the two, it is stipulated that the last 8 bits of each information group of RS (2720, 2550) are fixed to be 0.

In practical application systems, it is usually required to use the same input and output interfaces. Still taking 16-way interleaved RS (255, 239) and RS (2720, 2550) as an example, at present, 16-way interleaved RS (255, 239) has been widely used, and generally adopts 16*8=128bits data bus during realization, and each A group of 8-bits corresponds to an RS (255, 239) encoder or decoder in sequence. The RS (255, 239) encoder or decoder actually uses an 8-bits data bus, and each clock cycle just inputs and outputs one symbol. If RS (2720, 2550) uses the same interface as 16-way interleaved RS (255, 239), the data bus must also be 128 bits. However, each symbol of RS (2720, 2550) contains 12 bits, and 128 is not an integer multiple of 12. The 128-bit data input and output per clock cycle must contain incomplete symbols, but the existing RS coding and decoding technologies are all The unit is the code unit, and incomplete code units cannot be processed. 8-way interleaved RS (31, 26) and RS (155, 131), 8-way interleaved RS (15, 11) and RS (80, 59), etc. have the same functions as 16-way interleaved RS (255, 239) and RS (2720, 2550) same problem.

Therefore, there are defects in the prior art and need to be improved and developed.

Contents of the invention

The purpose of the present invention is to provide a data bus conversion device and its RS codec, aiming at the problem of incomplete code elements described above, through the insertion and removal of bit 0, to realize the connection between P*m1 and T*m2 bit buses mutual conversion, avoiding the generation of incomplete code elements, thereby effectively solving the problems of the prior art.

Technical scheme of the present invention is:

A data bus conversion device, wherein the data bus conversion device includes

Two RS codecs implemented simultaneously in the system, the two RS codecs are P-way interleaved RS (n1, k1) composite code and RS (n2, k2) code, the two RS codecs both use P*m1 bit wide data bus, and the input and output interfaces are the same;

An interleaving module and a deinterleaving module, the P-way interleaving RS (n1, k1) composite code decomposes the P*m1 bit-wide data bus into P-way independent data with m1 bit width through the interleaving module and the deinterleaving module The bus is respectively provided to P mutually independent RS(n1, k1) codecs;

A bus conversion module, the RS (n2, k2) codec realizes the conversion between the P*m1 bit data bus and the T*m2 bit data bus through the bus conversion module, and provides the T*m2 bit wide data bus to the RS The (n2, k2) semi-parallel codec performs T-way parallel codec;

Among them, RS(n1, k1) indicates that the number of information symbols is k1, the number of check symbols is (n1-k1), and each symbol contains an RS code of m1 bits; RS(n2, k2) indicates that the number of information symbols is k2, the number of check symbols is (n2-k2), and each symbol contains an RS code of m2 bits; T is the number of symbols processed in parallel by the RS (n2, k2) semi-parallel codec.

The data bus conversion device, wherein the bus conversion module includes a P*m1 to T*m2 bus conversion module and a T*m2 to P*m1 bus conversion module, and the P*m1 to T*m2 bus conversion module It is used to receive data through the P*m1 bit bus, store it in a shift register group, and then input it into the FIFO buffer through the T*m2 bit data bus, and then use the T*m2 bit data bus to output it;

A control module is used to control the shift register group to insert 0 of appropriate bits at the frame head and frame tail, manage FIFO, and simultaneously convert the received frame alignment information synchronized with the P*m1 bit bus into T* outputted Frame alignment information for m2 bit data bus synchronization.

The data bus conversion device, wherein, the T*m2 to P*m1 bus conversion module is used to receive data through the T*m2 bit bus, store it in the shift register group, and then input it to the P*m1 bit data bus Cache in FIFO, and then use P*m1 bit data bus to output;

The control module controls the shift register group to insert 0s of appropriate bits at the frame header and frame tail, manages the FIFO, and simultaneously converts the received frame alignment information synchronized with the T*m2 bit bus into an output P*m1 bit data bus Synchronized frame alignment information.

An RS codec using the data bus conversion device, wherein the RS codec includes

A P-way interleaved RS (n1, k1) composite code and an RS codec of RS (n2, k2) coding and decoding functions realized simultaneously, the P-way interleaved RS (n1, k1) encoder and RS (n2, k2) The encoder adopts the same input and output interface, the P-way interleaved RS (n1, k1) decoder and the RS (n2, k2) decoder adopt the same input and output interface, and the bus width is all P*m1 bits .

The RS codec, wherein the P-way interleaving RS (n1, k1) codec includes an interleaving module and a de-interleaving module, and between the interleaving module and the de-interleaving module is the P-way RS coding/decoding encoder; for the encoder, the input data enters the system and is sent to the P-way interleaved RS encoder for encoding, and the encoded data is output through a data bus with a P*m1 bit width; for the decoder, the input data enters the system and is sent to The P-way interleaved RS decoder performs decoding, and the decoded data is also output through a data bus with a width of P*m1 bits.

The RS codec, wherein, the RS (n2, k2) codec includes a P*m1 to T*m2 bus conversion module and a T*m2 to P*m1 bus conversion module, in the P*m1 m1 to T*m2 bus conversion module and the T*m2 to P*m1 bus conversion module is an RS (n2, k2) encoder/decoder; for the encoder, the data to be encoded is sent to the P*m1 To the T*m2 bus conversion module, insert bit 0 for filling, convert the P*m1 bit width data bus into a T*m2 bit data bus, and input the T*m2 bit width data into the RS(n2, k2) semi-parallel encoder Encode, the encoded data is first output to the T*m2 to P*m1 bus conversion module, remove the insertion bit 0 in the information group, and convert the T*m2 bit wide data bus into a P*m1 bit wide data bus output ; For the decoder, the data to be decoded is first sent to the P*m1 to T*m2 bus conversion module, inserting bit 0 for filling, and converting the P*m1 bit-wide data bus into a T*m2 bit-wide data bus , T*m2 bit width data is input to the RS(n2, k2) semi-parallel decoder for decoding, the decoded data is first output to the T*m2 to P*m1 bus conversion module, and the inserted bit 0 in the information group is removed , converting the T*m2-bit-wide data bus into a P*m1-bit-wide data bus for output.

The RS codec, wherein, the P*m1 bit-wide bus and the T*m2 bit-wide bus adopt clocks of the same frequency, and an enable signal is used to indicate whether the data on the bus is valid, if the enable signal does not enable Yes, the P*m1 or T*m2 bit data on the bus is invalid, otherwise it is valid.

A data bus conversion device and its RS codec provided by the present invention, because the input and output bus width of the RS (n1, k1) codec is the same as the symbol width, the RS (n2, k2) semi-parallel codec The input and output bus width of the encoder is T times the width of the symbol, and no incomplete symbols are involved. It can be realized by the traditional RS coding method, which effectively solves the problem that the incomplete symbols cannot be applied to the RS codec. The input and output interfaces between different RS codecs are unified.

Description of drawings

Fig. 1 is unified interface of the present invention and realizes the system structural diagram of the codec of P way interleaving RS (n1, k1) composite code and RS (n2, k2) code simultaneously;

Fig. 2 is P road interleaved RS (n1, k1) coder module structural diagram of the present invention;

Fig. 3 is P way interleaved RS (n1, k1) decoder module structural diagram of the present invention;

Fig. 4 is the RS (n2, k2) encoder module structural diagram of the present invention;

Fig. 5 is the RS (n2, k2) decoder module structural diagram of the present invention;

Fig. 6 is P*m1 to T*m2 bus conversion module structural diagram of the present invention;

Fig. 7 is a structural diagram of the T*m2 to P*m1 bus conversion module of the present invention.

Detailed ways:

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Its core idea of the method of the present invention is: two kinds of RS codecs realized simultaneously in the system--P way interleaved RS (n1, k1) composite code and RS (n2, k2) code all use P*m1 bit wide The data bus, the input and output interfaces are the same. The P-way interleaving RS(n1, k1) composite code decomposes the P*m1 bit-wide data bus into P-way independent data buses with m1-bit width through the interleaving and deinterleaving modules, and provides them to P mutually independent RS(n1 , k1) Codec. The RS(n2, k2) codec realizes the conversion between P*m1 bit data bus and T*m2 bit data bus through the bus conversion module, and provides T*m2 bit wide data bus for RS(n2, k2) semi-parallel compilation The encoder performs T-path parallel encoding and decoding.

Among them, RS(n1, k1) indicates that the number of information symbols is k1, the number of check symbols is (n1-k1), and each symbol contains an RS code of m1 bits; RS(n2, k2) indicates that the number of information symbols is k2, the number of check symbols is (n2-k2), and each symbol contains an RS code of m2 bits; T is the number of symbols processed in parallel by the RS (n2, k2) semi-parallel codec. Generally, m1 is smaller than m2, m1*k1 is smaller than or equal to m2*k2, and P*m1 is smaller than or equal to T*m2.

As shown in Figure 1, the bus conversion module is divided into two parts: the P*m1 to T*m2 bus conversion module and the T*m2 to P*m1 bus conversion module. The P*m1 to T*m2 bus conversion module passes the P*m1 bit The data is received by the bus, stored in the shift register group, and then input to the FIFO for buffering through the T*m2 bit data bus, and then output by the T*m2 bit data bus. The control module controls the shift register group to insert 0s of appropriate bits at the frame header and frame tail, manages the FIFO, and simultaneously converts the received frame alignment information synchronized with the P*m1 bit bus into a frame location synchronized with the output T*m2 bit data bus Frame alignment information. The T*m2 to P*m1 bus conversion module is similar to the P*m1 to T*m2 bus conversion module. First, it receives data through the T*m2 bit bus, stores it in the shift register group, and then inputs it to the P*m1 bit data bus. It is buffered in FIFO, and then output with P*m1 bit data bus. The control module controls the shift register group to insert 0s of appropriate bits at the frame header and frame tail, manages the FIFO, and at the same time converts the received frame alignment information synchronized with the T*m2 bit bus into one synchronized with the output P*m1 bit data bus Frame alignment information.

The input and output bus width of the RS(n1, k1) codec is the same as the symbol width, and the input and output bus width of the RS(n2, k2) semi-parallel codec is T times the symbol width, which does not involve incomplete codes Elements can be realized by the traditional RS encoding and decoding method, which effectively solves the problem of incomplete code elements and unifies the input and output interfaces between different RS codes.

The system structure of the RS codec that realizes P-way interleaved RS (n1, k1) composite code and RS (n2, k2) code coding and decoding functions is shown in Figure 1. The P-way interleaved RS (n1, k1) encoder and The RS (n2, k2) encoder uses the same input and output interface, and the P-way interleaved RS (n1, k1) decoder and RS (n2, k2) decoder also use the same input and output interface, and the bus width is P *m1 bits. For the encoder, the input data enters the system and is sent to the P-way interleaved RS (n1, k1) encoder or RS (n2, k2) encoder for encoding, and the encoded data is output through a data bus with a P*m1 bit width. For the decoder, after the input data enters the system, it is sent to the P-way interleaved RS (n1, k1) decoder or RS (n2, k2) decoder for decoding, and the decoded data also passes through the P*m1 bit width data bus output.

The structure of the P-way interleaved RS (n1, k1) encoder is shown in Fig. 2 . The data to be encoded is first sent to the deinterleaving module 210 through the P*m1 bit width input bus, and after deinterleaving, it is sent to P mutually independent RS (n1, k1) encoders for encoding through P pieces of m1 bit width data buses respectively. The coded data is sent to the interleaving module 220 for interleaving, and then output through a P*m1 bit width data bus. The structure of the P-way interleaved RS (n1, k1) decoder is similar to that of the encoder. As shown in Figure 3, the data to be decoded is first sent to the de-interleaving module 210 through the P*m1 bit width input bus, and then passed through after de-interleaving P pieces of m1-bit-width data buses are respectively sent to P independent RS (n1, k1) decoders for decoding, and the decoded data is sent to the interleaving module 220 for interleaving, and then passed through the P*m1-bit-width data bus Output the decoded data.

The structure of the RS (n2, k2) encoder is as shown in Figure 4. The data to be encoded is first sent to the P*m1 to T*m2 bus conversion module 410, and the bit 0 is inserted for filling, and the data bus of the P*m1 bit width is converted into T*m2 bit data bus. T*m2 bit width data is input into RS(n2, k2) semi-parallel encoder for encoding, each clock processes T symbols in parallel, each symbol contains m2 bits, no incomplete symbols appear, and the conventional RS encoder is still used accomplish. The encoded data is first output to the T*m2 to P*m1 bus conversion module 420, the insertion bit 0 in the information group is removed, and the T*m2 bit wide data bus is converted into a P*m1 bit wide data bus for output. The structure of the RS (n2, k2) decoder is similar to the structure of the RS (n2, k2) encoder, as shown in Figure 4, the data to be decoded is first sent to the P*m1 to T*m2 bus conversion module 410, insert Bit 0 is filled to convert the P*m1 bit wide data bus into a T*m2 bit wide data bus. The T*m2 bit width data is input to the RS (n2, k2) semi-parallel decoder for decoding, and each clock processes T symbols in parallel, and each symbol contains m2 bits. The decoded data is first output to the T*m2 to P*m1 bus conversion module 420, removes the inserted bits in the information group, and converts the T*m2 bit wide data bus into a P*m1 bit wide data bus for output. For the convenience of hardware implementation, the P*m1 bit-wide bus and the T*m2 bit-wide bus use clocks of the same frequency, and an enable signal is used to indicate whether the data on the bus is valid. If the enable signal is not enabled, the P*m1 or T*m2 bit data on the bus is invalid, otherwise it is valid.

比特，实际输入的信息组长度为 个m2比特码元。因为在信息组前面插入码元比特0不会改变校验组的值，一般需要在信息组前插入 -k2个码元比特0，同时需要在信息组末尾插入k2*m2-P*k1*m1个比特0。以16路交织RS(255，239)和RS(2720，2550)为例，因为RS(2720，2550)编码器的接口要与16路交织RS(255，239)的相同，后者采用128-bits输入输出总线，输入239个128-bits信息组以后等待16个以上的时钟周期，输出校验码元，RS(2720，2550)编码模块必须在239个时钟周期内完成校验组的计算，每个时钟周期接收 个12-bits码元，编码模块每个时钟周期并行处理11个码元，一个码字需要 个时钟周期，实际处理232*11＝2552个码元。不过一个码元实际的信息比特数为16*239*8＝30592，加上固定填充的8比特，还需要填充2552*12-30592-8＝24比特(即2个码元0)进行计算。将24个比特0插到码字前面，RS(2720，2550)码字就变成了RS(2722，2552)码字。为了与16路交织RS(255，239)一致，在编码器的输出端必须将插入到码字前面的24个填充比特去除，将RS(2722，2552)码字转换成RS(2720，2550)码字。RS(2720，2550)译码器的接口也要与16路交织RS(255，239)的相同，255个时钟周期接收完一个RS(2720，2550)码字，每个时钟周期需要并行处理 个码元，实际处理时间为

个时钟周期，实际处理了248*11＝2728个码元。所以，在并行译码前，需要在接收到的RS(2720，2550)码字前面插入6*12＝72比特的0(即6个码元0)，将其转换成RS(2728，2558)码字。Generally, the bus width of the RS(n2, k2) encoder is

bits, the length of the actual input information group is m2 bit symbols. Because inserting code element bit 0 in front of the information group will not change the value of the check group, it is generally necessary to insert - k2 code element bits 0, and k2*m2-P*k1*m1 bit 0s need to be inserted at the end of the information group at the same time. Take the 16-way interleaved RS (255, 239) and RS (2720, 2550) as an example, because the interface of the RS (2720, 2550) encoder is the same as that of the 16-way interleaved RS (255, 239), which uses 128- bits input and output bus, after inputting 239 128-bits information groups, wait for more than 16 clock cycles, and output the check code element, the RS (2720, 2550) encoding module must complete the calculation of the check group within 239 clock cycles, Each clock cycle receives Each 12-bits symbol, the encoding module processes 11 symbols in parallel in each clock cycle, and a codeword needs clock cycle, actually process 232*11=2552 symbols. However, the actual number of information bits in a symbol is 16*239*8=30592, plus 8 bits for fixed padding, 2552*12-30592-8=24 bits (that is, 2 symbol 0s) need to be filled for calculation. By inserting 24 bits of 0 in front of the codeword, the RS(2720, 2550) codeword becomes the RS(2722, 2552) codeword. In order to be consistent with the 16-way interleaved RS (255, 239), the 24 stuffing bits inserted in front of the codeword must be removed at the output of the encoder, and the RS (2722, 2552) codeword is converted into RS (2720, 2550) Codeword. The interface of the RS (2720, 2550) decoder is also the same as that of the 16-way interleaved RS (255, 239). After receiving an RS (2720, 2550) codeword in 255 clock cycles, each clock cycle needs to be processed in parallel. code units, the actual processing time is

clock cycle, 248*11=2728 symbols are actually processed. Therefore, before parallel decoding, it is necessary to insert 6*12=72 bits of 0 (that is, 6 symbol 0s) in front of the received RS (2720, 2550) codeword to convert it into RS (2728, 2558) Codeword.

Figure 6 is a structural diagram of the bus conversion module from P*m1 bits to T*m2 bits, and the FIFO is T*m2 bits wide and deep of memory. Registers of the 2*P*m1-bit shift register group are numbered 0, 1, . . . , 2*P*m1 from top to bottom. The pointer pointer points to the next position of the currently valid filling data in the bit shift register, and the registers with numbers smaller than pointer have valid data, and the registers with numbers greater than or equal to pointer are empty. For example, pointer=w, then there are valid data in register 0 to register w. If valid data is input at this time, the input P*m1 bit sequence is placed under the original remaining data, that is, it is placed in register w to register w+P*m1-1, and the pointer moves down to point to register w+P*m1. If the valid data in the shift register exceeds T*m2 bits (the pointer pointer is greater than or equal to T*m2), move out the top T*m2 bit data, and move the remaining data up T*m2 bits, and move up the pointer by T *m2 bits. If there is data input while data is being moved out, first move out the data, adjust the position of the remaining data, then place the newly input data under the remaining data in sequence, and adjust the pointer according to the new data position. Because as long as there is more than T*m2 bits of data in the shift register, the top data will be shifted out, and the data in the shift register will never exceed 2*P*m1 bits.

插入

个比特0到信息组前面；在输入P*k1*m1信息比特后，还需要添加k2*m2-k1*m1个比特0到移位寄存器。对于译码器的P*m1到T*m2转换模块，需要将移位寄存器设为0的同时设置指针为插入 个比特0到信息组前面。控制模块通过对指针的控制完成比特0的插入，它同时还控制FIFO，对帧定位信息进行转换，将输入的与P*m1比特宽数据总线同步的帧定位信号转转成与T*m2比特宽数据总线同步的帧定位信号。A clock cycle input conversion module has at most P*m1 bits, and the output conversion module may be T*m2 bits. Even if P*m1 bit data bus is continuously input, T*m2 bit data output will have gaps (some clock cycles The data is not enabled, indicating that there is no output). If there is a gap in the middle of the codeword, it will greatly increase the complexity of encoding and decoding. Therefore, FIFO is used to cache the data. After a codeword starts, enough data is buffered first, and then output continuously, thereby removing the gap in the middle of the codeword. If the P*m1 bit data bus is continuously input (in general, the input is continuous), a codeword needs n1 clock cycles, and is continuously output by the T*m2 bit data bus, which requires clock cycle, to ensure continuity, you need to cache bit data. When each codeword is initialized, the shift register is set to 0, and the pointer is set to

insert

bits 0 to the front of the information group; after inputting P*k1*m1 information bits, k2*m2-k1*m1 bits 0 need to be added to the shift register. For the P*m1 to T*m2 conversion module of the decoder, it is necessary to set the shift register to 0 and set the pointer to insert bits 0 to the front of the information group. The control module completes the insertion of bit 0 through the control of the pointer. It also controls the FIFO to convert the frame alignment information, and converts the input frame alignment signal synchronized with the P*m1 bit wide data bus into a T*m2 bit Frame alignment signal for wide data bus synchronization.

The T*m2 to P*m1 bus conversion module is similar to the P*m1 to T*m2 conversion module, using the structure shown in Figure 7. The shift register group comprising 2*P*m1 bits sequentially numbers each register as 0, 1, . . . , 2*P*m1-1 from top to bottom. The FIFO consists of a width of T*m2 bits and a depth of memory composition. The pointer pointer points to the next position of the currently valid filling data in the bit shift register, and the registers with numbers smaller than pointer have valid data, and the registers with numbers greater than or equal to pointer are empty. The module first receives data from the encoding module or the decoding module through the T*m2 bit data bus, and stores it in the FIFO. If more than T*m2 registers in the shift register are empty (pointer is less than 2*P*m1-T*m2), read T*m2 bits of data from the FIFO, and place the existing data in the shift register in order Next, adjust the pointer at the same time to point to the corresponding position after storing the data. If there is valid data exceeding P*m1 bits in the shift register, it will be output through the P*m1 bit data bus, and at the same time, the remaining data will be moved to the top of the shift register to adjust the pointer. Usually, reading data from FIFO and outputting data from shift register occur at the same time. At this time, first output P*m1 bit data, adjust the remaining data position, and then store the data read in from FIFO sequentially under the remaining data, and adjust the pointer.

比特填充值。For the P*m1 to T*m2 conversion module of the encoder, the first part of each codeword needs to be discarded Bit stuffing value; for the P*m1 to T*m2 conversion module of the decoder, it is necessary to discard the first bit of each codeword

bit padding value.

The RS(n1, k1) and RS(n2, k2) codecs in the system process one or T symbols per clock cycle, do not involve incomplete symbols, and are conventional RS codecs.

The present invention realizes the mutual conversion between P*m1 and T*m2 bit buses through the insertion and removal of bit 0, avoids the generation of incomplete code elements, and skillfully solves the incomplete code elements caused by the inconsistency of the data bus The problem is to implement a P-way interleaved RS(n1, k1) composite code and RS(n2, k2) codec with the same interface.

Claims (7)

1, a kind of data/address bus conversion equipment is characterized in that, described data/address bus conversion equipment comprises

Two kinds of RS coders in system, realizing simultaneously, these two kinds of RS coders for the P road interweave RS (n1, k1) (these two kinds of RS coders all use the data/address bus of P*m1 bit width, and input/output interface is identical for n2, k2) sign indicating number for compound key and RS;

One interleaving block and a de-interleaving block, the described P road RS (n1 that interweaves, k1) compound key resolves into the data/address bus that the P road independently has the m1 bit width to the data/address bus of P*m1 bit width by this interleaving block and de-interleaving block, offer P separate RS (n1, k1) coder respectively;

One bus conversion module, described RS (n2, k2) coder is realized conversion between P*m1 bit data bus and the T*m2 bit data bus by this bus conversion module, provide T*m2 bit width data/address bus to RS (n2, k2) half parallel encoding and decoding device carries out T road parallel encoding and decoding;

Wherein (n1 k1) represents that the information code element number is k1 to RS, and the verification code element number is (n1-k1), and each code element comprises the RS sign indicating number of m1 bit; RS (n2, k2) expression information code element number is k2, and the verification code element number is (n2-k2), and each code element comprises the RS sign indicating number of m2 bit; T is RS (n2, k2) code element number of half parallel encoding and decoding device parallel processing.

2, data/address bus conversion equipment according to claim 1, it is characterized in that, described bus conversion module comprise P*m1 to T*m2 bus conversion module and T*m2 to the P*m1 bus conversion module, described P*m1 is used for receiving data by the P*m1 bit bus to the T*m2 bus conversion module, deposit a shift register group in, be input to buffer memory among the FIFO by the T*m2 bit data bus again, then with the output of T*m2 bit data bus;

One control module, be used to control described shift register group and insert 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of T*m2 bit data bus that converts to and export with the synchronous frame alligning information of P*m1 bit bus that will receive simultaneously.

3, data/address bus conversion equipment according to claim 1, it is characterized in that, described T*m2 is used for receiving data by the T*m2 bit bus to the P*m1 bus conversion module, deposit shift register group in, be input to buffer memory among the FIFO by the P*m1 bit data bus again, then with the output of P*m1 bit data bus;

Described control module control shift register group is inserted 0 of suitable bit at frame head and postamble, management FIFO, the synchronous frame alligning information of P*m1 bit data bus that converts to and export with the synchronous frame alligning information of T*m2 bit bus that will receive simultaneously.

4, a kind of RS coder that uses data/address bus conversion equipment as claimed in claim 1 is characterized in that, described RS coder comprises

A P road of the Shi Xianing RS (n1 that interweaves simultaneously, k1) compound key and RS (n2, k2) the RS coder of code coding/decoding function, described P road interweave RS (n1, k1) encoder and RS (n2, k2) encoder adopts identical input/output interface, the described P road RS (n1 that interweaves, k1) (highway width all is the P*m1 bit for n2, k2) the identical input/output interface of decoder employing for decoder and RS.

5, RS coder according to claim 4 is characterized in that, described P road interweave RS (n1, k1) coder comprises an interleaving block and a de-interleaving block, is P road RS volume/decoder between this interleaving block and the de-interleaving block; For encoder, the input data enter to be delivered to the P road RS encoder that interweaves after the system and encodes, and the data behind the coding are by the data/address bus output of P*m1 bit width; For decoder, the input data enter to be delivered to the P road RS decoder that interweaves after the system and deciphers, and the data after the decoding are the data/address bus output by the P*m1 bit width equally.

6, according to claim 4 or 5 described RS coders, it is characterized in that, described RS (n2, k2) coder comprise a P*m1 to T*m2 bus conversion module and a T*m2 to the P*m1 bus conversion module, at this P*m1 to T*m2 bus conversion module and this T*m2 between the P*m1 bus conversion module being RS (n2, k2) volume/decoder; For encoder, data to be encoded are delivered to described P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit, T*m2 bit width data input RS (n2, k2) half parallel encoder is encoded, and the data behind the coding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width; For decoder, data to decode is at first delivered to P*m1 to the T*m2 bus conversion module, inserting bit 0 fills, the data/address bus of P*m1 bit width is converted to the data/address bus of T*m2 bit width, T*m2 bit width data input RS (n2, k2) half parallel decoder is deciphered, and the data after the decoding at first output to T*m2 to the P*m1 bus conversion module, remove the insertion bit 0 in the information sets, the data/address bus of T*m2 bit width is converted to the data/address bus output of P*m1 bit width.

7, RS coder according to claim 6, it is characterized in that, described P*m1 bit width bus and T*m2 bit width bus adopt the clock of same frequency, whether the data that indicate on the bus with enable signal are effective simultaneously, if enable signal does not enable, P*m1 on the bus or T*m2 Bit data are invalid, otherwise effectively.

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