CN1783857B - Device for clearing DC bias voltage and regulating gain - Google Patents
Device for clearing DC bias voltage and regulating gain Download PDFInfo
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- CN1783857B CN1783857B CN 200410095599 CN200410095599A CN1783857B CN 1783857 B CN1783857 B CN 1783857B CN 200410095599 CN200410095599 CN 200410095599 CN 200410095599 A CN200410095599 A CN 200410095599A CN 1783857 B CN1783857 B CN 1783857B
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Abstract
A device for eliminating dc bias includes first amplifier module, first low pass filter circuit and second amplifier module. The output terminal signal of first amplifier is A times of the signal of input terminal. The input terminal of first low pass filter is coupled to the output terminal of first amplifier module for outputting dc bias in received signal and amplifying dc bias by B times. Said second amplifier module includes first input terminal, second input terminal and output terminal, wherein the first input terminal is coupled to the output terminal of first low pass filter, second input terminal is coupled to positive input signal, the output signal is the summation of C1 times of first input terminal signal and C2 times of second input terminal signal according with the formula A*B*C1=-C2.
Description
Technical field
The invention relates to a kind of device of eliminating Dc bias, and particularly relevant for device for clearing DC bias voltage and regulating gain in zero intermediate frequency or Low Medium Frequency receiver.
Background technology
On the transmitter and receiver framework of the communication IC of zero intermediate frequency or Low Medium Frequency, often there is direct current offset (DC offset) to take place, especially serious with the transmitter and receiver framework of zero intermediate frequency.
When the direct current offset phenomenon takes place, can make that the adjustable gain amplifier (VGA) of level presents saturation mode behind the transmitter and receiver, thereby can't effectively bring into play the effect of its gain amplifier, and the influence that it caused can make the bit error rate (BER) of transmitter and receiver rise, even can cause fully and can't receive signal.
The influence that direct current offset caused in the transmitter and receiver framework for the communication IC that improves at zero intermediate frequency or Low Medium Frequency, in No. the 4873702nd, United States Patent (USP), propose to utilize simulation digital quantizer (ADC) with digital signal processor (DSP) technology direct-flow shifted signal is isolated, then utilize digital analog converter (DAC) isolated direct-flow shifted signal is converted into analog signal, subtract each other the cancellation of DC offset signal doing with the signal that contained direct current offset originally.
Though this patent has been eliminated the influence of direct current offset to transmitter and receiver, the simulation of its complexity digital quantizer, digital signal processor and digital the circuit design of analog converter, make us hanging back.
And a kind of circuit of cancellation of DC offset is also proposed in No. the 5748681st, the United States Patent (USP), it is to utilize a big electric capacity to finish high pass filter, therefore can cancellation of DC offset.But these filter capacitor two ends are owing to be connected to earth terminal without any one, so be to use very large metal-insulator electric capacity (Metal Insulator Metal; MIM) or polysilicon insulation electric capacity (Polysilicon Insulator Polysilicon; PIP) finish, thereby can occupy a large amount of IC areas, cause the puzzlement in the design.
And all propose to utilize a big electric capacity to finish low pass filter in No. 5798664 No. the 5793230th, United States Patent (USP), therefore can cancellation of DC offset.But these filter capacitor two ends are owing to be connected to earth terminal without any one, so be must use very large metal-insulator electric capacity or the polycrystalline series electric capacity that insulate to finish, so also be to occupy a large amount of IC areas, cause the puzzlement in the design.
In sum, though use simulation digital quantizer, digital signal processor and Shuo Zi analog converter, or use the problem that metal-insulator electric capacity and polycrystalline series insulation electric capacity can cancellation of DC offset.But the complex circuit design participant occupies the electric capacity of a large amount of IC areas, and still quite inconvenience causes everybody many puzzlements in the use.
Summary of the invention
Purpose of the present invention is to provide a kind of device for clearing DC bias voltage and regulating gain exactly, to eliminate Dc bias and to adjust gain.
Purpose of the present invention is to provide a kind of device for clearing DC bias voltage and regulating gain exactly, to eliminate the Dc bias signal and can not occupy a large amount of IC areas, does not more have complex circuit design.
The present invention proposes a kind of device for clearing DC bias voltage and regulating gain, comprises voltage tracking circuit, first amplifier module, first filter circuit and second amplifier module.
First amplifier module comprises first resistance, second resistance and first operational amplifier.Wherein, first end of first resistance is electrically coupled to positive input signal, positive input signal comprises a positive direct-current bias voltage signal and an AC signal, second end of first resistance is electrically coupled to the inverting input of first operational amplifier, first end of second resistance also is electrically coupled to the inverting input of first operational amplifier, and second end of second resistance is electrically coupled to the output of first operational amplifier.
First filter circuit comprises the 3rd resistance and first electric capacity.Wherein, first end of the 3rd resistance is electrically coupled to the output of first operational amplifier, and second end of the 3rd resistance is electrically coupled to first end of first electric capacity, and second end of first electric capacity is electrically coupled to earth terminal.
Second amplifier module comprises the 4th resistance, the 5th resistance, the 6th resistance and second operational amplifier.Wherein, first end of the 4th resistance is electrically coupled to positive input signal, second end of the 4th resistance is electrically coupled to the inverting input of second operational amplifier, first end of the 5th resistance is electrically coupled to the output of first filter circuit, second end of the 5th resistance and first end of the 6th resistance are electrically coupled to the inverting input of second operational amplifier, and second end of the 6th resistance is electrically coupled to the output of second operational amplifier.
Voltage is followed the trail of circuit and is had two inputs, be electrically coupled to positive input signal and negative input signal respectively, with the normal phase input end of the accurate position of output reference voltage to first operational amplifier and second operational amplifier, negative input signal comprises a negative Dc bias signal and an AC signal.
Wherein, the 4th resistance is that R4, first resistance are that R1, second resistance are that R2 and the 5th resistance are R5, and meets following formula:
The present invention also proposes a kind of device for clearing DC bias voltage and regulating gain, comprises first amplifier module, first low pass filter and second amplifier module.
Wherein, first amplifier module comprises first input end and output.The first input end of first amplifier module is electrically coupled to positive input signal, positive input signal comprises a positive direct-current bias voltage signal and an AC signal, and the output end signal of this first amplifier module is A times for the signal of the first input end of first amplifier module.
First low pass filter comprises input and output.Wherein, the input of first low pass filter is electrically coupled to the output of first amplifier module, exporting the Dc bias in its received signal, and this Dc bias is amplified B doubly.
Second amplifier module comprises first input end, second input and output.Wherein, the first input end of second amplifier module is electrically coupled to the output of first filter, second input of this second amplifier module is electrically coupled to positive input signal, wherein the signal of the second amplifier module output be for the C1 of the first input end signal of second amplifier module doubly with the C2 summation doubly of the signal of second input of second amplifier module, and meet following formula:
A*B*C1＝-C2。
The present invention is low than the frequency of normal signal because of the frequency of utilizing the Dc bias signal, therefore uses low pass filter that the Dc bias signal is separated with normal signal, eliminates Dc bias and the purpose of adjusting gain to reach.And all in the present invention electric capacity all can use the less metal-oxide half field effect transistor of volume (Metal OxideSemiconductor Field Effect Transistor) electric capacity to finish, and therefore can reduce area required on chip.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred implementation of the present invention is elaborated below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 illustrates the circuit diagram into the device for clearing DC bias voltage and regulating gain of one embodiment of the present invention.
Fig. 2 illustrates the circuit diagram into the device for clearing DC bias voltage and regulating gain of another preferred embodiment of the present invention.
Fig. 3 illustrates the waveform input signal figure into the clearing DC bias voltage and regulating gain device of one embodiment of the present invention.
Fig. 4 illustrates the signal output waveform figure into the clearing DC bias voltage and regulating gain device of one embodiment of the present invention.
Main description of reference numerals:
100: device for clearing DC bias voltage and regulating gain
200: device for clearing DC bias voltage and regulating gain
300: the waveform input signal figure of device for clearing DC bias voltage and regulating gain
400: the signal output waveform figure of device for clearing DC bias voltage and regulating gain
110,202: the first amplifier modules
112: the first resistance
114: the second resistance
116: the first operational amplifiers
120: the first filter circuits
122: the three resistance
124: the first electric capacity
130,206: the second amplifier modules
132: the four resistance
134: the five resistance
136: the six resistance
138: the second operational amplifiers
140,208: the three amplifier modules
142: the nine resistance
144: the three operational amplifiers
146: the ten resistance
150: the second filter circuits
152: the three electric capacity
154: the 11 resistance
160,212: the four amplifier modules
162: the 12 resistance
164: the 13 resistance
166: the 14 resistance
168: the four-operational amplifiers
170,214: voltage is followed the trail of circuit
172: the seven resistance
174: the eight resistance
176: the second electric capacity
204: the first low pass filters
210: the second low pass filters
Embodiment
Please refer to Fig. 1, Fig. 1 is the circuit diagram that illustrates the device for clearing DC bias voltage and regulating gain of one embodiment of the present invention, is applicable to the zero intermediate frequency receiver in the communication receiving system.Wherein, circuit Figure 100 of device for clearing DC bias voltage and regulating gain comprises first amplifier module 110, first filter circuit 120, second amplifier module 130, the 3rd amplifier module 140, second filter circuit 150, the 4th amplifier module 160 and voltage tracking circuit 170.
First amplifier module 110 comprises first resistance 112, second resistance 114 and first operational amplifier 116, first filter circuit 120 comprises that the 3rd resistance 122 and first electric capacity, 124, the second amplifier modules 130 comprise the 4th resistance 132, the 5th resistance 134, the 6th resistance 136 and second operational amplifier 138.
The 3rd amplifier module 140 comprises the 9th resistance 142, the 3rd operational amplifier 144 and the tenth resistance 146, second filter circuit 150 comprises the 11 resistance 154 and the 3rd electric capacity 152, the 4th amplifier module 160 comprises the 12 resistance the 162, the 13 resistance the 164, the 14 resistance 166 and the 4th computing amplification 168, and voltage is followed the trail of circuit 170 and comprised the 7th resistance 172, the 8th resistance 174 and second electric capacity 176.
In first amplifier module 110, first end of first resistance 112 is to be electrically coupled to positive input signal, second end of first resistance 112 is the inverting inputs that are electrically coupled to first operational amplifier 116, first end of second resistance 114 is the inverting inputs that are electrically coupled to first operational amplifier 116, and second end of second resistance 114 is the outputs that are electrically coupled to first operational amplifier 116.
In first filter circuit 120, first end of the 3rd resistance 122 is the outputs that are electrically coupled to first operational amplifier 116, first end of first electric capacity 124 is second ends that are electrically coupled to the 3rd resistance 122, and second end of first electric capacity 124 is to be electrically coupled to earth terminal.
In second amplifier module 130, first end of the 4th resistance 132 is to be electrically coupled to positive input signal, second end of the 4th resistance 132 is the inverting inputs that are electrically coupled to second operational amplifier 138, first end of the 5th resistance 134 is the outputs that are electrically coupled to first filter circuit 120, second end of the 5th resistance 134 is the inverting inputs that are electrically coupled to second operational amplifier 138, first end of the 6th resistance 136 is the inverting inputs that are electrically coupled to second operational amplifier 138, and second end of the 6th resistance 136 is the outputs that are electrically coupled to second operational amplifier 138.
In the 3rd amplifier module 140, first end of the 9th resistance 142 is to be electrically coupled to negative input signal, and second end of the 9th resistance 142 is the inverting inputs that are electrically coupled to the 3rd operational amplifier 144.First end of the tenth resistance 146 is the inverting inputs that are electrically coupled to the 3rd operational amplifier 144, and second end of the tenth resistance 146 is the outputs that are electrically coupled to the 3rd operational amplifier 146.
In second filter circuit 150, first end of the 11 resistance 154 is the outputs that are electrically coupled to the 3rd operational amplifier 144, the 3rd electric capacity 152 first ends are second ends that are electrically coupled to the 11 resistance 154, and second end of the 3rd electric capacity 152 is to be electrically coupled to earth terminal.
In the 4th amplifier module 160, first end of the 12 resistance 162 is to be electrically coupled to positive input signal, second end of the 12 resistance 162 is the inverting inputs that are electrically coupled to four-operational amplifier 168. first end of the 13 resistance 164 is the outputs that are electrically coupled to second filter circuit 150, second end of the 13 resistance 164 is the inverting inputs that are electrically coupled to four-operational amplifier 168, first end of the 14 resistance 166 is the inverting inputs that are electrically coupled to four-operational amplifier 168, and second end of the 14 resistance 166 is the outputs that are electrically coupled to four-operational amplifier 168.
Follow the trail of in the circuit 170 at voltage, first end of the 7th resistance 172, the 8th resistance 174 and second electric capacity 176 is the normal phase input ends that are electrically coupled to first operational amplifier 116, second operational amplifier 138, the 3rd operational amplifier 144 and four-operational amplifier 168, second end of the 7th resistance 172 is to be electrically coupled to positive input signal, second end of the 8th resistance 174 is to be electrically coupled to negative input signal, and second end of second electric capacity 176 is to be electrically coupled to earth terminal.
In the present embodiment, two inputs that voltage is followed the trail of circuit 170 receive positive input signal and negative input signal respectively, the 7th resistance 172 and the resistance value of the 8th resistance 174 can be designed to the same greatly in the use, the normal phase input end of reference voltage to the first operational amplifier 116, second operational amplifier 138, the 3rd operational amplifier 144 and the four-operational amplifier 168 of a zero potential just can be provided thus.In the present embodiment, voltage is followed the trail of circuit 170 and also can be replaced by a reference voltage, and the electric capacity that is used in the circuit all can use the less metal-oxide half field effect transistor electric capacity of volume to finish.
In the present embodiment, the positive input signal imported of input includes positive direct-current bias voltage signal (V
Dc_offset) and normal signal (V
Signal), its signal can be represented with equation (1):
V
In+=V
Dc_offset+ V
SignalEquation (1)
When first resistance 112 when being R1, second resistance 114 for R2, the 3rd resistance 122 for R3 and first electric capacity 124 for C1, after then first amplifier module 110 receives positive input signal, because the reference voltage that is input as zero potential of the normal phase input end of first operational amplifier 116, so first operational amplifier 116 can amplify positive input signal
Doubly.So the output end signal of first operational amplifier 116 can be represented with equation (2):
And the positive input signal after this amplification is exported in first filter circuit 120.
So when this amplification
When positive input signal doubly inputs to first filter circuit 120, the output end signal V of first filter circuit 120
A+Can represent with following equation:
Because this positive input signal includes positive direct-current bias voltage signal and normal signal, and the frequency of positive direct-current bias voltage signal is low than the frequency of normal signal, therefore suitably select the value of the 3rd resistance 122 and first electric capacity 124, can be with the normal signal filtering of higher-frequency, and the positive direct-current bias voltage signal can pass through.So, the output end signal V of first filter circuit 120
A+Can be revised as with equation (3) and represent:
And this positive direct-current bias voltage signal is exported to the inverting input of second operational amplifier 138.
When the 4th resistance 130 when being R4, the 5th resistance 134 for R5 and the 6th resistance 136 for R6, the inverting input of second operational amplifier 138 receives the positive direct-current bias voltage signal of being exported by first filter circuit 120, and because the reference voltage that is input as zero potential of the normal phase input end of second operational amplifier 138, so the output end signal of second operational amplifier 138 can be represented with equation (4):
And another input signal that inverting input received of second operational amplifier 138 is to be positive input signal, so another signal of second operational amplifier, 138 outputs just can be represented with equation (5):
So the signal of second operational amplifier, 138 outputs is to do addition for equation (4) and equation (5), can represent the signal of its output with equation (6):
From the output equation (6) of second operational amplifier 138, can find if select suitable resistance value to make
Can find that then the positive direct-current bias voltage signal is eliminated, and normal signal can be exaggerated
Doubly, so can being revised as with equation (7), the output equation of second operational amplifier 138 represents:
By suitable adjustment
Ratio, just can do the gain of normal signal and amplify or dwindle, eliminate Dc bias and the purpose of adjusting gain to reach, and the electric capacity that is used in the present embodiment all can utilize metal-oxide half field effect transistor (MOS) electric capacity to finish, and therefore can significantly reduce needed chip area.
Please refer to Fig. 3, it illustrates the waveform input signal figure of the clearing DC bias voltage and regulating gain device of one embodiment of the present invention, can find to include Dc bias signal and normal signal in Fig. 3 in defeated letter signal.
Then, please continue with reference to figure 4, it illustrates the signal output waveform figure of the clearing DC bias voltage and regulating gain device of one embodiment of the present invention, can find input signal in Fig. 4 after handling via this device, and the Dc bias signal in the input signal significantly is eliminated.
And the operating principle of the 3rd amplifier module 140, second filter circuit 150 and the 4th amplifier module 160 is identical with above-mentioned first amplifier module 110, first filter circuit 120 and second amplifier module 130, also can come the filtering normal signal, make that bearing the Dc bias signal can pass through via the electric capacity of the resistance value of resistance value and the 3rd electric capacity 152 of design the 11 resistance 154.
And when the 9th resistance 142 when being R9, the tenth resistance 146 for R10, the 12 resistance 162 for R12 and the 13 resistance 164, when its relation meets following formula for R13:
Then can reach and eliminate negative Dc bias signal and the effect of adjusting the normal signal gain, so the detailed operating principle of the 3rd amplifier module 140, second filter circuit 150 and the 4th amplifier module 160 is not given unnecessary details at this.
Then, please continue with reference to figure 2, it is the clearing DC bias voltage and regulating gain manipulated or operated apparatus that illustrates another preferred embodiment of the present invention, is applicable to the zero intermediate frequency receiver in the communication receiving system. circuit Figure 200 of this device for clearing DC bias voltage and regulating gain comprises first amplifier module 202, first low pass filter 204, second amplifier module 206, the 3rd amplifier module 208, second low pass filter 210, the 4th amplifier module 212 and voltage tracking circuit 214.
Wherein, first amplifier module 202 has first input end, second input and output.The first input end of first amplifier module 202 is to be electrically coupled to positive input signal, and its second input is to be electrically coupled to voltage to follow the trail of circuit 214.
First low pass filter 204 has input and output.The input of first low pass filter 204 is the outputs that are electrically coupled to first amplifier module 202, and its output is electrically coupled to second amplifier module 206.
The 3rd amplifier module 208 has first input end, second input and output.The first input end of the 3rd amplifier module 208 is to be electrically coupled to negative input signal, and its second input is to be electrically coupled to voltage to follow the trail of circuit 214.
Second low pass filter 210 has input and output.The input of second low pass filter 210 is the outputs that are electrically coupled to the 3rd amplifier module 208, and its output is to be electrically coupled to the 4th amplifier module 206.
The 4th amplifier module 212 has first input end, second input, the 3rd input and output.The first input end of the 4th amplifier module 212 is to be electrically coupled to negative input signal, and its second input is the output that is electrically coupled to second low pass filter 210, and its 3rd input is to be electrically coupled to voltage to follow the trail of circuit 214.
Voltage is followed the trail of circuit 214, has first input end, second input and output.Its first input end is to be electrically coupled to positive input signal, and its second input is to be electrically coupled to negative input signal, and exports the reference voltage of zero potential according to the size of positive input signal and negative input signal.
In the present embodiment, the enlargement ratio of first amplifier module 202 is A times, the first input end of first amplifier module 202 is electrically coupled to positive input signal, and this positive input signal amplified the input that A exports first low pass filter 204 after doubly to, and its second input receives the reference voltage of zero potential.
Because this positive input signal includes positive direct-current bias voltage signal and normal signal, and the frequency of positive direct-current bias voltage signal is low than the normal signal frequency.So, when this positive input signal that amplifies A times inputs to the input of first low pass filter 204, the A of higher-frequency times normal signal can be by 204 filterings of first low pass filter, and can be exaggerated B more doubly and export second input of second amplifier module 206 to than A times of positive direct-current bias voltage signal of low frequency.
Second amplifier module, 206 its first input ends receive positive input signal, and after amplifying C2 times, export output to, its second input is to receive the A*B positive direct-current bias voltage signal of being exported by first low pass filter 204 doubly, and export output to after amplifying C1 times, and its 3rd input is the reference voltage that receives zero potential.
So the output end signal of second amplifier module 206 is to do addition for first input end signal and second input end signal, and its relation is when meeting equation (8):
A*B*C1=-C2 equation (8)
Then the positive direct-current bias voltage signal can be eliminated, and the gain of normal signal can be exaggerated or dwindle.
And the enlargement ratio of the 3rd amplifier module 208 also is A times, exports in second low pass filter 210 after the negative input signal of negative Dc bias signal amplifies A times so also have.Second low pass filter 210 is also with the doubly negative normal signal filtering of the A of higher-frequency, and the doubly negative Dc bias signal of the A that stays is amplified B again exports in second input of the 4th amplifier module 212 after doubly.
The first input end of the 4th amplifier module 212 receives negative input signal, and also amplifies C1 and export output to after doubly. and its second input receives the A*B negative Dc bias signal of being exported by second low pass filter 210 doubly.
So, its output end signal is that the input signal of the first input end and second input is done addition, and when its relation meets equation (8), then negative Dc bias signal can be eliminated, and the gain of negative normal signal can be exaggerated or dwindle, so the detailed operating principle of the 3rd amplifier module 208 and the 4th amplifier module 212 is not given unnecessary details at this.
In sum, the frequency factor low than the frequency of normal signal because of utilizing the Dc bias signal uses low pass filter that the Dc bias signal is separated with normal signal in the present invention, eliminates Dc bias and the purpose of adjusting gain to reach.And the electric capacity that is used can use metal-oxide half field effect transistor electric capacity to finish in the present embodiment, can reduce needed chip area in design.
Though the present invention discloses as above with preferred implementation; but be not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be with being as the criterion defined in the claim.
Claims (17)
1. device for clearing DC bias voltage and regulating gain comprises:
One voltage is followed the trail of circuit, in order to provide a reference voltage accurate position;
One first amplifier module comprises:
One first resistance, an end of this first resistance is coupled to a positive input signal, and wherein this positive input signal comprises a positive direct-current bias voltage signal and an AC signal;
One first operational amplifier, the end of oppisite phase of this first operational amplifier is coupled to the other end of this first resistance, and the positive terminal of this first operational amplifier is coupled to this voltage and follows the trail of circuit; And
One second resistance, an end of this second resistance is coupled to the end of oppisite phase of this first operational amplifier, and the other end of this second resistance is coupled to the output of this first operational amplifier;
One first filter circuit comprises:
One the 3rd resistance, an end of the 3rd resistance is coupled to the output of this first operational amplifier; And
One first electric capacity, an end of this first electric capacity is coupled to the other end of the 3rd resistance, and the other end is coupled to earth terminal;
One second amplifier module comprises:
One the 4th resistance, an end of the 4th resistance is coupled to this positive input signal;
One the 5th resistance, an end of the 5th resistance is coupled to the output of this first filter circuit;
One second operational amplifier, the positive terminal of this second operational amplifier are coupled to this voltage and follow the trail of circuit, and the end of oppisite phase of this second operational amplifier is coupled to the other end of the 4th resistance and the 5th resistance; And
One the 6th resistance, an end of the 6th resistance is coupled to the end of oppisite phase of this second operational amplifier, and the other end of the 6th resistance is coupled to the output of this second operational amplifier;
Wherein, the 4th resistance is that R4, this first resistance are that R1, this second resistance are that R2 and the 5th resistance are R5, and meets following formula:
2. device for clearing DC bias voltage and regulating gain as claimed in claim 1, wherein this voltage tracking circuit comprises:
One the 7th resistance, an end of the 7th resistance is coupled to the positive terminal of this first operational amplifier and this second operational amplifier, and the other end of the 7th resistance is coupled to this positive input signal;
One the 8th resistance, one end of the 8th resistance is coupled to the positive terminal of this first operational amplifier and this second operational amplifier, the other end of the 8th resistance is coupled to a negative input signal, wherein should comprise a negative Dc bias signal and an AC signal by negative input signal; And
One second electric capacity, an end of this second electric capacity is coupled to the positive terminal of this first operational amplifier and this second operational amplifier, and the other end of this second electric capacity is coupled to earth terminal;
Wherein, the 7th resistance is that R7 and the 8th resistance are R8, and meets following formula:
R7＝R8。
3. device for clearing DC bias voltage and regulating gain as claimed in claim 1, it is applicable to a communication receiving system.
4. device for clearing DC bias voltage and regulating gain as claimed in claim 3, wherein this communication receiving system is a zero intermediate frequency receiver.
5. device for clearing DC bias voltage and regulating gain as claimed in claim 1, wherein this voltage tracking circuit is a reference voltage.
6. device for clearing DC bias voltage and regulating gain as claimed in claim 1, wherein the 6th resistance is a variable resistor.
7. device for clearing DC bias voltage and regulating gain as claimed in claim 1, wherein this first electric capacity is a variable capacitance.
8. device for clearing DC bias voltage and regulating gain as claimed in claim 1, wherein this first electric capacity is a metal-oxide half field effect transistor (MOS) electric capacity.
9. device for clearing DC bias voltage and regulating gain as claimed in claim 1 also comprises:
One the 3rd amplifier module comprises:
One the 9th resistance, an end of the 9th resistance is coupled to a negative input signal;
One the 3rd operational amplifier, the end of oppisite phase of the 3rd operational amplifier is coupled to the other end of the 9th resistance, and the positive terminal of the 3rd operational amplifier is coupled to this voltage and follows the trail of circuit; And
1 the tenth resistance, an end of the tenth resistance is coupled to the end of oppisite phase of the 3rd operational amplifier, and the other end of the tenth resistance is coupled to the output of the 3rd operational amplifier;
One second filter circuit comprises:
1 the 11 resistance, an end of the 11 resistance is coupled to the output of the 3rd operational amplifier; And
One the 3rd electric capacity, an end of the 3rd electric capacity is coupled to the other end of the 11 resistance, and the other end of the 3rd electric capacity is coupled to earth terminal;
One the 4th amplifier module comprises:
1 the 12 resistance, an end of the 12 resistance is coupled to this negative input signal;
1 the 13 resistance, an end of the 13 resistance is coupled to the output of this second filter circuit;
One four-operational amplifier, the positive terminal of this four-operational amplifier are coupled to this voltage and follow the trail of circuit, and the end of oppisite phase of this four-operational amplifier is coupled to the other end of the 12 resistance and the 13 resistance; And
1 the 14 resistance, an end of the 14 resistance couples the end of oppisite phase of this four-operational amplifier, and the other end of the 14 resistance is coupled to the output of this four-operational amplifier,
Wherein, the 12 resistance is that R12, the 9th resistance are that R9, the tenth resistance are that R10 and the 13 resistance are R13, and meets following formula:
10. device for clearing DC bias voltage and regulating gain as claimed in claim 9, wherein the 14 resistance is a variable resistor.
11. device for clearing DC bias voltage and regulating gain as claimed in claim 9, wherein the 3rd electric capacity is a variable capacitance.
12. device for clearing DC bias voltage and regulating gain as claimed in claim 9, wherein the 3rd electric capacity is a metal-oxide half field effect transistor (MOS) electric capacity.
13. a device for clearing DC bias voltage and regulating gain comprises:
One first amplifier module, comprise a first input end and an output, this first input end of this first amplifier module is coupled to a positive input signal, wherein this positive input signal comprises a positive direct-current bias voltage signal and an AC signal, the signal of this output of this first amplifier module be this first amplifier module this first input end signal A doubly;
One first low pass filter comprises an input and an output, and this input of this first low pass filter is coupled to this output of this first amplifier module, in order to the direct current bias voltage in the signal of exporting its reception, and with this Dc bias amplification B doubly; And
One second amplifier module, comprise a first input end, one second input and an output, this first input end of this second amplifier module is coupled to the output of this first low pass filter, this second input of this second amplifier module is coupled to this positive input signal, wherein the signal of this output of this second amplifier module be for the C1 of the signal of this first input end of this second amplifier module doubly with the C2 summation doubly of the signal of this second input of this second amplifier module, and meet following formula:
A*B*C1＝-C2。
14. device for clearing DC bias voltage and regulating gain as claimed in claim 13 also comprises:
One the 3rd amplifier module, comprise a first input end and an output, this first input end of the 3rd amplifier module is coupled to a negative input signal, wherein should comprise a negative Dc bias signal and an AC signal by negative input signal, the signal of this output of the 3rd amplifier module is A times of signal of this first input end of the 3rd amplifier module;
One second low pass filter comprises an input and an output, and this input of this second low pass filter is coupled to this output of the 3rd amplifier module, in order to the Dc bias in the signal of exporting its reception, and with this Dc bias amplification B doubly; And
One the 4th amplifier module, comprise a first input end, one second input and an output, this first input end of the 4th amplifier module is coupled to the output of this second low pass filter, this second input of the 4th amplifier module is coupled to this negative input signal, wherein the signal of this output of the 4th amplifier module be for the C1 of the signal of this first input end of the 4th amplifier module doubly with the C2 summation doubly of the signal of this second input of the 4th amplifier module.
15. device for clearing DC bias voltage and regulating gain as claimed in claim 14, also comprise voltage tracking circuit, be coupled to this positive input signal and should bear input signal, in order to export the accurate position of a reference voltage, wherein this first amplifier module comprises that also one second input and this second amplifier module also comprise one the 3rd input, the 3rd amplifier module comprises that also one second input and the 4th amplifier module also comprise one the 3rd input, and above-mentioned input all is connected to the accurate position of this reference voltage.
16. device for clearing DC bias voltage and regulating gain as claimed in claim 13, it is applicable to a communication receiving system.
17. device for clearing DC bias voltage and regulating gain as claimed in claim 16, wherein this communication receiving system is a zero intermediate frequency receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410095599 CN1783857B (en) | 2004-12-02 | 2004-12-02 | Device for clearing DC bias voltage and regulating gain |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410095599 CN1783857B (en) | 2004-12-02 | 2004-12-02 | Device for clearing DC bias voltage and regulating gain |
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| CN1783857A CN1783857A (en) | 2006-06-07 |
| CN1783857B true CN1783857B (en) | 2010-05-05 |
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| CN 200410095599 Expired - Fee Related CN1783857B (en) | 2004-12-02 | 2004-12-02 | Device for clearing DC bias voltage and regulating gain |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101867350B (en) * | 2009-04-17 | 2013-08-21 | 杭州中科微电子有限公司 | Zero-intermediate-frequency/low-intermediate-frequency configurable variable gain amplifier |
| CN102340301B (en) * | 2011-10-18 | 2013-09-04 | 四川和芯微电子股份有限公司 | Direct current voltage offset cancellation circuit and system |
| CN116009629A (en) * | 2022-12-29 | 2023-04-25 | 苏州浪潮智能科技有限公司 | A bias voltage correction circuit, method and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748681A (en) * | 1995-10-27 | 1998-05-05 | Lucent Technologies Inc | Offset correction for a homodyne radio |
| US20040119539A1 (en) * | 2002-12-20 | 2004-06-24 | Shivakumar Seetharaman | Dc offset cancellation circuit, system and method |
| CN1520032A (en) * | 2003-01-20 | 2004-08-11 | 矽统科技股份有限公司 | DC Offset Cancellation Circuit Applied to Variable Gain Amplifier |
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2004
- 2004-12-02 CN CN 200410095599 patent/CN1783857B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748681A (en) * | 1995-10-27 | 1998-05-05 | Lucent Technologies Inc | Offset correction for a homodyne radio |
| US20040119539A1 (en) * | 2002-12-20 | 2004-06-24 | Shivakumar Seetharaman | Dc offset cancellation circuit, system and method |
| CN1520032A (en) * | 2003-01-20 | 2004-08-11 | 矽统科技股份有限公司 | DC Offset Cancellation Circuit Applied to Variable Gain Amplifier |
Non-Patent Citations (1)
| Title |
|---|
| 全文. |
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