CN1783020A - Interrupt managing method for embedded operation system based on PowerPC system structure - Google Patents

Abstract

The invention relates to an interrupt management method of an embedded operating system based on the PowerPC system structure, the steps are as follows: the interrupt is divided into two types: system interrupt and user interrupt, and the user interrupt service program is divided into a first-class interrupt service program and a second-class interrupt Service program; when a user interrupt occurs, the hardware first responds to the interrupt; then save the context, switch the stack, and maintain interrupt nesting to ensure that the interrupted task can continue to run after the interrupt processing is completed; Find and call the corresponding interrupt service program in the vector table, then maintain interrupt nesting, stack switching, and finally restore the context, and the processor continues to run the task that was originally interrupted. The invention has the following advantages: the execution efficiency and utilization efficiency of the interrupt are improved, and the control and use of the interrupt are facilitated. Prevents stack overflow exceptions caused by nested interrupts, and improves the controllability and predictability of the user stack size.

Description

Interrupt Management Method of Embedded Operating System Based on PowerPC Architecture

technical field

The invention relates to an embedded real-time operating system technology, mainly realizing an interrupt management method of an embedded operating system based on PowerPC system structure.

Background technique

Interrupts are an essential mechanism for the operating system. Interrupts are used to notify the processor that a certain event has occurred. Once the interrupt is recognized, the processor will save data reflecting the current task state (such as the value in the register), which is called "context"; after saving the context, the processor will execute a special interrupt service routine to respond to the event that caused the interrupt; Finally, the context is restored and the interrupted task continues. The interrupt mechanism is used to deal with some unexpected internal and external emergencies. Due to its unpredictable characteristics, the robustness of the interrupt mechanism is particularly important for an operating system, especially a real-time embedded operating system. It is directly related to the stability of the operating system and the efficiency of operation. Due to the combination of the interrupt mechanism and the operating system, the interrupt mechanism must ensure the normal operation of the task, which requires initial and aftermath work when the interrupt occurs and the interrupt exits.

Currently popular microkernel embedded operating systems, such as uC/OS, do not provide interrupt encapsulation and management. Users need to define their own interrupt service program interface, context protection, context recovery, and binding to interrupt sources. It is very inconvenient for users to write interrupt service programs, which will inevitably increase the difficulty of user development, prolong the development cycle and reduce the stability of the system.

Interrupt management is different from other mechanisms such as task management of the operating system, and it has a great correlation with the hardware architecture. Therefore, considering the three major embedded system indicators of stability, execution efficiency and system overhead, specific interrupt management methods need to be implemented for different architectures and different processor series.

Contents of the invention

The invention solves the defects in the general interrupt management, and provides an interrupt management method of the embedded operating system based on the PowerPC architecture.

The interrupt management method of this embedded operating system based on PowerPC architecture, the implementation steps are as follows:

1) Interrupts are divided into two types: system interrupts and user interrupts. System interrupts are centrally managed by the system to handle interrupts caused by the system, such as exceptions caused by abnormal operations and reset (Reset) interrupts; user interrupts handle user-available External interrupts, such as serial port interrupts, analog-to-digital conversion interrupts, etc. System interrupts refer to all interrupts except external interrupts and maskable external breakpoints. When a system interrupt occurs, it will enter the unified system interrupt service program entry, and only save a small amount of necessary register data before executing the interrupt service program. User interrupts refer to external interrupts and maskable external breakpoints. External interrupts are triggered by external pins, and maskable external breakpoint interrupts are generated by other modules in the chip. The hardware system does not distinguish specific user interrupts, but uses a unified user interrupt service The program entry schedules user interrupts by maintaining a user interrupt vector table. The invention provides entry encapsulation for system interrupt and user interrupt respectively, all system interrupts uniformly use one system interrupt entry, all user interrupts uniformly use one user interrupt as the entry, and interrupts are respectively operated in the two entries.

2) The user interrupt service program is divided into a first-class interrupt service program and a second-class interrupt service program. The user is not allowed to call system services in the first-class interrupt service program. There is no operation that affects task scheduling in this type of interrupt service program. Interrupt service After the program ends, the system will return to the place where the interrupt occurred and continue to run; in the second type of interrupt service program, system services are allowed to be called, and when the interrupt service program ends, task scheduling will be triggered to ensure that the task with the highest priority is executed;

3) When a user interrupt occurs, the hardware first responds to the interrupt; then saves the context, switches the stack, and maintains interrupt nesting to ensure that the interrupted task can continue to run after the interrupt processing is completed; Find and call the corresponding interrupt service program in the vector table, then maintain interrupt nesting, stack switching, and finally restore the context, and the processor continues to run the task that was interrupted; maintaining interrupt nesting means that in the process of processing interrupts, shielding The low-priority interrupt prevents the low-priority interrupt from interfering with the execution of the high-priority interrupt service routine; after the user interrupt program returns, the masked interrupt is resumed. Manage interrupt nesting at the software layer. Multi-level interrupt nesting uses the system's stack space to save the context, while the task's context will be saved in the task's stack space, which is needed when the processor switches between nested interrupts and user tasks. Switch between system stack and task stack.

4), for the second type of interrupt service program, when returning to the task layer from the interrupt, task scheduling is required to ensure that the high priority task can run immediately; when saving and restoring the context, only the volatile register is saved and restored for the first type of interrupt value, and for the second type of interrupt, it is also necessary to save and restore the value of the non-volatile register.

The present invention has the following advantages:

1. The present invention classifies interrupts and interrupt service routines. Interrupts are divided into system interrupts and user interrupts. Different processing mechanisms are used for different types of interrupt service routines, thereby improving the execution efficiency of interrupts.

2. In the present invention, interrupt nesting based on the PowerPC system is supported, and a maximum of 16 layers of nesting can be supported, which improves the utilization efficiency of interrupts and facilitates the control and use of interrupts.

3. The present invention provides a unified interrupt management interface, and the user can configure the attributes of the interrupt service program by calling these interfaces. The invention hides complex interrupt processing details, and improves the efficiency and convenience for users to develop interrupt service programs in the PowerPC architecture.

4. The present invention introduces the system stack to handle nested interrupts, which effectively prevents stack overflow exceptions caused by nested interrupts, improves the controllability and predictability of the user stack size, and saves memory overhead.

This interrupt mechanism has been strictly tested on the MPC555 hardware platform of the PowerPC architecture, which proves that the mechanism has good performance and stability.

Description of drawings

System interrupt processing flowchart in Fig. 1 of the present invention;

A flow chart of a class of user interruption processing in Fig. 2 of the present invention;

Fig. 3 is a flow chart of the second type of user interruption processing in the present invention.

Detailed ways

Below in conjunction with the MPC555 platform of PowerPC architecture, the present invention is further introduced:

The present invention divides the whole interrupt system into two types, one is system interrupt and the other is user interrupt, and these two types of interrupts together constitute the interrupt system of the PowerPC architecture.

●System interruption

In the PowerPC architecture, system interrupts refer to all interrupts except external interrupts and maskable external breakpoints. When a system interrupt occurs, it will enter the unified system interrupt service program entry, and only save a small amount of necessary register data before executing the interrupt service program. For example, on the MPC555 hardware platform, the floating-point number exception interrupt belongs to the system interrupt, as shown in Figure 1, the processing process when the interrupt occurs is as follows:

1. When an interrupt occurs, the hardware finds a unified system interrupt entry from the interrupt vector table, and executes the following steps from this entry.

2. Save the corresponding register data. On the MPC555 hardware platform, these registers include general integer registers GPR0-GPR13, LR, CR, MSR, SRR0, SRR1, XER, and CTR.

3. Obtain the interrupt source from a specific register, and call the system interrupt service routine according to the interrupt source. In this example, the floating-point number exception system interrupt service routine is called.

4. Restore the register data saved in step 2.

5. Interrupt return, continue to run the program from the place where the interrupt occurred.

● User Interrupt

In the PowerPC architecture, user interrupts refer to external interrupts and maskable external breakpoints. The external interrupt is triggered by an external pin, and the maskable external breakpoint interrupt is generated by other modules on-chip. In the present invention, the hardware system does not distinguish specific user interrupts, but uses a unified user interrupt service program entry. The present invention schedules user interrupts by maintaining a user interrupt vector table. The user interrupt service routine is divided into a type of user interrupt service routine and a second type of interrupt service routine.

For example, in an example on the MPC555 platform of the PowerPC architecture, the user configures a class I interrupt service program for a serial port interrupt. When the serial port interrupt occurs, the interrupt service program is responsible for some simple data processing, as shown in Figure 2 Shown, the interrupt handling process is as follows:

6. When an interrupt occurs, the hardware finds a unified user interrupt entry from the interrupt vector table, and executes the following steps from this entry.

7. Save the return address and a small number of registers to be used in the following steps, such as general registers GPR2-GPR3.

8. If it is from the task to enter the interrupt, it needs to switch from the task stack to the system stack. If it is a nested interrupt, it does not need to switch the stack.

9. Mask interrupts with a lower priority than this interrupt.

10. Obtain the interrupt source, and then find the user interrupt service program of the serial port interrupt from the user interrupt vector table according to the value and execute it.

11. If the task is returned from an interrupt, it needs to switch from the system stack back to the task stack. If it exits from a nested interrupt, it does not need to switch the stack.

12. Restore the registers saved in step 2.

13. Exit from the interrupt and continue to execute the interrupted program.

In the same instance, the user configures a class 2 interrupt service program for an analog-to-digital conversion interrupt. When the interrupt occurs, the interrupt service program will activate a task with a higher priority for processing analog-to-digital conversion to ensure After the interrupt exits, the task can be executed even if the interrupt processing process is as follows:

1. When an interrupt occurs, the hardware finds a unified user interrupt entry from the interrupt vector table, and executes the following steps from this entry.

2. Save the return address and a small number of registers to be used in the following steps, such as general registers GPR2-GPR3.

3. If it is from the task to enter the interrupt, it needs to switch from the task stack to the system stack. If it is a nested interrupt, it does not need to switch the stack.

4. Save the non-volatile registers. On the MPC555 hardware platform, the non-volatile registers include general-purpose integer registers GPR14-GPR31, CR, XER, and CTR. Therefore, it is better to save and restore the second type of interrupt than the first type of interrupt. Values of more registers.

5. Mask interrupts with a lower priority than this interrupt.

6. Obtain the interrupt source, find the user interrupt service program of the serial port interrupt from the user interrupt vector table and execute it. This program activates a high-priority task.

7. If the task is returned from the interrupt, it needs to switch from the system stack back to the task stack and restore the value of the non-volatile register. If it exits from the nested interrupt, it does not need to switch the stack.

8. Restore all registers saved in step 2 and step 4.

9. Exit from the interrupt. If you exit from the nested interrupt, continue to run the interrupt service program; if you return to the task layer, because a high-priority task is activated, the scheduler is triggered to run the high-priority task instead. Instead of continuing to execute the interrupted program.

Claims (7)

1, a kind of interrupt management method based on the embedded operating system of PowerPC architecture, it is characterized in that: the realization step is as follows: 1) Interrupts are divided into two types: system interrupts and user interrupts. System interrupts are managed centrally by the system to handle interrupts caused by the system; user interrupts handle external interrupts available to users; 2) The user interrupt service program is divided into a first-class interrupt service program and a second-class interrupt service program. The user is not allowed to call system services in the first-class interrupt service program. There is no operation that affects task scheduling in this type of interrupt service program. Interrupt service After the program ends, the system will return to the place where the interrupt occurred and continue to run; in the second type of interrupt service program, system services are allowed to be called, and when the interrupt service program ends, task scheduling will be triggered to ensure that the task with the highest priority is executed; 3) When a user interrupt occurs, the hardware first responds to the interrupt; then saves the context, switches the stack, and maintains interrupt nesting to ensure that the interrupted task can continue to run after the interrupt processing is completed; Find and call the corresponding interrupt service routine in the vector table, then maintain interrupt nesting, stack switching, and finally restore the context, and the processor continues to run the previously interrupted task; 4) For the second-type interrupt service program, when returning from the interrupt to the task layer, task scheduling is required to ensure that high-priority tasks can run immediately; when saving and restoring the context, only save and restore in the project for a type of interrupt The value of the volatile register used, and the value of the non-volatile register needs to be saved and restored for the second type of interrupt. 2. The interrupt management method of the embedded operating system based on PowerPC architecture according to claim 1, characterized in that: maintaining interrupt nesting means that in the process of interrupting, shielding low-priority interrupts prevents low-priority Interrupts at the highest level interfere with the execution of the high-priority interrupt service routine; after the user interrupt routine returns, the masked interrupt is resumed. 3, the interrupt management method based on the embedded operating system of PowerPC architecture according to claim 1, it is characterized in that: manage interrupt nesting on software layer, the stack space of multi-level interrupt nesting uses system to preserve context, The context of the task will be saved in the stack space of the task. When the processor switches between nested interrupts and user tasks, it needs to switch between the system stack and the task stack. 4. The interrupt management method of an embedded operating system based on PowerPC architecture according to claim 1, wherein: system interrupts refer to all interrupts except external interrupts and maskable external breakpoints. When a system interrupt occurs, it will enter the unified system interrupt service program entry, and only save a small amount of necessary register data before executing the interrupt service program. 5, the interrupt management method based on the embedded operating system of PowerPC architecture according to claim 1 is characterized in that: user interrupt refers to external interrupt and shieldable external breakpoint, external interrupt is triggered by external pin, shieldable External breakpoint interrupts are generated by other modules in the chip. The hardware system does not distinguish specific user interrupts, but uses a unified user interrupt service program entry to schedule user interrupts by maintaining a user interrupt vector table. 6. The interrupt management method of the embedded operating system based on PowerPC architecture according to claim 1, characterized in that: the user has configured a section of a class of interrupt service program for a serial port interrupt, and when the serial port interrupt occurred, the interrupt The process is as follows: 1), when an interrupt occurs, the hardware finds a unified user interrupt entry from the interrupt vector table, and executes the following steps from this entry; 2), save the return address and a small number of registers to be used in the following steps; 3) If it is from the task to enter the interrupt, it needs to switch from the task stack to the system stack, if it is a nested interrupt, it does not need to switch the stack; 4) Shield interrupts with a lower priority than the interrupt; 5), obtain the interrupt source, then find and execute the user interrupt service program of the serial port interrupt from the user interrupt vector table according to the value; 6) If the task is returned from the interrupt, it needs to switch from the system stack back to the task stack, and if it exits from the nested interrupt, it does not need to switch the stack; 7), restore the register saved in step 2; 8) Exit from the interrupt and continue to execute the interrupted program. 7, the interrupt management method based on the embedded operating system of PowerPC architecture according to claim 1, is characterized in that: the user has configured a second class interrupt service program for an analog-to-digital conversion interrupt, and when this interrupt occurred, interrupt The service program will activate a task with a higher priority to process analog-to-digital conversion to ensure that the task can be run even after the interrupt exits. The interrupt processing process is as follows: 1), when an interrupt occurs, the hardware finds a unified user interrupt entry from the interrupt vector table, and executes the following steps from this entry; 2), save the return address and a small number of registers to be used in the following steps; 3) If it is from the task to enter the interrupt, it needs to switch from the task stack to the system stack, if it is a nested interrupt, it does not need to switch the stack; 4), save the non-volatile registers, on the MPC555 hardware platform, the non-volatile registers include general integer registers GPR14-GPR31, CR, XER, CTR; 5) Shield interrupts with a lower priority than the interrupt; 6), obtain the interrupt source, find and execute the user interrupt service program of the serial port interrupt from the user interrupt vector table, and this program activates a high-priority task; 7) If the task is returned from the interrupt, it needs to switch from the system stack back to the task stack and restore the value of the non-volatile register. If it exits from the nested interrupt, it does not need to switch the stack; 8), restore all registers saved in step 2 and step 4; 9) Exit from the interrupt, if exit from the nested interrupt, continue to run the interrupt service routine; if return to the task layer, because a high-priority task is activated, the scheduler is triggered to run the high-priority task Instead of continuing to execute the interrupted program.

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