CN1779662A - Improved virtual address translation method and device - Google Patents

Abstract

The invention discloses an improved virtual address transformation method and its device. The method includes using data locality to compare the virtual address that needs to be transformed into a physical address with the last transformed virtual address. If they belong to the same virtual page table, then The random memory (RAM) part of the translation lookaside buffer (TLB) is not accessed, but the physical page table address obtained by the last conversion is directly used to reduce the number of accesses to the random memory in the translation lookaside buffer; and the instruction translation lookaside buffer (ITLB) and data translation look-aside buffer (DTLB) share a single-read port random access memory; and postpone the physical page table address output by random access memory and the selection operation of the last used physical page table address saved, which can reduce translation The power and area effects of the backing buffer section without reducing the performance of the processor and increasing the delay of the circuit.

Description

Improved virtual address translation method and device

technical field

The invention relates to the technical field of microprocessor architecture, in particular to a design method of a translation lookaside buffer (TLB, Translation Lookaside Buffer) responsible for converting a virtual address into a physical address in a processor.

Background technique

In the virtual storage system, the virtual address must be converted into a physical address. The translation lookaside buffer in the memory management part of the processor is designed to speed up this address conversion. The translation lookaside buffer stores each logical page address and physical address. The table entry of the page address, and the mapping relationship between the two is established, so that the mapping process from the virtual address to the physical address can be completed inside the processor, and the conversion from the virtual address to the physical address can be accelerated.

The translation look-aside buffer is usually composed of two parts, one is to store the virtual address page table entry, which is used for the content comparator (CAM) of the fully connected comparison with the accessed virtual address, and the other is to store the physical address page table entry, through the index Random access memory (RAM) for lookups. When a memory access address accesses the translation lookaside buffer, the virtual page table entry that matches the memory access address is first searched in parallel in the content comparator, and after finding it, accesses the random access memory according to the index of the found location to obtain the corresponding address of the access address The physical page table entry where the physical address is located.

Since the processor has two parallel processes of instruction fetching and data accessing, regardless of instruction fetching or data accessing, it is necessary to access the translation backup buffer component to perform the process of converting virtual addresses into physical addresses. The traditional translation backup buffer There are two ways to implement the buffer: one is to use two translation lookaside buffers, namely: Instruction Translation Lookaside Buffer (ITLB, Instruction Translation Lookaside Buffer) and Data Translation Lookaside Buffer (DTLB, Data Translation Lookaside Buffer), which are processed separately Instruction fetching and data memory access operations; the other is to use a shared translation lookaside buffer, which accepts both instruction fetching and data memory accessing. The disadvantage of the first method in the traditional design is that the circuit area is large and the power consumption is high, while the disadvantage of the second method in the traditional design is that the performance of the processor will be negatively affected because the instruction fetch and data memory access occur at the same time When the second method cannot be processed at the same time, the processing of one of the accesses must be delayed. If the second method uses a dual-port content comparator and a dual-port random access memory, it will cause the disadvantages of increased circuit area and increased power consumption.

Contents of the invention

The purpose of the present invention is to overcome the defective of prior art; Improve the conversion process from virtual address to physical address, reduce the area and power consumption of translation look-aside buffer circuit, also do not affect the performance of processor and circuit sequence simultaneously, thereby provide a An improved virtual address exchange method and a device for realizing the method.

In order to solve the above-mentioned technical problems, the present invention provides an improved virtual address conversion method, that is, a method for converting from a virtual address to a physical address, comprising the following steps:

a) The instruction translation backup buffer and the data translation backup buffer compare the virtual address of this fetch/data with the virtual address/data virtual address of the last fetch;

b) judge whether they belong to the same page table or directly mappable space, if yes, perform step g), if not, perform the next step;

c) The instruction translation back buffer and the data translation back buffer share a single-read port random access memory, and accept queries to physical addresses;

d) The instruction translation back buffer and the data translation back buffer save the transformed physical address in the register, and respectively postpone the selection with the physical page table address output by the random access memory;

e) When the instruction translation back buffer and/or the data translation back buffer are used, the physical addresses of the two sources (this transformation and the last transformation) are used respectively to generate two target signals respectively;

f) respectively select the two target signals generated in step e), and output the required result signal;

g) Do not access the random access memory, use the saved last changed address, and execute step e).

In the above scheme, in the steps a), b) and g), there are the following two situations. When the virtual address is transformed into a physical address, the random access memory of the translation look-aside buffer is not accessed. The address that needs to be transformed caused by the operation is compared with the address that has been transformed caused by the last instruction fetch operation. If the same address as the previous address falls in the same virtual page table entry, the random access memory is no longer accessed, and the previous address is used directly. The physical page table address result obtained by one transformation, the address transformation caused by data access also uses the same process as the address transformation caused by instruction fetching. Another case is that for the virtual address caused by instruction fetch and data memory access operations For physical address conversion, if the address space where the virtual address is located is a direct mapping space, the address mapping can be completed without looking up the mapping relationship table entry of the translation lookaside buffer, without accessing the random access memory of the translation lookaside buffer.

In the above scheme, in the steps d) and e), if the virtual address is in the same page table as the virtual address during the next address translation, then use the physical address saved in the register, otherwise query the translation back buffer The random memory of the device uses the physical page table address output by the random memory.

A device for implementing an improved virtual address conversion method provided by the present invention includes a content comparator circuit for storing and comparing virtual page table addresses and a random access memory circuit for storing physical page table addresses, instruction fetching and data accessing have their own The content comparator circuit of the content comparator circuit, that is, the first content comparator circuit and the second content comparator circuit, and the first two alternative circuit for selecting the index of the comparison output of the two content comparator circuits, and the instruction fetch and Data access shares a random access memory circuit with only one read port, and also includes comparison between the virtual address of this instruction fetch transformation and the virtual address of the previous instruction fetch transformation to determine whether the fetch virtual address belongs to the same page table or can be directly accessed. The first comparing circuit and the first judging circuit of the mapping space, the second comparing circuit and the second judging circuit between the virtual address of this data access transformation and the virtual address of the last data access transformation, save the instruction fetch last time The first register group of the physical page table address obtained after the transformation and the second register group of the physical page table address obtained after the last transformation for storing data access, and the first register group outputs a 1-bit result through the third comparison circuit signal and the physical page table address output by the random access memory circuit through the fourth comparator circuit to output a second two-choice circuit between the result signal, and the second register group outputs the 1-bit result signal through the sixth compare circuit and the random The physical page table address output by the memory circuit is output through the third two-one selection circuit between the fifth comparison circuit and the 1-bit result signal, and the required result is output through the second two-one selection circuit and the third two-one selection circuit Signal.

In the above scheme, the third comparison circuit is a tag (TAG) comparison circuit of the instruction cache (CACHE), which is used to compare the tag value of the instruction cache with the content in the first register group, and output a 1-bit result Signal.

In the above solution, the fourth comparison circuit is a tag comparison circuit of the instruction cache, which is used to compare the tag value of the instruction cache with the content of the physical page table address output by the random access memory, and output a 1-bit result signal.

In the above solution, the fifth comparison circuit is a tag comparison circuit of the data cache, which is used to compare the tag value of the data cache with the content of the physical page table address output by the random access memory, and output a 1-bit result signal.

In the above solution, the sixth comparison circuit is a tag comparison circuit of the data cache, used for comparing the tag value of the data cache with the content in the second register group, and outputting a 1-bit result signal.

In the above scheme, the single-read port random access memory circuit is used to maintain the physical page table address and the random access memory of related control signals, and the instruction translation backup buffer and the data translation backup buffer share the single-read port random access memory circuit, The single-read port random access memory circuit preferentially handles the address conversion access of instruction fetching.

In the above solution, the single-read port RAM circuit can be replaced by a single-read port register file circuit.

In the above solution, the first comparing circuit and the first judging circuit are used to generate an enable signal for accessing random access memory. Mapping space before accessing random access memory.

In the above solution, the second comparing circuit and the second judging circuit are used to generate an enable signal for accessing the random access memory, if the address converted twice before and after is not in the same page table, and the address converted this time does not belong to the directly accessible Mapping space before accessing random access memory.

In the above solution, the second one-of-two selection circuit uses the 1-bit output result of the fourth comparison circuit after the instruction backup buffer accesses the random access memory, otherwise selects the 1-bit output result of the third comparison circuit; the third After the data back-up buffer accesses the RAM, the one-of-two selection circuit uses the 1-bit output result of the fifth comparison circuit, otherwise selects the 1-bit output result of the sixth comparison circuit.

As can be seen from the above, the present invention uses data locality through innovative design to compare the virtual address that needs to be transformed into a physical address with the virtual address that was transformed last time. If they belong to the same virtual page table, the RAM of the translation backup buffer will not be accessed. part, and directly use the physical page table address obtained by the last conversion to reduce the number of accesses to the random access memory in the translation lookaside buffer; and the instruction translation lookaside buffer and the data translation lookaside buffer share a single read port random access memory; and Postponing the selection operation of the physical page table address output by the random memory and the saved last used physical page table address, which can achieve the effect of reducing the power consumption and area of the translation lookaside buffer part without reducing the performance of the processor and increase the delay of the circuit.

Description of drawings

Fig. 1 is the flow chart of the method embodiment of converting from virtual address to physical address of the present invention;

Fig. 2 is a schematic block diagram of an embodiment of the composition of the improved virtual address conversion device of the present invention.

Detailed ways

The technical scheme of the present invention will be described in detail below with reference to the accompanying drawings. The applicant also applied for another invention titled "A Method and Device for Converting from Virtual Address to Physical Address" on the same day, which is hereby taken as a reference .

The object of the present invention is to improve the conversion process from virtual address to physical address, reduce the area and power consumption of the translation lookaside buffer circuit, and at the same time, do not affect the performance and circuit timing of the processor.

Referring to Fig. 1, an improved virtual address translation method includes the following steps:

Step 100, the instruction translation backup buffer and the data translation backup buffer judge and compare the virtual address of the instruction fetch/data with the virtual address/data virtual address of the last instruction fetch;

Step 110, judging whether they belong to the same page table or directly mappable space? If yes, perform step 160, if not, perform the next step;

In steps 100, 110 and 160, in the following two cases, the random access memory of the translation look-aside buffer is not accessed when the virtual address is transformed into a physical address. Compare the converted address caused by the instruction fetch operation. If the last address falls in the same virtual page table entry, the random access memory is no longer accessed, and the physical page table address result obtained by the previous conversion is directly used. The address transformation caused by data access also uses the same process as the address transformation caused by instruction fetch. Since processor instruction fetch and memory access have high locality, this design can greatly reduce the access to random memory. times, to reduce power consumption; in another case, for the transformation from virtual address to physical address caused by fetching instructions and data access operations, if the address space where the virtual address is located is a direct mapped space (unmapped), The address mapping that can be completed without looking up the mapping relationship table items of the translation backup buffer does not access the random access memory of the translation backup buffer, so that the random access memory can be made longer by reducing the method of accessing the random access memory of the translation backup buffer in a low power state;

Step 120, the command translation backup buffer and the data translation backup buffer share a single-read port random access memory, and accept the inquiry of the physical address. Due to the design of step 110, the number of times of accessing the translation backup buffer random access memory during address conversion will decrease Significantly reduced, so when the instruction translation back buffer and the data translation back buffer share the same random access memory, there are few conflicts between the two, and the performance of the processor will not be affected;

In step 130, the instruction translation back buffer and the data translation back buffer save the transformed physical address, and respectively postpone the selection with the physical page table address output by the random access memory;

Step 140, using the physical addresses of the two sources (this conversion and last conversion) respectively when the instruction translation backup buffer and the data translation backup buffer are in use, respectively generate two target signals;

Step 150, respectively select the two target signals, and output the required result signal.

In step 130 - in step 150, after the instruction translation back buffer and the data translation back buffer share a random access memory, the instruction translation back buffer and the data translation back buffer need to use registers to convert the respective addresses obtained each time The physical address is saved. If the virtual address is in the same page table as the virtual address at the next address conversion, the physical address saved in the register is used. Otherwise, the random memory of the translation backup buffer is queried and the physical page output by the random memory is used. table address, which requires a two-choice circuit to select the source of the physical page table address. In order to avoid increasing the delay of the circuit as much as possible, it does not directly select the output of the register storing the physical page table address and the random access memory, but in the back In a circuit that needs to use physical addresses, use the physical addresses of these two sources at the same time, and after generating two target signals, select these two target signals, thereby avoiding and associated control signals for increased load and strong drive.

Step 160, do not access the random access memory, and use the saved last converted address.

The device for converting from virtual address to physical address will be described in detail below in conjunction with FIG. 2 .

With reference to Fig. 2, make the device of an improved virtual address transformation, comprise first comparing circuit 10, the second comparing circuit 13, the 3rd comparing circuit 20, the 4th comparing circuit 21, the 5th comparing circuit 22, the 6th comparing circuit 23 , the first content comparator circuit 11, the second content comparator circuit 12, the first judging circuit 14, the second judging circuit 15, the first two select one circuit 16, the second two select one circuit 24, the third two select one Circuit 25 , first register group 18 , second register group 19 and single read port random access memory circuit 17 .

The first comparison circuit 10 is used to compare with the virtual address fetched last time, the first judging circuit 14 is used to judge whether the virtual address fetched belongs to the same page table or directly mappable space, and the first content comparator circuit 11 is used to fetch The query of instruction virtual address, the second content comparator circuit 12 is used for the query of data access virtual address, the second comparison circuit 13 is used for comparing with the last data access virtual address, and the second judging circuit 15 is used for judging data Whether the memory access virtual address belongs to the same page table or directly mappable space; the first two selection circuit 16 is used to select two indexes generated by the respective content comparators of the instruction translation back buffer and the data translation back buffer after comparison , single-read port random access memory circuit 17, used to keep the random access memory of the physical page table address and related control signals, the instruction translation backup buffer and the data translation backup buffer are shared (alternative circuits such as register files can also be selected), the first register Group 18 is used to store the physical page table address after the last instruction fetch address conversion, the second register group 19 is used to store the physical page table address after the last data access conversion, and the third comparison circuit 20 uses the physical page table At the address, such as the tag comparison circuit of the instruction cache, it is used to compare the tag value of the instruction cache with the content in the first register group, and output a 1-bit result signal. The fourth comparison circuit 21 uses the address of the physical page table, such as The tag comparison circuit of the instruction cache is used to compare the tag value of the instruction cache with the content of the physical page table address output by the random access memory, and outputs a 1-bit result signal. The fifth comparison circuit 22 uses the physical page table address, such as data The tag comparison circuit of the cache is used to compare the tag value of the data cache with the content of the physical page table address output by the random access memory, and output a 1-bit result signal. The sixth comparison circuit 23 is used at the address of the physical page table, such as the data high speed The tag comparison circuit of the cache is used to compare the tag value of the data cache with the content in the second register group, and output a 1-bit result signal, and the second two-selection circuit 24 is used to select the two outputs output by the instruction translation back-up buffer simultaneously. The two results obtained from two physical address sources, the third two-one selection circuit 25 is used to select the two results obtained by using the two physical address sources output by the data translation lookaside buffer at the same time.

Taking instruction fetch as an example, when an instruction fetch address requests access to the instruction translation back buffer, the virtual address is first compared with the content comparator that holds the address entry of the virtual page table, and at the same time compared with the last time the translation back buffer in history Compare the transformed virtual address and determine whether the virtual address belongs to the direct-mapped address space. If the virtual address transformed this time belongs to the same virtual page table as the virtual address transformed last time, or the virtual address transformed this time belongs to the direct-mapped address space , an enable control signal is generated, and this conversion is not allowed to access the RAM of the translation lookaside buffer; otherwise, if this conversion does not belong to the same virtual page table as the last conversion, and the address of this conversion does not belong to the direct mapping space , then use the index obtained by the query content comparator to access the RAM of the translation lookaside buffer to obtain the corresponding physical page table address. The translation lookaside buffer has only one single-port random access memory for maintaining the physical page table address and related control signals. Of course, storage methods such as register files can also be selected. If the instruction translation lookaside buffer and the data translation lookaside buffer need to be accessed at the same time In the case of this random access memory, access conflicts will occur. At this time, address translation access for fetching/or data access can be prioritized according to the impact on performance.

The instruction translation lookaside buffer and the data translation lookaside buffer share the same random access memory, which requires that the contents stored in the instruction translation lookaside buffer and the data translation lookaside buffer are exactly the same, or one of them contains a page table address mapping item that is another A subset of the page table address mapping entries included. At the same time, due to the shared single-port random access memory, it is also required that the instruction translation back buffer and the data translation back buffer each have a set of registers to maintain the last conversion in their respective history. Physical page table address content, if this address transformation uses the last transformed physical page table address and does not access the random access memory, choose to use the physical page table address content held in the register, otherwise, if the random access memory is accessed, then Use the physical page table address of RAM output. But it should be noted that instead of directly selecting to use, the selection will be postponed. For example, in the cache, the physical page table address will be compared with the tag part of the cache, so as to determine whether the cache hits, then in the implementation of the present invention Let the physical page table address of the two sources mentioned above be compared with the tag of the cache at the same time, and get the result of whether the two bits indicate whether it is a hit, and then choose which one to use according to whether the RAM is accessed in the translation lookaside buffer. a result. All the circuits used in this device can be obtained from standard cell libraries publicly provided by various chip foundries (such as "SMIC" and "TSMC").

From the above, it can be seen that the advantage of the present invention is that the power consumption and the area of the translation look-aside buffer are effectively reduced, and at the same time, the influence on the performance of the processor and the delay of the actual circuit is avoided. The method used in the present invention can obviously reduce the amount of visits to the random access memory of the instruction translation backup buffer and the data translation backup buffer, thereby greatly reducing the conflicts of the instruction translation backup buffer and the data translation backup buffer accessing the random access memory at the same time. The performance of the processor will not be affected if the instruction translation back buffer and the data translation back buffer share a single-port random access memory, and at the same time, the power consumption and area of the translation back buffer are reduced. In addition, the special design of the selection circuit introduced thereby avoids adding delays to the circuit.

Finally, it should be noted that: the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be modified or Any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.

Claims (10)

1, an improved virtual address translation method, is characterized in that, comprises the following steps: a) The instruction translation backup buffer and the data translation backup buffer compare the virtual address of this fetch/data with the virtual address/data virtual address of the last fetch; b) Determine whether they belong to the same page table or directly mappable space? If yes, perform step g), if not, perform the next step; c) The instruction translation back buffer and the data translation back buffer share a single-read port random access memory, and accept queries to physical addresses; d) The instruction translation back buffer and the data translation back buffer save the transformed physical address in the register, and respectively postpone the selection with the physical page table address output by the random access memory; e) When the instruction translation back buffer and/or the data translation back buffer are used, the physical addresses of the two sources (this transformation and the last transformation) are used respectively to generate two target signals respectively; f) respectively select the two target signals generated in step e), and output the required result signal; g) Do not access the random access memory, use the saved last changed address, and execute step e). 2. The improved virtual address conversion method as claimed in claim 1, characterized in that, in said steps a), b) and g), there are the following two situations, when the virtual address is converted to the physical address, the translation is not accessed The random memory of the backup buffer, one is to compare the address that needs to be transformed caused by each instruction fetch operation with the address that has been transformed caused by the last instruction fetch operation, if the same address as the previous address falls on the same virtual page In the table entry, the random memory is no longer accessed, but the physical page table address result obtained by the previous conversion is directly used. The address conversion caused by data access also uses the same process as the address conversion caused by fetching. Another case Yes, for the conversion of virtual addresses to physical addresses caused by instruction fetching and data access operations, if the address space where the virtual address is located is a direct mapping space, it can be completed without looking up the mapping relationship table entry of the translation lookaside buffer Mapped without accessing the RAM of the translation lookaside buffer. 3. The improved virtual address translation method according to claim 1, wherein, in said steps d) and e), if the next address translation is performed, the virtual address is on the same page as the virtual address for this secondary translation In the table, the physical address saved in the register is used, otherwise, the random memory of the translation look-aside buffer is queried, and the physical page table address output by the random memory is used. 4. An improved device for virtual address conversion, including a content comparator circuit for storing and comparing virtual page table addresses and a random access memory circuit for storing physical page table addresses, characterized in that instruction fetching and data accessing have their own The content comparator circuit, that is, the first content comparator circuit and the second content comparator circuit, and the first two alternative circuit for selecting the index of the comparison output of the two content comparator circuits, and fetching instructions and data Memory access shares a random access memory circuit with only one read port, and also includes comparison between the virtual address of this fetch transformation and the virtual address of the previous fetch transformation to determine whether the fetch virtual address belongs to the same page table or can be directly mapped The first comparison circuit and the first judgment circuit of the space, the second comparison circuit and the second judgment circuit between the virtual address of this data access transformation and the virtual address of the last data access transformation, save the last transformation of the index fetch The first register group of the physical page table address obtained after and the second register group of the physical page table address obtained after the last conversion for storing data access, and the first register group outputs a 1-bit result signal through the third comparison circuit and the physical page table address output by the random access memory circuit through the fourth comparison circuit to output a 1-bit result signal, and the second register group outputs a 1-bit result signal and the random access memory through the sixth comparison circuit The physical page table address output by the circuit passes through the third two-to-one circuit between the output 1-bit result signal of the fifth comparison circuit, and outputs the desired result signal through the second two-to-one circuit and the third two-to-one circuit . 5. The improved virtual address translation device according to claim 4, characterized in that the third comparison circuit is a tag comparison circuit of the instruction cache, and is used to compare the tag value of the instruction cache with the first The content in the register group outputs a 1-bit result signal; the fourth comparison circuit is a tag comparison circuit of the instruction cache, which is used to compare the tag value of the instruction cache with the content of the physical page table address output by the random access memory, and outputs 1 bit result signal; the fifth comparison circuit is a tag comparison circuit of the data cache, which is used to compare the tag value of the data cache with the content of the physical page table address output by the random access memory, and outputs a 1-bit result signal; the sixth The comparison circuit is a tag comparison circuit of the data cache, used for comparing the tag value of the data cache with the content in the second register group, and outputting a 1-bit result signal. 6. The device for improved virtual address translation according to claim 4, characterized in that, said single-read port random access memory circuit is used to keep physical page table addresses and related control signals in random access memory, and an instruction translation back-up buffer The single-read port random access memory circuit is shared with the data translation look-aside buffer, and the single-read port random access memory circuit preferentially handles address conversion access of instruction fetching and/or data accessing. 7. The improved virtual address translation device according to claim 6, characterized in that the single-read port RAM circuit can be replaced by a single-read port register file circuit. 8. A device for converting from a virtual address to a physical address according to claim 4, wherein the first comparing circuit and the first judging circuit are used to generate an enable signal for accessing random access memory, if the preceding and following The address of the virtual address translation of the two instruction fetches is not in the same page table, and the address of the virtual address translation of the instruction fetch this time does not belong to the directly mappable space, and the RAM is accessed. 9. The improved virtual address conversion device according to claim 4, characterized in that the second comparison circuit and the second judgment circuit are used to generate an enable signal for accessing random access memory, if two data accesses before and after The address transformed by the memory virtual address is not in the same page table, and the address transformed by the virtual address transformation of this data access does not belong to the space that can be directly mapped, and the RAM is accessed. 10. The improved virtual address conversion device according to claim 4, characterized in that, after the instruction look-aside buffer accesses the random access memory, the second two-selection circuit uses the 1-bit output result of the fourth comparison circuit, Otherwise select the 1-bit output result of the third comparison circuit; after the data back-up buffer accesses the random access memory, the third two-selection circuit uses the 1-bit output result of the fifth comparison circuit, otherwise selects the 1-bit output result of the sixth comparison circuit Output the result.

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