CN1773601B - Display device and driving method thereof - Google Patents

Abstract

The present invention provides a display device including: a pixel including a first sub-pixel and a second sub-pixel; a first signal line connected to the first subpixel and transmitting a first signal; a second signal line connected to the second subpixel and transmitting a second signal; a third signal line crossing the first and second signal lines, connected to at least one of the first and second sub-pixels, and transmitting a third signal; and a fourth signal line crossing the first and second signal lines for transmitting the fourth signal line, wherein the first sub-pixel and the second sub-pixel are supplied with data voltages having different magnitudes, and the data voltages applied to the first and second sub-pixels are generated from a single image information.

Description

Display device and driving method thereof

technical field

The present invention relates to a display device and a driving method thereof, in particular, to a liquid crystal display.

Background technique

Generally, a liquid crystal display (LCD) includes a pair of panels having a pixel electrode and a common electrode, and a liquid crystal (LC) layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs). The pixel electrodes are supplied with data voltages row by row through the TFTs. The common electrode is formed on the entire surface of the panel, and is supplied with a common voltage. The pixel electrode and the common electrode and the LC layer interposed therebetween form an LC capacitor from a circuit point of view, and the LC capacitor and the switching element are basic elements forming a pixel.

The LCD generates an electric field in the LC layer by applying a voltage to the electrodes, and a desired image is obtained by controlling the strength of the electric field to change the transmittance of light incident on the LC layer.

Among LCDs, vertical alignment (VA) mode LCDs, which align LC molecules so that their longitudinal axes are perpendicular to the panel in the absence of an electric field, are favored due to their high contrast ratio and wide reference viewing angle. High profile.

The wide viewing angle of the VA mode LCD can be realized by the cutout of the field generating electrode and the protrusion of the field generating electrode. Since the cutouts and protrusions can determine the inclination direction of LC molecules, by using the cutouts and protrusions, the inclination directions can be distributed in several directions, thereby expanding the viewing angle.

However, VA mode LCDs have poor side visibility compared to front visibility. For example, a lateral gamma curve is different from a frontal gamma curve.

To improve side visibility, the pixel is divided into two sub-pixels that can be connected to each other. One of the sub-pixels is directly supplied with a voltage, while the other sub-pixel experiences a voltage drop through a capacitive connection, so that the two sub-pixels have different voltages to cause different transmittances.

However, conventional methods cannot control the transmittance of two sub-pixels. In particular, since the transmittance changes depending on the color of light, it is preferable that the voltages be different for different colors, which in turn is not possible. Furthermore, the aperture ratio is reduced due to the additional conductor for the capacitive connection, and the transmittance is reduced due to the voltage drop due to the capacitive connection.

Meanwhile, the polarity of the data voltage with respect to the common voltage is inverted every frame, every predetermined number of rows or columns, or every pixel for avoiding defects includes defect. In the data voltage inversion scheme, column inversion, which inverts the polarity of the data line every predetermined number of pixel columns, will maintain the polarity of the data voltage applied to the data line for a predetermined time to reduce the data signal delay in the line and reduce power loss.

However, column inversion can cause vertical flicker and vertical disturbance, thereby degrading the image quality of the LCD.

Contents of the invention

The main purpose of the present invention is to avoid the above defects in the prior art, and provide a display device and a driving method thereof.

A display device according to an embodiment of the present invention includes: a pixel including a first sub-pixel and a second sub-pixel; a first signal line connected to the first sub-pixel and transmitting a first signal; a second signal line connected to the first sub-pixel the second sub-pixel and transmit the second signal; the third signal line crosses the first and second signal lines and is connected to at least one of the first and second sub-pixels, and transmits the third signal; and a fourth signal line crossing the first and second signal lines and transmitting a fourth signal, wherein the first subpixel and the second subpixel are supplied with data voltages having different magnitudes, And the data voltages supplied to the first and second sub-pixels are generated from a single image information.

The first sub-pixel includes a first switching element connected to the first signal line, and a first liquid crystal capacitor connected to the first switching element, and the second sub-pixel includes a first switching element connected to the second signal line The second switching element on the upper, and the second liquid crystal capacitor connected to the second switching element.

The first liquid crystal capacitor includes a first subpixel electrode connected to the first switching element, and the second liquid crystal capacitor includes a second subpixel electrode connected to the second switching element.

The first and second subpixel electrodes are spaced apart from each other such that there is a gap at an oblique angle to the first to fourth signal lines.

At least one of the first and second sub-pixels has a cutout so as to form an oblique angle with the first to fourth signal lines.

The first and second sub-pixels further include a common electrode having a cutout portion making an oblique angle to the first to fourth signal lines.

The first switching element is connected to the first and third signal lines, and the second switching element is connected to the second and third signal lines.

The first switch element is turned on according to the first signal and transmits the third signal, and the second switch element is turned on according to the second signal and transmits the third signal.

The first switch element is turned on according to the third signal and transmits the first signal, and the second switch element is turned on according to the third signal and transmits the second signal.

A first subpixel is connected to the first and third signal lines, and a second subpixel is connected to the second and fourth signal lines.

The first subpixel also includes a first storage capacitor connected to the first switching element, and the second subpixel further includes a second storage capacitor connected to the second switching element.

First and second grayscale voltage groups different from each other are generated, the first subpixel electrode is supplied with a voltage selected from the first grayscale voltage group, and the second subpixel electrode is supplied with a voltage selected from the second grayscale voltage group. The voltages in the voltage group.

Image information is processed to generate first and second image signals, and the first and second subpixel electrodes are supplied with voltages selected from a single grayscale voltage group corresponding to the first and second image signals.

The first subpixel and the second subpixel are capacitively coupled to each other.

A liquid crystal display according to an embodiment of the present invention includes: a pixel including a first sub-pixel and a second sub-pixel; a gate line connected to the first and second sub-pixels and transmitting a gate signal; a first data line and the gate line intersects, is connected to the first sub-pixel, and transmits a first data voltage; and a second data line intersects the gate line, is connected to the second sub-pixel, and transmits the second data voltage.

The first data voltage is different from the second data voltage, and the first and second data voltages are generated from a single image information.

The polarity of the first data voltage is opposite to that of the second data voltage.

The polarity of the first data voltage is kept constant for a predetermined time.

A display device according to another embodiment of the present invention includes: a plurality of pixels arranged in a matrix, each of which includes a first sub-pixel and a second sub-pixel; a plurality of first gate lines connected to the first sub-pixel a sub-pixel, and transmit a first gate voltage; a plurality of second gate lines, connected to the second sub-pixel, and transmit a second gate voltage; a plurality of data lines, connected to the first and The second gate line is crossed, connected to the first and second sub-pixels, and transmits the data voltage; the grayscale signal generation circuit generates the first grayscale signal group and the second grayscale signal group; the selection circuit alternately selects and outputting first and second signal groups; a data driver generating data voltages corresponding to image data based on the first and second grayscale signal groups, and supplying the data voltages to the data lines; and a gate A driver sequentially supplies the first and second gate-on voltages to the first and second gate lines.

The grayscale signal includes an analog grayscale voltage.

The selection circuit includes an analog switch, or an analog multiplexer. The selection circuit is integrated into the data driver. The grayscale signal generating circuit includes a plurality of analog voltage generating circuits, each of which includes a series of resistors.

The grayscale signal includes digital grayscale data.

The display device further includes a digital-to-analog voltage converter converting digital grayscale data in the grayscale signal group selected by the selection circuit to generate a plurality of grayscale voltages.

The selection circuit includes a plurality of multiplexers connected to the grayscale signal generation circuit.

The application of the first gate-on voltage and the application of the second gate-on voltage at least partially overlap each other.

The duration of the first gate-on voltage is equal to or less than the duration of the second gate-on voltage.

A liquid crystal display according to another embodiment of the present invention includes: a plurality of pixels arranged in a matrix, each of which includes a first sub-pixel and a second sub-pixel; a plurality of first gate lines connected to the first sub-pixel a sub-pixel, and transmit a first gate voltage; a plurality of second gate lines, connected to the second sub-pixel, and transmit a second gate voltage; a plurality of data lines, connected to the first and The second gate line is crossed, connected to the first and second sub-pixels, and transmits the data voltage; the reference voltage generation circuit generates a plurality of reference voltages whose magnitudes change periodically; the grayscale voltage generation circuit is based on the reference a plurality of grayscale voltages; a data driver selects a data voltage corresponding to image data from the grayscale voltages, and applies the data voltages to the data lines; and a gate driver sequentially applies the first First and second gate pass voltages are applied to the first and second gate lines.

A liquid crystal display according to still another embodiment of the present invention includes: first and second gate lines extending substantially parallel to each other and separated from each other; data lines crossing the first and second gate lines; A thin film transistor connected to the first gate line and the second data line; a second thin film transistor connected to the second gate line and the second data line; a first display electrode connected to the the first thin film transistor; and a second display electrode connected to the second thin film transistor, wherein the first and second display electrodes have oblique sides facing each other.

A liquid crystal display according to still another embodiment of the present invention includes: first and second gate lines extending in a first direction and separated from each other; data lines crossing the first and second gate lines; first a thin film transistor connected to the first gate line and the second data line; a second thin film transistor connected to the second gate line and the second data line; a first display electrode connected to the the first thin film transistor; and a second display electrode connected to the second thin film transistor, wherein the first display electrode is longer than the second display electrode in the second direction, and the first display electrode is set within the length of the second display electrode in the second direction.

A liquid crystal display according to another embodiment of the present invention, comprising: first and second gate lines extending in a first direction and separated from each other; data lines crossing the first and second gate lines; a first thin film a transistor connected to the first gate line and the second data line; a second thin film transistor connected to the second gate line and the second data line; a first display electrode connected to the a first thin film transistor; and a second display electrode connected to the second thin film transistor, wherein each of the first and second display electrodes is substantially symmetrical with respect to a straight line extending in the first direction.

The liquid crystal display further includes a third display electrode facing the first and second display electrodes.

At least one of the first and second display electrodes has a cutout.

The third display electrode has a cutout or a protrusion.

At least one of the first and second display electrodes and the third display electrode have cutouts arranged alternately.

The gaps between the first and second display electrodes and the cutouts of the third display electrodes are arranged alternately.

The liquid crystal display further includes storage electrode lines overlapping the first and second display electrodes.

Each of the first and second thin film transistors has a gate electrode connected to the first or second gate line, a source electrode connected to the data line, and a source electrode connected to the first or second The second display electrode is the drain electrode.

The voltage of the first display electrode is different from the voltage of the second display electrode.

The voltage of the first display electrode subtracted by a predetermined voltage is smaller than the voltage of the second display electrode subtracted by the predetermined voltage.

The liquid crystal display further includes a guard electrode overlapping with the data line and provided as the first and second display pixel electrodes.

A thin film transistor array panel according to an embodiment of the present invention, comprising: a gate line formed on the substrate; first and second data lines insulated from the gate line and crossing the gate line; a first thin film a transistor connected to the gate line and the first drain electrode and including a first drain electrode; a second thin film transistor connected to the gate line and the second drain electrode and including a second drain electrode; layer, formed on the gate line, the first and second data lines, and the first and second thin film transistors, and has a first contact hole exposing the first data line and exposing the The second contact hole of the second data line; and the pixel electrode, including the first sub-pixel electrode connected to the first drain electrode through the first contact hole, and connected to the first drain electrode through the second contact hole. The second sub-pixel electrode on the second drain electrode.

The thin film transistor array panel further includes a guard electrode insulated from the first and second sub-pixel electrodes and overlapping with at least one of the gate line and the first and second data lines.

The pixel electrode and the guard electrode are disposed on the passivation layer.

The TFT array panel further includes a storage electrode line including a storage electrode overlapping with the first and second drain electrodes to form a storage capacitor.

The guard electrode and the storage electrode are supplied with a single voltage.

The guard electrode completely covers the first and second data lines.

The area of the first sub-pixel electrode is different from the area of the second sub-pixel electrode.

According to the method for driving a liquid crystal display according to an embodiment of the present invention, wherein the liquid crystal display includes a plurality of pixels, and each pixel includes a plurality of sub-pixels, the method includes: receiving input image data; converting the image data into at least two data voltage; and applying at least two data voltages to the subpixels.

The conversion includes: generating at least two groups of gray voltages; and selecting gray voltages corresponding to the input image data from the at least two groups of gray voltages to generate data voltages.

The converting includes: converting the input image data into at least two output image data; and selecting gray voltages corresponding to the at least two output image data from the set of gray voltages to generate data voltages.

According to the method for driving a liquid crystal display in an embodiment of the present invention, the liquid crystal display includes a plurality of pixels arranged in a matrix, each of which includes first and second sub-pixels, and the method includes: applying a first data voltage to the first subpixel; and applying a second data voltage having a second polarity opposite to the first polarity to the second subpixel.

The first and second data voltages are generated from a single image data.

The first sub-pixels of adjacent pixels in a row have opposite polarities, and the second sub-pixels of adjacent pixels in a row have opposite polarities.

The first subpixels of adjacent pixels in a column have the same polarity, and the second subpixels of adjacent pixels in a column have the same polarity.

Each data voltage is supplied to at least two sub-pixels simultaneously.

A method for driving a liquid crystal display, the liquid crystal display comprising a plurality of pixels, each of the pixels comprising a first sub-pixel and a second sub-pixel, the method comprising: transmitting image data; outputting a first group of grayscale voltages; converting the image data into a first data voltage selected from the first set of grayscale voltages; applying the first data voltage to the first sub-pixel; using a second set of grayscale voltages by using a multiplexer outputting the second set of grayscale voltages different in magnitude from the first set of grayscale voltages instead of the first set of grayscale voltages; converting the image data into a second set of grayscale voltages selected from the second set of grayscale voltages a data voltage; and applying the second data voltage to the second sub-pixel.

The method further includes: generating first and second groups of gray-scale voltages; wherein the output of the first group of gray-scale voltages includes: selecting the first group of gray-scale voltages by using a multiplexer, and wherein the second group of gray-scale voltages The outputting of the grayscale voltages includes: selecting the second group of grayscale voltages by using a multiplexer.

The method further includes: storing first and second sets of digital grayscale data; wherein the output of the first set of grayscale voltages includes: selecting the first set of digital grayscale data by using a multiplexer; A set of digital grayscale data is analog-converted into the first set of grayscale voltages, and wherein the output of the second set of grayscale voltages includes: selecting the second set of digital grayscale data by using a multiplexer; and converting the first set of grayscale voltages The two sets of digital grayscale data are analog-converted into the second set of grayscale voltages.

Description of drawings

The present invention will become apparent through the following detailed description of the embodiments of the present invention in conjunction with the accompanying drawings, wherein:

1 is a block diagram of an LCD according to an embodiment of the present invention;

2 is an equivalent circuit diagram of a pixel of an LCD according to an embodiment of the present invention;

3A, 3B, and 3C are block diagrams of LCDs according to embodiments of the present invention;

4A and 4B are equivalent circuit diagrams of pixels of an LCD according to an embodiment of the present invention;

5A, 5B, and 5C show an example of a grayscale voltage generator and a data driver of an LCD as shown in FIGS. 3A-4B;

6 is a block diagram of a reference voltage changing circuit and a voltage generating resistor string according to an embodiment of the present invention;

7A is a gamma graph of an LCD according to an embodiment of the present invention;

FIG. 7B is a graph showing grayscale voltage as a function of input grayscale of an LCD according to an embodiment of the present invention;

8A, 8B, and 8C show signal waveforms of LCDs according to embodiments of the present invention;

9 is a block diagram of an LCD according to another embodiment of the present invention;

10 is a block diagram of a grayscale voltage generator according to an embodiment of the present invention;

11 is a block diagram of a grayscale voltage generator according to another embodiment of the present invention;

Fig. 12 shows waveforms of various signals of the LCD shown in Figs. 9-11;

13 is a block diagram of an LCD according to another embodiment of the present invention;

Figure 14 shows the waveforms of various signals in the LCD shown in Figure 13;

15 is a block diagram of an LCD according to another embodiment of the present invention;

16 is an equivalent circuit diagram of a pixel of an LCD according to another embodiment of the present invention;

FIG. 17A schematically shows the arrangement of pixels and the polarity of data voltages according to an embodiment of the present invention;

Figure 17B shows the polarity of the subpixels shown in Figure 17A;

Fig. 18 shows the waveforms of various signals of the LCD shown in Fig. 17A;

19 is a schematic layout diagram of a lower panel (TFT array panel) according to an embodiment of the present invention;

20 is a schematic layout diagram of an upper panel (common electrode panel) according to an embodiment of the present invention;

21 is a schematic layout diagram of an LC panel assembly including the TFT array panel shown in FIG. 19 and the common electrode panel shown in FIG. 20;

Figures 22 and 23 are cross-sectional views taken along XXII-XXII and XXIII-XXIII of the LC panel assembly shown in Figure 21, respectively;

24 is a schematic layout diagram of a TFT array panel according to another embodiment of the present invention;

25 is a block diagram of an LCD according to another embodiment of the present invention;

26 is an equivalent circuit diagram of a pixel of an LCD according to another embodiment of the present invention;

27 is a schematic layout diagram of a lower panel (TFT array panel) according to an embodiment of the present invention;

28 is a schematic layout diagram of an upper panel (common electrode panel) according to an embodiment of the present invention;

29 is a schematic layout diagram of an LC panel assembly including the TFT array panel shown in FIG. 27 and the common electrode panel shown in FIG. 28;

30A and 30B are cross-sectional views of the LC panel assembly shown in FIG. 29 taken along lines XXXA-XXXA and XXXB-XXXB;

31 is a schematic layout diagram of a TFT array panel according to another embodiment of the present invention;

Figure 32A is a cross-sectional view taken along the line XXXIIA-XXXIIA of the TFT array panel shown in Figure 31;

Figure 32B is a cross-sectional view taken along the line XXXIIB-XXXIIB of the TFT array panel shown in Figure 31; and

Figure 33 shows the polarity of the pixel electrodes in column inversion according to an embodiment of the present invention.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings, which show preferred embodiments according to the present invention. However, the present invention can be implemented in many different forms and is not limited to the embodiments described here.

In the drawings, the thickness of layers, films and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region, or substrate is "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is "directly on" another element, it means that there are no intervening elements therebetween.

An LCD according to an embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 2 .

FIG. 1 is a block diagram of an LCD according to an embodiment of the present invention; FIG. 2 is an equivalent circuit diagram of a pixel of the LCD according to an embodiment of the present invention.

Referring to FIG. 1, an LCD according to an embodiment of the present invention includes an LC panel assembly 300, a gate driver 400 and a data driver 500 connected to the panel assembly 300, a grayscale voltage generator 800 connected to the data driver 500, and a control panel assembly 300. Signal controller 600 for each component.

Referring to FIG. 1, the panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected thereto and substantially arranged in a matrix. In the specific structure shown in FIG. 2, the panel assembly 300 includes a lower panel 100, an upper panel 200, and an LC layer 3 interposed therebetween.

The signal lines include a plurality of gate lines (not shown) transmitting gate signals (also referred to as “scanning signals”), and a plurality of data lines (not shown) transmitting data signals. The gate lines extend substantially in a row direction and are substantially parallel to each other, while the data lines extend substantially in a column direction and are substantially parallel to each other.

Referring to FIG. 2, each pixel PX includes a pair of sub-pixels PXa and PXb. Each sub-pixel PXa/PXb includes a liquid crystal (LC) capacitor Clca/Clcb and a switching element Qa/Qb connected to a gate line, a data line, and the LC capacitor Clca/Clcb.

Switching elements Qa/Qb including thin film transistors (TFTs) are provided on the lower panel 100, and have three terminals: a control terminal connected to a gate line, an input terminal connected to a data line, and an LC capacitor Clca/Qb connected to a data line. Output terminal on Clcb.

The LC capacitor Clca/Clcb includes the sub-pixel electrodes PEa/PEb and the common electrode CE disposed on the upper panel 200 as two terminals. The LC layer 3 is provided between the electrodes PEa/PEb and CE, and functions as a dielectric of the LC capacitor Clca/Clcb. A pair of subpixel electrodes PEa and PEb are isolated from each other and form a pixel electrode PE. The common electrode CE is supplied with a common voltage Vcom and covers the entire surface of the upper panel 200 . In another embodiment, the common electrode CE may also be disposed on the lower panel 100, and at least one of the electrodes PE and CE may have a rod or a strip shape.

To display color, each pixel PX represents one of the primary colors individually (i.e., space-separated), or each pixel PX sequentially represents the primaries (i.e., time-separated), so that the spatial or temporal sum of the primary colors is identified for the desired color. An example set of primary colors includes red, green, and blue. FIG. 2 shows an example of spatial separation in which each pixel PX includes a color filter CF representing one of the primary colors in a region of the upper panel 200 facing the pixel electrode 190 . Alternatively, the color filter CF is disposed on or under the sub-pixel electrode PEa or PEb on the lower panel 100 .

One or more polarizers (not shown) are attached to at least one of the panels 100 and 200 .

Referring again to FIG. 1 , the gray voltage generator 800 generates a plurality of gray voltages related to the transmission of the pixel PX. However, the gray voltage generator 800 may also generate only a given number of gray voltages (also referred to as reference gray voltages) instead of all the gray voltages.

The gate driver 400 is connected to the gate lines of the panel assembly 300 and synthesized with a gate-on voltage Von and a gate-off voltage Voff from an external device to generate a gate signal Vg for the gate lines.

The data driver 500 is connected to the data lines of the panel assembly 300 and supplies a data voltage Vd selected from gray voltages supplied by the gray voltage generator 800 to the data lines. However, when the gray-scale voltage generator 800 generates the reference gray-scale voltage, the data driver 500 can also generate gray-scales for all gray-scales by distinguishing the reference gray-scale voltage and the selected data voltage Vd from the generated gray-scale voltages. Voltage.

The signal controller controls the gate driver 400 and data driving and the like.

In a tape carrier package (TCP) type, each drive unit 400, 500, 600, 700, and 800 may include at least one integrated circuit (IC) chip mounted on an LC panel assembly 300 or a flexible printed circuit (FPC), connected to to the panel assembly 300. Optionally, at least one processing unit 400, 500, 600, 700, and 800 can be integrated with signal lines and switching elements Qa and Qb on the panel assembly 300. Optionally, all processing units 400 , 500, 600, 700, and 800 may be integrated on a single IC chip, but at least one of the processing units 400, 500, 600, 700, and 800 or at least one of the processing units 400, 500, 600, 700, and 800 At least one circuit element may be provided outside of a single IC chip.

An LCD according to an embodiment of the present invention will now be described in detail with reference to FIGS. 3A, 3B, 3C, 4A, and 4B.

3A, 3B, and 3C are block diagrams of an LCD according to an embodiment of the present invention; FIGS. 4A and 4B are equivalent circuit diagrams of pixels of an LCD according to an embodiment of the present invention.

3A-3C, an LCD according to an embodiment of the present invention includes an LC panel assembly 300, a (pair of) gate drivers 400a, 400b, 410, 420, a data driver 500, a grayscale voltage generator 800, and a signal controller 600.

The panel assembly 300 includes a plurality of signal lines and a plurality of pixels PX connected thereto and arranged substantially in a matrix.

The signal lines are disposed on the lower panel 100 (refer to FIG. 2 ), and include a plurality of pairs of gate lines and a plurality of data lines.

4A and 4B show equivalent circuit diagrams of signal lines and pixels PX. The display signal lines include an upper gate line GLa, a lower gate line GLb, a data line DL, and a storage electrode line SL extending substantially parallel to the gate lines GLa and GLb.

Each pixel PX shown in FIG. 4A includes a pair of sub-pixels Pxa and PXb, and each sub-pixel PXa/PXb includes a switching element Qa/Qb connected to at least one of the gate line GLa/GLb and the data line DL, and connected to A liquid crystal (LC) capacitor Clca/Clcb on the switching element Qa/Qb, and a storage capacitor Csta/Cstb connected between the switching element Qa/Qb and the storage electrode line SL. The storage capacitors Csta and Cstb can be omitted as necessary, and in this case, the storage electrode line SL can also be omitted.

Each pixel PX shown in FIG. 4B includes a pair of subpixels Pxa, PXb, and a coupling capacitor Ccp connected between the subpixels Pxa and PXb. Each subpixel PXa/PXb includes a switching element Qa/Qb connected to at least one of the gate lines GLa and GLb and the data line DL, and a liquid crystal (LC) capacitor Clca/Clcb connected to the switching element Qa/Qb. One subpixel Pxa includes a storage capacitor Csta connected between the switching element Qa and the storage electrode line SL.

The storage capacitors Csta/Cstb are auxiliary capacitors for the LC capacitors Clca/Clcb. The storage capacitor Csta/Cstb including the subpixel electrode PEa/PEb and a separate signal line is disposed on the lower panel 100, overlaps the subpixel electrode PEa/PEb through an insulator, and is supplied with a predetermined voltage such as a supply voltage Vcom. Alternatively, the storage capacitor Csta/Cstb includes the sub-pixel electrode PEa/PEb and an adjacent gate line called a front gate line, the insulator of which overlaps the sub-pixel electrode PEa/PEb.

3A to 3C again, the gate drivers 400a, 400, 410, 420 are connected to the gate lines Gla-Gnb, and are synthesized with the gate-on voltage Von and the gate-off voltage Voff from an external device to generate a voltage applied to the gate. Gate signal of polar line Gla-Gnb. In FIG. 3A, a pair of gate drivers 400a, 400b are respectively located on the left and right of the panel assembly 300, and are respectively connected to the odd and even gate lines Gla-Gnb. Each gate driver 410, 420 shown in FIG. 3B and FIG. 3C is located on one side of the panel assembly 300 and connected to all gate lines Gla-Gnb. The gate driver 420 shown in FIG. 3C includes two driving circuits 421, 422 to be connected to the odd and even gate lines Gla-Gnb, respectively.

The gray voltage generator 800 generates two sets of (reference) gray voltages related to the transfer of pixels. Two sets of grayscale voltages are individually supplied to the two sub-pixels Pxa, PXb. Each set of gray voltages includes gray voltages with positive polarity with respect to the common voltage Vcom and gray voltages with negative polarity with respect to the common voltage Vcom. However, the grayscale voltage generator 800 can also generate only one set of (reference) grayscale voltages.

An example of the grayscale voltage generator and the data driver in the LCD shown in FIGS. 3A-4B will now be described in detail with reference to FIGS. 5A, 5B, and 5C.

The LCD example shown in FIG. 5A includes a data driver 500, a grayscale voltage generator 800, and an analog switch (SW) 850 as separate elements. The grayscale voltage generator 800 includes two voltage generating resistor strings GStr1, GStr2. Analog The switch 850 is connected between the gray voltage generator 800 and the data driver 500, and selects one of two groups of gray voltages from the gray voltage generator 800 in response to a selection signal SE.

The LCD example shown in FIG. 5B incorporates an analog switch 850 as shown in FIG. 5A to a data driver 500 . Reference numeral 510 denotes a general data driver unit.

The LCD example shown in FIG. 5C includes a reference voltage changing circuit (VCC) 860 instead of the grayscale voltage generator 800 . The reference voltage changing circuit 860 generates a certain number of reference voltages whose magnitudes are changed depending on the selection signal SE. The data driver 500 includes a voltage generating resistor string (GStr) 560 generating a grayscale voltage, and generates different sets of gamma voltages according to a reference voltage supplied from a reference voltage changing circuit 860 .

FIG. 6 shows an example of the reference voltage changing circuit and the voltage generating resistor string shown in FIG. 5C.

Referring to FIG. 6, the voltage generating resistor string 560 includes a plurality of series connected resistors R201-R211, a central resistor R206, and first and second sets of five resistors connected on both sides of the central resistor R206. A first set of resistors R201-R205 have ends connected to a low voltage and a second set of resistors R207-R211 have ends connected to a supply voltage AVDD.

The reference voltage changing circuit 860 includes NPN and PNP bipolar transistors Q1 , Q2 , Q3 , a pair of resistor R1 and diode D1 , and another pair of resistor R2 and diode D2 . NPN and PNP bipolar transistors Q1, Q2, Q3 are connected between central resistor R206, first set of resistors R201-R205, and second set of resistors R207-R211. The pair of resistors and diodes R1, D1 and R2, D2 are connected between transistors Q1, Q2, Q3. PNP transistor Q4 is connected between a high voltage input terminal supplying supply voltage (power supply voltage) AVDD and transistor Q3, and transistor Q4 has a base supplied with low voltage through resistors R5, R7, and is connected to transistor Q3 through diode D3. NPN transistor Q2 is connected to the select signal SE input terminal through resistor R3, and PNP transistor Q3 is connected to the high voltage input terminal through resistors R4, R6. Capacitor C2 is connected between the bases of transistors Q1, Q3, capacitor C1 is connected between transistors Q2 and Q4 through resistors R3, R5, and capacitor C3 is connected between resistors R4, R6.

In the reference voltage changing circuit 860, the transistor Q3 is always on to transmit the supply voltage AVDD. If the select signal SE is low, transistor Q4 is turned off to disconnect the high voltage, and transistor Q2 is turned on to form a path to the low voltage. Therefore, a low voltage is supplied to the contacts N1 and N2.

Conversely, if the select signal SE is high, the transistor Q2 is turned off to cut off the connection to the low voltage, and the transistor Q4 is turned on to form a path to the high voltage. Therefore, a high voltage determined by the resistors R1, R6, etc. is supplied to the contacts N1, N2.

The operation of the above-mentioned LCD will be described in detail below.

The signal controller 600 is supplied with input image signals R, G, B and input control signals for controlling display thereof from an external graphics controller (not shown). The input image signals R, G, B contain brightness information of each pixel PX, and the brightness has a predetermined value, for example, has 1024 (=2 ¹⁰ ), 256 (=2 ⁸ ), or 64 (=2 ⁶ ) gray levels . The input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock MCLK, and a data enable signal DE.

Based on the input control signal and the input image signal R, G, B, after generating the gate control signal CONT1 and the data control signal CONT2 and processing the image signal R, G, B suitable for the operation of the panel assembly 300, the signal controller 600 will The gate control signal CONT1 is transmitted to the gate drivers 400 a , 400 b , 410 , 420 , and the processed image signal DAT and data control signal CONT2 are transmitted to the data driver 500 . The processing of the image signals R, G, B includes rearranging the image data R, G, B according to the pixel arrangement of the panel assembly 300 shown in FIG. 3 .

The gate control signal CONT1 includes a scan start signal STV indicating start of scan, and at least one clock signal for controlling the output timing of the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE for defining a duration of the gate-on voltage Von. The clock signal can be used as the selection signal SE shown in FIGS. 5A-5C and FIG. 6 .

The data control signal CONT2 includes a horizontal synchronization start signal STH notifying the start of data transfer to a group of sub-pixels Pxa, PXb, a load signal LOAD instructing to supply data voltages to the data lines D1-Dm, and a data clock signal HCLK. The data control signal CONT2 may include an inversion signal RVS for inverting the polarity of the data voltage (relative to the supply voltage Vcom).

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives image data DAT for one group of sub-pixels Pxa, PXb from the signal controller 600, and receives two groups of grayscales supplied by the grayscale voltage generator 800. A set of voltages. The data driver 500 converts image data DAT selected from gray voltages supplied from the gray voltage generator 800 into analog data voltages, and supplies the data voltages to D1-Dm.

Unlike this, as shown in FIG. 5A , an external selection circuit 850 provided separately instead of the data driver 500 selects and transmits one of two sets of grayscale voltages to the data driver 500 . In another embodiment as shown in FIG. 5C , the grayscale voltage generator 800 provides a reference voltage with varying magnitudes, which is divided by the data driver 500 to form grayscale voltages.

The gate drivers 400a, 400b, 410, 420 apply the gate-on voltage Von to the gate lines Gla-Gnb in response to the gate control signal CONT1 from the signal controller 600, thereby turning on the switching elements Qa, Qa, Qb. The data voltages applied to the data lines D1-Dm are applied to the sub-pixels Pxa, PXb through the turned-on switching elements Qa, Qb.

The difference between the data voltage and the common voltage Vcom is represented as the voltage across the LC capacitors Clca, Clcb, which is also called the pixel voltage. The LC molecules in the LC capacitors Clca, Clcb are oriented according to the magnitude of the pixel voltage, and the orientation of the molecules determines the deflection of light passing through the LC layer 3 . This deflection converts the deflection of light into the transmission of light, whereby the pixel PX displays the luminance represented by the image signal DAT.

As shown in FIG. 7A , the above two groups of gray scale voltages show two different gamma curves Ta, Tb. Since two groups are supplied to the two sub-pixels Pxa, PXb of the pixel PX, the composite curve T of the two gamma curves forms the gamma curve of the pixel PX. Preferably, two sets of grayscale voltages are determined so that the synthesized gamma curve T is close to the reference gamma curve when viewed from the front. For example, the synthetic gamma curve T for frontal viewing coincides with the best-fit reference gamma curve for frontal viewing, and the synthetic gamma curve T for lateral viewing is closest to the frontal reference gamma curve. GS1 and GSf in Fig. 7A mean the lowest input grayscale and the highest input grayscale, respectively. For example, gamma curves on the lower side will be further reduced to improve visibility.

Repeat the above process with 1/2 horizontal period (it is represented by "1/2H", and is equal to the half period of the horizontal synchronous signal Hsync or the data enable signal DE), and all the gate lines G _la -G _nb in one frame The gate-on voltage Von is supplied in sequence, so that the data voltage is applied to all the pixels.

When the next frame starts after the end of one frame, the inversion control signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage is inverted (which is also referred to as 'frame inversion'). It is also possible to control the inversion control signal RVS so that the polarity of the image data signal transmitted in the data line is periodically inverted in a frame (for example, line inversion and dot inversion), or in a package (packet, package) The polarity of the image data signal in is inverted (for example, column inversion and dot inversion).

However, since the gate lines of such LCDs are twice as large as those of ordinary LCDs, the charging time of the above-mentioned LCD may be too short for the pixel PX to reach its target brightness, and the inversion may also reduce the charging time.

The charging time can be increased by applying a gate-on voltage to two adjacent gate lines that partially overlap, which in turn can be achieved by using the gate driver shown in FIGS. 3A and 3B .

Several types of application data voltages are described in detail below with reference to FIGS. 8A, 8B, and 8C.

8A, 8B, and 8C show signal waveforms of an LCD according to an embodiment of the present invention. The reference Vga refers to the gate signal applied to the upper gate line, the reference Vgb refers to the gate signal applied to the lower gate line, and the reference Vd refers to the data voltage carried by the data line.

In the case of dot inversion, since the polarity of the adjacent pixels is reversed, the provision of the data voltage of the adjacent pixels does not significantly improve the charging time either. Therefore, as shown in FIG. 8A , preferably, the charging times for adjacent pixels overlap with each other, and the charging times for adjacent sub-pixels of one pixel overlap with each other. In addition, preferably, the magnitude of a group of grayscale voltages applied to the post-charged sub-pixels is greater than the magnitude of a group of grayscale voltages applied to the first-charged subpixels, as shown in FIG. 8A and FIG. 8B .

In the case of column inversion, since the polarity of two adjacent pixels in the column is the same, the sub-pixel can be pre-charged with the data voltage of the adjacent pixel. Therefore, as shown in Figure 8B, the charging time of all adjacent sub-pixels is between Overlap within a predetermined time.

FIG. 8C shows the case where the gate-on voltage is applied to only one gate line at the same time as the gate driver shown in FIG. 1B .

An LCD according to another embodiment of the present invention will be described in detail below with reference to FIGS. 9 , 10 and 11 .

9 is a block diagram of an LCD according to another embodiment of the present invention; FIG. 10 is a block diagram of a grayscale voltage generator according to an embodiment of the present invention; FIG. 11 is a block diagram of a grayscale voltage generator according to another embodiment of the present invention .

The LCD shown in FIG. 9 has almost the same structure as the LCD shown in FIG. 3B. That is, the LCD includes an LC panel assembly 300 , a gate driver 430 , a data driver 500 , a gray voltage generator 900 , and a signal controller 600 .

The signal controller 600 according to the present embodiment generates and outputs a selection signal SE for controlling the gray voltage generator 900 .

The grayscale voltage generator 900 according to this embodiment either generates two separate sets of analog grayscale voltages, and alternately outputs two sets of grayscale voltages in response to the selection signal SE, or selects one of two sets of digital grayscale data stored by position. and generate a set of analog grayscale voltages based on the selected digital grayscale data. In the latter case, it can be seen that two sets of analog gray-scale voltages corresponding to two sets of digital gray-scale voltages are alternately set. Two sets of grayscale voltages are respectively supplied to two sub-pixels forming a pixel. Each set of gray voltages includes gray voltages having positive and negative polarities with respect to the common voltage Vcom. As described above, the gray voltage generator 900 generates only a given number of reference gray voltages instead of all gray voltages.

The grayscale voltage generator 900 shown in FIG. 10 includes a register unit 910 , a data selection unit 920 , and a conversion unit 930 .

The register unit 910 includes a pair of digital registers 911, 912, which will store different sets of grayscale data γ _1a -γ _Xa , γ _1b -γ _Xb with a one-to-one correspondence.

The data selection unit 920 includes a plurality of multiplexers (MUX) connected to digital registers 911 , 912 . Each multiplexer ₍ MUX) receives a pair of voltages (r _1a r _1b , r _{2a r 2b} , . (r _1a r _1b , r _2a r _2b ,...,r _Xa r _Xb ).

The conversion unit 930 includes a plurality of digital-to-analog converters (DACs), which are respectively connected to multiplexers (MUX). Each digital-to-analog converter (DAC) converts digital data supplied from a multiplexer (MUX) into analog voltages (r ₁ , r ₂ , ..., r _X ) and outputs analog voltages (r ₁ , r ₂ , ..., r _X ).

The grayscale voltage generator 900 shown in FIG. 11 includes a voltage generator 940 and an analog multiplexer AMUX 950.

The voltage generator 940 includes a pair of resistor strings 941 and 942 . Each resistor string 941 and 942 generates one set of gray voltages, and the two sets of gray voltages have different magnitudes.

The analog multiplexer 950 selects and outputs one of the two groups of gray voltages from the voltage generator 940 according to the selection signal SE.

The operation of the LCD shown in FIGS. 9-11 will be described in detail below with reference to FIG. 12 .

FIG. 12 shows waveform diagrams of various signals of the LCD shown in FIGS. 9-11.

As mentioned before, the signal controller 600 processes the image signals R, G, B based on the input control signal and the input image signals R, G, B. FIG. The signal controller 600 generates a gate control signal CONT1, a data control signal CONT2, and a selection signal SE. The signal controller 600 transmits the gate control signal CONT1 to the gate driver 430, transmits the data control signal CONT2 and the processed image signal DAT to the data driver 500, and the signal controller 600 transmits the selection signal SE to the grayscale voltage generator 900.

The gate control signal CONT1 includes a scan start signal STV and at least one clock signal, and may further include an output enable signal OE for defining a duration of the gate-on voltage Von. The data control signal CONT2 includes a horizontal synchronization start signal STH, a load signal LOAD, and a data clock signal HCLK, and may further include an inversion signal RVS for inverting the polarity of the data voltage.

The selection signal SE is an indication signal for selecting one signal from two groups of gray voltages generated by the gray voltage generator 900, and has the same period as the horizontal synchronization start signal STH, the load signal TP, and the like.

The period of the clock signal in the gate control signal CONT1 may be twice that of the horizontal synchronization start signal STH, and in this case, the clock signal may be used as the selection signal SE.

The data driver 500 receives image information di for a group of pixels PX, eg, pixels of an i-th pixel column synchronized with the data clock signal HCLK, in response to a pulse of the horizontal synchronization start signal STH from the signal controller 600 . During receiving image data di, the data driver 500 applies data voltages of previous pixel rows to the data lines D1-Dm. After receiving the image data di, the grayscale voltage generator 900 selects a set of (reference) grayscale voltages determined by the signal SE, and the data driver 500 converts the image information di into an analog data voltage selected from the grayscale voltages, and converts the Data voltages are applied to the data lines D1-Dm.

As described above, the data driver 500 may generate gray voltages divided by reference gray voltages.

The gate driver 400 applies the gate-on voltage Von to the gate lines Gla-Gnb, for example, the i-th pixel row connected to the gate line of the upper sub-pixel PXa in response to the gate control signal CONT1, thereby turning on the gate line connected to the upper sub-pixel PXa. The switching element Qa. The data voltage applied to the data lines D1-Dm is applied to the sub-pixel PXa through the turned-on switching element Qa.

Next, the signal controller 600 changes the value of the selection signal SE to make the gray voltage generator 900 generate and output another set of (reference) gray voltages to the data driver 500 . Then, the data driver 500 reselects the gray voltage corresponding to each image data di from the new gray voltages, and applies it as the data voltage to the corresponding data lines D1-Dm.

The gate driver 430 applies the gate-on voltage Von to the gate lines Gla-Gnb, for example, the gate line connected to the lower sub-pixel PXb in the ith pixel row in response to the gate control signal CONT1, thereby turning on the gate line connected to the lower sub-pixel PXb. The switching element Qb. The data voltage applied to the data lines D1-Dm is applied to the sub-pixel PXb through the turned-on switching element Qb.

An LCD according to another embodiment of the present invention will be described in detail below with reference to FIGS. 13 and 14 .

FIG. 13 is a block diagram of an LCD according to another embodiment of the present invention; FIG. 14 shows waveforms of various signals in the LCD shown in FIG. 13 .

The LCD shown in FIG. 13 has almost the same structure as the LCD shown in FIG. 9. That is, the LCD according to this embodiment includes an LC panel assembly 300, a gate driver 440, a data driver 500, a grayscale voltage generator 900, And signal controller 600.

However, the signal controller 600 according to the present embodiment no longer generates the selection signal SE, and the grayscale voltage generator 800 and the data driver 500 generate a set of (reference) grayscale voltages related to the transmittance of the pixel, and based on the (reference ) grayscale voltage to generate data voltage.

Conversely, the signal controller 600 converts the input image signals R, G, B into a pair of output image signals DATa, DATb. Here, the conversion of the image signal is performed through steps determined by experiments, stored in a look-up table (not shown), and performed through the operation of the signal controller 600 .

The data driver 500 receives the image data of a group of sub-pixels Pxa, PXb, such as the upper sub-pixel Pxa of the i-th pixel row, synchronously in response to the horizontal synchronization start signal STH of the signal controller 600 and the data clock signal HCLK. During receiving the image data dia, the data driver 500 applies the data voltage of the lower sub-pixel PXb of the previous pixel row to the data lines D1-Dm. After receiving the image data dia, according to the pulse of the load signal TP of the signal controller 600, the grayscale voltage generator 900 converts the image data dia into an analog data voltage selected from the grayscale voltage, and applies the data voltage to Data lines D1-Dm.

The gate driver 400 applies the gate-on voltage Von to the gate lines Gla-Gnb, eg, the upper gate line Gia of the i-th pixel row, in response to the gate control signal CONT1, thereby turning on the switching element Qa connected thereto. The data voltage applied to the data lines D1-Dm is applied to the sub-pixel PXa through the turned-on switching element Qa. In FIG. 14 , symbols gia and gib represent gate signals applied to the upper and lower gate lines Gia and Gib of the i-th pixel row, respectively.

In addition, after completing the transmission of the image data dia of the upper sub-pixel Pxa of the i-th pixel row, the signal controller 600 transmits the image data dib of the lower sub-pixel PXb of the i-th pixel row together with a new pulse of the horizontal synchronization signal STH to the data driver 500. Next, the signal controller 600 provides pulses to the load signal TP, so that the data driver 500 reselects the gray voltage corresponding to each image data dib among the gray voltages, and applies the selected gray voltage as the data voltage to the data line D1-Dm.

The gate driver 400 applies the gate-on voltage Von to the next gate line Gla-Gnb, for example, to the lower gate line Gib of the i-th pixel row in response to the gate control signal CONT1, thereby turning on the gate line connected thereto. Switching element Qb. The data voltage applied to the data lines D1-Dm is applied to the sub-pixel PXb through the turned-on switching element Qb.

As described above, the conversion of image data into a pair of output image data will cause a pair of sub-pixels Pxa, PXb to have different transmittances from each other. Therefore, as shown in FIG. 7A , the two sub-pixels Pxa, PXb present different gamma curves Ta, Tb, and the gamma curve of the pixel PX is the curve T synthesized from the gamma curves Ta, Tb.

An LCD according to another embodiment of the present invention will be described in detail below with reference to FIGS. 15, 16, 17A, 17B, and 18. FIG.

Fig. 15 is a block diagram of an LCD according to another embodiment of the present invention; Fig. 16 is an equivalent circuit diagram of a pixel of an LCD according to another embodiment of the present invention; Fig. 17A schematically shows a pixel row according to an embodiment of the present invention 17B shows the polarity of the sub-pixel shown in FIG. 17A; FIG. 18 shows the waveforms of various signals of the LCD shown in FIG. 17A.

The LCD shown in FIGS. 15-18 has almost the same structure as the LCD shown in FIG. 3A. That is, the LCD includes an LC panel assembly 300 , a pair of gate drivers 440 a and 440 b , a data driver 500 , a gray voltage generator 800 , and a signal controller 600 .

As shown in FIG. 15, the LC panel assembly 300 includes multiple pairs of gate lines Gla-Gnb, multiple data lines D0-Dm, and multiple pixels. The number of data lines D0-Dm is greater than that of the LCD shown in FIG. 3A.

As shown in FIGS. 16 and 17A , each pixel PX includes two sub-pixels Pxa and PXb. One PXa (hereinafter referred to as the first sub-pixel) includes a switching element Qa connected to the upper gate line and the left data line, an LC capacitor Clca connected to the switching element Qa, and a storage capacitor Csta connected to the switching element Qa. The subpixel electrode 190a forming the LC capacitor Clca has a triangular shape.

Another subpixel PXb (hereinafter referred to as a second subpixel) includes a switching element Qb connected to the lower gate line and the right data line, an LC capacitor Clcb connected to the switching element Qb, and a storage capacitor connected to the switching element Qb Cstb, the subpixel electrode 190b forming the LC capacitor Clcb is spaced apart from the subpixel electrode 190b of the first subpixel Pxa by a predetermined gap, and the subpixel electrodes 190a and 190b substantially form a rectangle.

The inversion type is column inversion. As shown in FIG. 17A , the column inversion will cause the polarities of the first sub-pixel Pxa and the second sub-pixel PXb to be opposite in each pixel PX. The first sub-pixels Pxa of two pixels PX adjacent in the column direction have the same polarity, and the second sub-pixels PXb of the two pixels PX adjacent in the row direction have opposite polarities.

As shown in FIG. 18 , in order to compensate for the insufficient charging time caused by doubling the number of gate lines, precharging can be performed by overlapping the time of applying gate signals ga, gb to two adjacent gate lines. Referring to the connection relationship shown in FIG. 17A, the first subpixel Pxa is precharged with the data voltage of the second subpixel PXb of the left pixel PX of the upper pixel row, and the second subpixel PXb is precharged with the data voltage of the second subpixel PXb of the right pixel PX. The data voltage of the sub-pixel Pxa is precharged. Compared with dot inversion which inverts the polarity of the data voltage transmitted in the data line, column inversion facilitates precharging. In FIG. 18, notation Vd denotes a data voltage applied to a predetermined data line, notation Vpa denotes a voltage of a first sub-pixel, and notation Vpb denotes a voltage of a second sub-pixel.

When sub-pixels of a pixel are connected to different data lines, and the data driver 500 performs column inversion as described above, consider that the obvious inversion type of sub-pixels is dot inversion. Therefore, LCD has the advantages of both column inversion and dot inversion.

In addition, since each pixel has the same shape, image quality can be increased.

Examples of the LC panel assembly as described above will be described in detail below with reference to FIGS. 19 , 20 , 21 , 22 , 23 , and 24 .

Fig. 19 is a schematic layout diagram of a lower panel (TFT array panel) according to an embodiment of the present invention; Fig. 20 is a schematic layout diagram of an upper panel (common electrode panel) according to an embodiment of the present invention; Fig. 21 is a diagram including the TFT shown in Fig. 19 The layout schematic diagram of the LC panel assembly of the array panel and the common electrode panel shown in FIG. A schematic layout diagram of a TFT array panel according to another embodiment of the present invention.

19-23 show examples of an LC panel assembly for the LCD shown in FIG. 4A, and FIG. 24 is an example of an LC panel assembly for the LCD shown in FIG. 4B. The following description mainly focuses on the panel assembly shown in Figures 19 and 23, while different features of the panel assembly shown in Figure 24 will also be described.

Referring to FIGS. 19-23 , the LC panel assembly according to this embodiment includes a TFT array panel 100 , a common electrode panel 200 facing the TFT array panel 100 , and a liquid crystal layer 3 interposed between the panels 100 and 200 .

First, the TFT array panel 100 will be described in detail with reference to FIG. 19 , FIGS. 21-23 , and FIG. 24 .

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 such as transparent glass or plastic. In FIG. 24 , a plurality of connection electrodes 126 are further formed on the substrate 110 .

The gate lines 121a, 121b transmit gate signals, will extend substantially laterally, and are physically and electrically separated from each other. A pair of first and second gate lines 121a, 121b are located on opposite upper and lower sides, respectively, and include A plurality of gates 124a, 124b protruding from the lower side and the upper side respectively. Each gate line 121a, 121b also includes an end portion 129a, 129b with a larger area to contact another layer or an external driving circuit, And arranged on the left and right sides of the substrate 110. However, the positions of the two ends 129a, 129b can also be the left or right side of the substrate 110. The gate drive circuit (not shown) for generating gate signals can be installed on Flexible printed circuit (FPC) film (not shown), which can be connected to the substrate 110, or directly mounted on the substrate 110, or integrated into the substrate 110. The gate lines 121a and 121b can be extended to connect to the integrated to the drive circuit on the substrate 110.

The storage electrode lines 131 are supplied with a predetermined voltage such as a common voltage Vcom, and each include a branch line extending almost parallel to the gate lines 121a, 121b and a plurality of pairs of first and second storage electrodes 137a, 137b. Each storage electrode line 131 is located between the first gate line 121a and the second gate line 121b, and is closer to the first gate line 121a than the second gate line 121b.

The first storage electrode 137a is longer and narrower than the second storage electrode 137b. However, the storage electrode line 131 shown in FIG. 24 includes only one storage electrode 137 corresponding to the first storage electrode 137a. The storage electrode lines 131 may have various shapes and arrangements.

Capacitive electrode 126 as shown in FIG. 24 is adjacent to storage electrode 137 and extends substantially parallel to storage electrode 137 . The capacitive electrode 126 includes a protrusion protruding downward for contacting another layer.

The gate lines 121 and the storage electrode lines 131 are preferably made of aluminum-containing metals such as aluminum or aluminum alloys, silver-containing metals such as silver or silver alloys, copper-containing metals such as copper or copper alloys, and molybdenum-containing metals such as molybdenum or molybdenum alloys. , chromium, tantalum, and titanium. However, it may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the two thin films is preferably made of low-resistivity metals including Al-containing metals, Ag-containing metals, and Cu-containing metals, and the other thin film is preferably made of Mo-containing metals, Cr, Ta, or Ti, etc. Indium tin (ITO) and indium zinc oxide (IZO) are other materials made of metals with good physical, chemical, and electrical contact properties. Preferable examples of the combination of the two films are a Cr film on the lower layer and an Al (alloy) film on the upper layer, and an Al (alloy) film on the lower layer and a Mo (alloy) film on the upper layer. However, the gate lines 121a and 121b and the storage electrode line 131 may also be made of various other materials and conductors.

Sides of the gate lines 121a and 121b and the storage electrode lines 131 are inclined relative to the surface of the substrate at an inclination angle of about 30° to 80°.

A gate insulating layer 140 made of silicon nitride (SiNx), silicon oxide (SiOx), or the like is formed on the gate lines 121a, 121b and the storage electrode line 131 .

A plurality of semiconductor stripes 151 formed of hydrogenated amorphous silicon (abbreviated as "a-Si"), polysilicon, or the like are formed on the gate insulating layer 140 . Each semiconductor strip 151 extends substantially longitudinally and includes a plurality of first and second protrusions 154a, 154b branching toward the first and second gates 124a, 124b, respectively. The semiconductor strip 151 extends substantially in the longitudinal direction and becomes wider near the gate lines 121 a , 121 b and the storage electrode line 131 , so that the semiconductor strip 151 covers a large area of the gate lines 121 a and 121 b and the storage electrode line 131 .

A plurality of ohmic contact strips and islands 161 , 165 are formed on the semiconductor 151 . The ohmic contact strips and islands 161, 165a are preferably made of n+ hydrogenated a-Si heavily doped with n-type impurities such as phosphorous, or of silicide. Each ohmic contact strip 161 includes a plurality of protrusions 163a, and the protrusions 163a are located on the protrusions 154a of the semiconductor strip 151 in pairs with the ohmic contact islands 165a.

Although not shown in the figure, pairs of protrusions (not shown) of the semiconductor strip 151 and semiconductor islands (not shown) are disposed on the second protrusion 154 b of the semiconductor strip 151 in pairs.

The sides of the semiconductor strip 151 and the ohmic contacts 161, 165a are inclined with respect to the surface of the substrate 110, preferably at an inclination angle of 30° to 80°.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175 a and 175 b are formed on the ohmic contacts 161 and 165 a and the gate insulating layer 140 .

The data lines 171 transmit data signals and extend substantially longitudinally to cross the gate lines 121a and 121b and the storage connections 135a and 135b. Each data line 171 includes a plurality of first and second source electrodes 173a, 173b respectively protruding toward the first and second gate electrodes 124a, 124b, and is bent in a letter C shape. Each data line 171 also includes an end portion 179 with a larger area for contacting another layer or an external driving circuit. A data driving circuit (not shown) for generating data signals is mounted on an FPC film (not shown), which may be connected to the substrate 110 , or directly mounted on the substrate 110 , or integrated on the substrate 110 . The data line 171 can be extended to directly connect with the data driving circuit integrated on the substrate 110 .

The first and second drain electrodes 175a, 175b are separated from the data line 171, and are disposed opposite to the first and second gate electrodes 124a, 124b and opposite to the first and second source electrodes 173a, 173b. Each of the first and second drain electrodes 175a, 175b includes a wide end portion 177a or 177b and a narrow end portion. The wide end portion 177a or 177b overlaps the first and second storage electrodes 137a, 137b, while the narrow end portion is located on the first and second protrusion 154a or 154b and is partially covered by the first or second source electrode 173a and 173b. defend.

However, the second drain electrode 175b shown in FIG. 24 is not relatively short, and the first drain electrode 175a overlaps the storage electrode 137 and the connection electrode 126 .

The gate electrodes 124a/124b, the source electrodes 173a/173b, and the drain electrodes 175a/175b form TFTs Qa and Qb together with the semiconductor islands 154a/154b, which have channels formed on the semiconductor islands 154a/154b provided on Between the source electrode 173a/173b and the drain electrode 175a/175b.

Preferably, the data line 171 and the drain electrodes 175a, 175b are made of refractory metals such as Cr, Mo, Ta, Ti, or alloys thereof, however, it may also have a refractory metal layer (not shown) and low resistance. multilayer structure of the device conductive layer (not shown). Examples of a multilayer structure are a two-layer structure consisting of a lower layer of Cr/Mo (alloy) film and an upper layer of Al (alloy) film, and a three-layer structure consisting of a lower layer of Mo (alloy) film, and the upper Mo (alloy) film. However, the data line 171 and the gate electrodes 175a, 175b may be made of various metals or conductors other than that.

Preferably, the data line 171 and the drain electrodes 175a, 175b have inclined edge profiles, and the inclination angle thereof ranges from 30° to 80°.

The ohmic contacts 162, 163a, and 165a are placed only between the lower semiconductor islands 152, 154a, and 154b and the upper conductors 171, 175a, 175b, and reduce the contact resistivity therebetween. Although in most areas, the semiconductor strip 151 is narrower than the data line 171, as described above, the width of the semiconductor strip 151 close to the gate lines 121a, 121b and the storage electrode line 131 is widened and the surface contour is smoothed, thereby preventing Data line 171 is disconnected. The semiconductor strip 151 includes some exposed portions not covered by the data line 171 and the drain electrodes 175a, 175b, for example, the portion between the source electrode 173 and the drain electrodes 175a, 175b.

A passivation layer 180 is formed on the data line 171 and the drain electrodes 175 a, 175 b and exposed portions of the semiconductor 151 . The passivation layer 180 is preferably made of an inorganic or organic insulator, and has a flat surface. Examples of inorganic insulators include silicon nitride and silicon oxide. Preferably, the organic insulator is photosensitive and has a dielectric constant of about 4.0 or less. But the passivation layer 180 may include a lower thin film of an inorganic insulator and an upper thin film of an organic insulator, so as to have good organic insulating characteristics while preventing the exposed portions of the semiconductor islands 152, 154a, and 154b from being damaged by the organic insulator.

A plurality of contact holes 182, 187a, 187b are formed on the passivation layer 180 to respectively expose the end 179 of the data line 171 and the drain electrodes 175a, 175b, and the passivation layer 180 and the gate insulating layer 140 are formed to expose the gate line 121a. A plurality of contact holes 181a, 181b at the ends 129a, 129b of , 121b. In FIG.

A plurality of pixel electrodes 190 respectively including first and second sub-pixel electrodes 190 a, 190 b, a plurality of shielding electrodes 88 , and a plurality of contact assistants 81 a, 81 b, 82 are formed on the passivation layer 180 . It is preferably made of a transparent conductor such as ITO or IZO or a reflective conductor such as Ag, Al, Cr, and alloys thereof.

The first/second sub-pixel electrode 190a/190b is physically and electrically connected to the first/second drain 175a/175b through the contact hole 185a/185b, thereby receiving the data voltage from the first/second drain 175a/175b . In FIG. 24 , the second subpixel electrode 190 b is connected to the connection electrode 126 through the contact hole 186 , and the first subpixel electrode 190 a overlaps with the connection electrode 126 .

The sub-pixel electrodes 190 a , 190 b supplying the data voltage together with the common electrode 270 supplying the supply voltage form an electric field, which determines the alignment of liquid crystal molecules (not shown) of the liquid crystal layer 3 between the two electrodes 190 , 270 . The sub-pixel electrodes 190a/190b and the common electrode 270 form LC capacitors Clca/Clcb, which maintain the supplied voltage after the TFT is turned off. And in order to enhance the voltage holding capability, the storage capacitors Csta, Cstb are formed by overlapping the first and second sub-pixel electrodes 190a, 190b with the drain electrodes 175a, 175b having the first and second storage electrodes 137a, 137b and so on.

Each pixel electrode 190 is cut at the left corner, and the hypotenuse of the cut corner of the pixel electrode 190 forms an angle of 45 degrees with respect to the gate line 121 .

Each pixel electrode 190 includes a pair of first and second sub-pixel electrodes 190a, 190b spaced apart from each other by a set gap 194 and has a rectangular shape. The first sub-pixel electrode 190a is a rotated equilateral trapezoid, and has a left side disposed close to the second storage electrode 137b, a right side disposed opposite to the left side, and a 45° angle with respect to the gate lines 121a and 121b. Upper bevel and lower bevel. The second subpixel electrode 190b includes a pair of trapezoidal portions facing the oblique sides of the first subpixel electrode 190a, and a longitudinal portion facing the left side of the first subpixel electrode 190a.

Therefore, the gap 94 between the first sub-pixel electrode 190a and the second sub-pixel electrode 190b has a substantially uniform width, and includes upper and lower oblique portions 91, 93 at an angle of 45° to the gate lines 121a, 121b. and a longitudinal portion 92 of substantially uniform width.

The first sub-pixel electrode 190 a has a cutout portion 95 extending along the storage electrode line 131 , and is equally divided into an upper half and a lower half according to the cutout portion 95 . The entrance of the cutout portion 95 is formed on the right side of the first sub-pixel electrode 190a, and the entrance of the cutout portion 95 has a pair of oblique lines substantially parallel to the upper oblique line portion 91 and the lower oblique line portion 93 of the gap 94, respectively. side. The gaps 94 and the cutouts 95 are oppositely symmetrical to the storage electrode lines 131 .

At this time, the number of partitions or cutouts depends on design factors, such as the size of the pixel electrode 190, the ratio of the horizontal side to the vertical side of the pixel electrode 190, the characteristics and type of the liquid crystal layer 3, and the like.

Hereinafter, for convenience of explanation, the gap 94 is represented as a cutout.

In addition, the first subpixel electrode 190a overlaps with the first gate line 121a, and the second subpixel electrode 190b overlaps with the first and second gate lines 121a and 121b. The first gate line 121 a passes near the center of the upper half of the pixel electrode 190 .

The guard electrode 88 extends along the data line 171 and completely covers the data line 171 . The guard electrode 88 is supplied with a common voltage, which is supplied through the contact hole of the passivation layer 180 and the gate insulating layer 140, or may be from a short circuit point (not shown) that transmits the common voltage from the TFT array panel 100 to the common electrode panel 200. out) to be supplied. At this time, preferably, the distance between the guard electrode 88 and the pixel electrode 190 is minimized to reduce the aspect ratio.

The guard electrode 88 can prevent electromagnetic interference between the data line 171 and the pixel electrode 190, and between the data line 171 and the common electrode 270, so as to reduce the voltage distortion of the pixel electrode 190 and the signal delay of the data voltage carried by the data line 171.

In addition, since the pixel electrode 190 needs to be separated from the guard electrode 88 to prevent a short circuit therebetween, the distance between the pixel electrode 190 and the data line 171 is increased, thereby reducing the parasitic capacitance therebetween. Moreover, the permittivity of the LC layer 3 is higher than that of the passivation layer 180, and the parasitic capacitance between the data line 171 and the guard electrode 88 is compared with the parasitic capacitance between the data line 171 and the common electrode 270 when there is no guard electrode 88 Reduced.

In addition, since the pixel electrode 190 and the guard electrode 88 are formed of the same layer, the distance between them can be maintained uniformly, and therefore, the parasitic capacitance between them also remains unchanged.

The contact assistants 81a, 81b, 82 are respectively connected to the ends 129a, 129b of the gate lines 121a, 121b and the ends 179 of the data lines 171 through the contact holes 181a, 181b, 182 . The contact aids 81a, 81b, 82 protect the ends 129a, 129b and improve the adhesion between the ends 129a, 129b and the ends 179 and external devices.

When the gate driver or data driver is integrated on the panel assembly 300, the gate lines 121a, 121b or the data lines 171 are extended to be directly connected to the driver, and the contact assistants 81a, 81b, 82 can be used to connect the gate lines 121a, 121b or data line 171 to the driver.

Next, the common electrode panel 200 will be described in detail with reference to FIGS. 20-24 .

A light shielding member 220 called a black matrix to prevent light leakage is formed on an insulating substrate 210 made of transparent glass or plastic or the like. The light shielding member 220 has a plurality of openings facing the pixel electrode 190 while having almost the same shape as the pixel electrode 190 . Different from this, the light shielding member 220 includes a plurality of straight portions facing the data lines 171 on the TFT array panel 100 and a plurality of wide portions facing the TFTs Qa, Qb on the TFT array panel 100 . However, the light shielding member 220 may have various shapes in order to cut off light leakage near the pixel electrode 190 and the TFTs Qa, Qb.

A plurality of color filters 230 are also formed on the substrate 210 . Most of them are located in the area surrounded by the light shielding member 230 . The color filter 230 extends substantially longitudinally along the pixel electrode 190 . The color filter 230 displays one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light shielding member 230 . This coating 250 is preferably made of an (organic) insulator, and it prevents the color filter 230 from being exposed and provides a flat surface. Coating 250 may also be omitted.

A common electrode 270 is formed on the coating layer 250 . The common electrode 270 is preferably made of a transparent conductor such as ITO, IZO, etc. and has multiple sets of cutouts 271 , 273 , 275 .

A set of cutouts 271 , 273 , 275 faces the pixel electrode 190 and includes an upper cutout 271 , a central cutout 275 , and a lower cutout 273 . Each of the cutouts 271 , 273 , 275 is placed between the adjacent cutouts 94 , 95 of the pixel electrode 190 , or between the cutout 94 and the hypotenuse of the pixel electrode 190 . Each cutout portion 271 , 273 , 275 includes at least one oblique portion extending substantially parallel to the upper oblique portion 91 or the lower oblique portion 93 of the gap. The cutouts 271 , 273 , 275 are substantially antisymmetric with respect to the storage electrode line 131 .

The upper and lower cutout portions 271, 273 respectively include a slanted portion 271o or 273o, a transverse portion 271t or 273t, and a longitudinal portion 271l or 273l. The oblique portion 271 o or 273 o extends from the left side of the pixel electrode 190 and approximately reaches the lower or upper edge of the pixel electrode 190 . Each of the lateral portion 271t or 273t and the vertical portion 271l or 273l extends from each end portion of the oblique portion 271o or 273o along the edge of the pixel electrode 190 and overlaps with the side of the pixel electrode 190 so that it is opposite to the oblique portion 271o, 273o. form an obtuse angle.

The central cutout portion 275 includes a pair of oblique portions 275o1, 275o2, and a pair of terminating longitudinal portions 275l1, 275l2. The oblique portions 275o1, 275o2 extend approximately from the center of the left side of the pixel electrode 190 to the right side of the pixel electrode 190. The terminating longitudinal portions 275l1, 275l2 extend from the ends of the respective oblique portions 275o1, 275o2 along the right side of the pixel electrode 190, and overlap the right side of the pixel electrode 190, making obtuse angles with respect to the oblique portions 275o1, 275o2.

The number of cutouts 271 , 273 , 275 depends on design factors. The light shielding member 220 overlaps with the cutouts 271 , 273 , 275 to block light leaking through the cutouts 271 , 273 , 275 .

The inner sides of the panels 100, 200 are coated with an orientation layer 11, 21 which may be vertical.

Preferably, polarizers 12 , 22 are provided on the outer surfaces of the panels 100 , 200 , so that their polarization axes intersect, and one of the polarization axes is parallel to the gate lines 121 . When the LCD is a reflective LCD, one of the polarizers can be omitted.

The LCD also includes a retardation film (not shown) for compensating the retardation of the LC layer 3 . The LCD may further include a backlight (not shown), which supplies light to the LC layer 3 through polarizers 12, 22, a retardation film, and a panel 100.200.

Preferably, the LC layer 3 has negative dielectric anisotropy and undergoes a homeotropic orientation, wherein LC molecules in the LC layer 3 are oriented such that their longitudinal axes are substantially perpendicular to the panel 100, 200 in the absence of an electric field. Therefore, incident light cannot pass through the crossed polarizer system 12,22.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field almost perpendicular to the surfaces of the panels 100 and 200 is formed, and the pixel electrode 190 and the common electrode 270 are collectively referred to as "field generating electrodes". The LC molecules change their orientation in response to an electric field so that their long axes are perpendicular to the direction of the electric field.

The cutouts 94, 95, 271, 273, 275 of the field generating electrodes 190, 270 and the sides of the pixel electrode 190 distort the electric field so as to have sides substantially perpendicular to the cutouts 94, 95, 271, 273, 275 and A horizontal element on the side of the pixel electrode 190 .

Accordingly, the electric field is directed in a direction inclined to be perpendicular to the surface of the opposite panel 100 , 200 . Liquid crystal molecules tend to reorient so that their long axes are perpendicular to the direction of the electric field. Because the electric field close to the cutouts 94, 95, 271, 273, 275 and the pixel electrode 190 is not parallel to the long-axis direction of the LC molecules, but at a certain angle, the LC molecules rotate along the long-axis direction, and in the direction of the LC molecules. The plane defined by the long axis and the electric field has the shortest moving distance.

Referring to FIG. 21 , a set of cutouts 94 , 95 , 271 , 273 , 275 divides the pixel electrode 190 into a plurality of subregions, each subregion having two main sides forming an oblique angle with the main side of the pixel electrode 190 . The major sides of each sub-area form 45° with the polarization axis of the polarizer 12, 22 to maximize light efficiency.

Since most of the LC molecules on each sub-region are tilted perpendicular to the main side, the distribution of azimuth angles of the tilted directions is located in four directions, thereby increasing the reference viewing angle of the LCD.

The shape and arrangement of the cutouts 94, 95, 271, 273, 275 may vary.

At least one cutout 94, 95, 271, 273, 275 may be replaced by a protrusion (not shown) or a depression (not shown). The protrusions are preferably made of organic or inorganic materials and placed on or under the electric field generating electrode 190 or 270 .

An LCD according to another embodiment of the present invention will now be described in detail with reference to FIGS. 25 and 26. FIG.

25 is a block diagram of an LCD according to another embodiment of the present invention; FIG. 26 is an equivalent circuit diagram of a pixel of an LCD according to another embodiment of the present invention.

As shown in FIG. 25 , the LCD according to this embodiment of the present invention includes an LC panel assembly 300 , a gate driver 490 , a data driver 590 , a grayscale voltage generator 800 , and a signal controller 600 .

The panel assembly 300 includes a plurality of gate lines G1-Gn, a plurality of data lines D1-D2m, and a plurality of pixels PX. The number of gate lines G1-Gn is half that of the previous embodiment, and the number of data lines D1-D2m is twice that of the previous embodiment. A pair of data lines D1-D2m are arranged on the left and right sides of the pixel row.

As shown in FIGS. 25 and 26 , each pixel PX includes a pair of sub-pixels PXa, PXb. One sub-pixel PXa (hereinafter referred to as the first sub-pixel) includes a switching element Qa connected to the gate line and the right data line, an LC capacitor Clca connected to the switching element Qa, and a storage capacitor connected to the switching element Qa Csta. Another sub-pixel PXb (hereinafter referred to as the second sub-pixel) includes a switching element Qb connected to the gate line and the left data line, an LC capacitor Clcb connected to the switching element Qb, and a storage capacitor connected to the switching element Qb. Capacitor Cstb.

Examples of the LCD shown in FIGS. 25 and 26 will be described in detail below with reference to FIGS. 27 , 28 , 29 , 30A, and 30B.

Fig. 27 is a schematic layout diagram of a lower panel (TFT array panel) according to an embodiment of the present invention; Fig. 28 is a schematic layout diagram of an upper panel (common electrode panel) according to an embodiment of the present invention; Fig. 29 is a schematic diagram including the TFT shown in Fig. 27 The schematic layout of the array panel and the LC panel assembly of the common electrode panel shown in FIG. 28; FIGS. 30A and 30B are cross-sectional views of the LC panel assembly shown in FIG. 29 taken along lines XXXA-XXXA and XXXB-XXXB.

27-30B, the LC panel assembly according to this embodiment of the present invention includes: a TFT array panel 100, a common electrode panel 200 facing the TFT array panel 100, and a liquid crystal layer 3 sandwiched between the panels 100 and 200 .

First, the TFT array panel 100 will be described in detail with reference to FIGS. 25 , 30A, and 30B.

A plurality of pairs of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of, for example, transparent glass. Each gate line 121 includes a plurality of gate electrodes 124 and a wide end portion 129 . Each storage electrode line 131 includes a rectangular storage electrode 133 extending upward and downward. Each storage electrode line 131 is located between two adjacent gate lines 121 and is equidistant from the gate lines 121 .

A gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131 .

A plurality of semiconductor islands 154 a , 154 b are formed on the gate insulating layer 140 . The respective semiconductor islands 154 a and 154 b are provided on the gate electrode 124 .

A plurality of ohmic contact strips and islands 163a, 163b, 165a, 165b are formed on the semiconductor islands 154a, 154b. The ohmic contacts 163 a , 163 b , 165 a , 165 b are located in pairs on the semiconductor islands 154 a , 154 b and the ohmic contacts face each other with respect to the gate 124 .

A plurality of pairs of data lines 171 a , 171 b and a plurality of drain electrodes 175 a , 175 b are formed on the ohmic contacts 163 a , 163 b , 165 a , 165 b and the gate insulating layer 140 .

Each data line 171a, 171b includes U-shaped source electrodes 173a, 173b and wide end portions 179a, 179b. Each drain electrode 175 a , 175 b includes a wide end and a narrow end, wherein the wide end overlaps the storage electrode 133 . The sides of the wide ends of the drain electrodes 175 a and 175 b are substantially parallel to the sides of the storage electrode 133 .

A passivation layer 180 is formed on the data lines 171a, 171b and the drain electrodes 175a, 175b and exposed portions of the semiconductor islands 154a, 154b.

On the passivation layer 180, there are a plurality of contact holes 185a, 185b, 182a, 182b respectively exposing the drain electrodes 175a, 175b and the ends 179a, 179b of the data lines 171a, 171b, the passivation layer 180 and the gate insulating layer 140 has a plurality of contact holes 181 exposing the ends 129 of the gate lines 121 .

A plurality of pixel electrodes 190 including first and second sub-pixel electrodes 190a, 190b, a guard electrode 88, and a plurality of contact assistants 81, 82a, 82b are formed on the passivation layer 180. Referring to FIG.

Preferably, the area of the second sub-pixel electrode 190b is larger than that of the first sub-pixel electrode 190a, and preferably twice the area of the first sub-pixel electrode 190a. The LC molecules in the sub-pixel PXb subjected to a low data voltage have relatively Orientation close to its initial orientation, so that the distortion of low-voltage LC molecules has relatively little influence on side visibility, and the addition of sub-pixel electrodes 190b improves side visibility. Especially, when the area ratio is about 2:1 , side visibility can be greatly improved.

A pair of first and second subpixel electrodes 190a, 190b are basically located in the area surrounded by data lines 171a, 171b and gate lines 121, most of the outer boundaries of the first and second subpixel electrodes 190a, 190b are in line with The gate lines 121 or the data lines 171a, 171b are parallel to form a rectangle. The first and second subpixel electrodes 190a, 190b are separated from each other. The first sub-pixel electrode 190a includes two parts respectively disposed on the upper and lower sides of the second sub-pixel electrode 190b, and are connected to each other through vertical connectors. The second subpixel electrode 190b is disposed between two portions of the first subpixel electrode 190a.

Four corners of each pixel electrode 190 are chamfered, and the chamfered hypotenuse of the pixel electrode 190 forms an angle of about 45 degrees with respect to the gate line 121 .

The pixel electrode 190 has central cutouts 91, 92, lower cutouts 93a, 94a, 95a, and upper cutouts 93b, 94b, 95b, cutouts 91, 92, 93a, 93b, 94a, 94b, 95a, 95b is divided into a plurality of areas. The cutouts 91 , 92 , 93 a , 93 b , 94 a , 94 b , 95 a , 95 b are oppositely symmetrical to the storage electrode lines 131 . The first and second sub-pixel electrodes 190a, 190b are separated from each other by the cutout portions 93a, 93b and the cutout connectors 99 connecting the cutout portions 93a, 93b.

The lower and upper cutouts 93a, 93b, 94a, 94b, 95a, 95b extend from the left side, left corner, lower side, or upper side of the pixel electrode 190 to the right side of the pixel electrode 190 approximately obliquely. The lower cutouts 93 a - 95 a and the upper cutouts 93 b - 95 b are respectively disposed at upper and lower halves of the pixel electrode 190 , which can be separated by the storage electrode line 131 . The lower and upper cutouts 93a-95b form an angle of 45 degrees with the gate line 121, and they extend perpendicularly to each other.

Each of the central cutouts 91, 92 includes a central portion extending in the lateral direction, and a pair of oblique portions substantially parallel to the lower cutouts 93a-95a and the upper cutouts 93b-95b. The central cutout 92 is connected to a cutaway connector 99 .

Therefore, the lower half of the pixel electrode 190 is divided into six regions by the lower cutouts 91-95a, and the upper half of the pixel electrode 190 is divided into six regions by the upper cutouts 91-95b. The number of partitions or cutouts depends on design factors such as the size of the pixel electrode 190 , the ratio of the lateral side to the vertical side of the pixel electrode 190 , the type or characteristics of the liquid crystal layer 3 , and the like.

The pixel electrode 190 overlaps the adjacent gate line 121, or the adjacent data line 171a, 171b, so as to increase the aperture ratio.

The contact assistants 81, 82a, 82b are respectively connected to the end 129 of the gate line 121 and the ends 179a, 179b of the data lines 171a, 171b through the contact holes 181, 182a, 182b.

The guard electrode includes a plurality of lateral portions extending along the gate lines 121, and longitudinal portions extending along the data lines 171a, 171b. The vertical portion completely covers the data lines 171a, 171b, while the lateral portion is narrower than the gate line 121 to expose upper and lower edges of the gate line 121 . Two adjacent data lines 171a, 171b completely cover the lateral portion of the guard electrode 88 . However, it is also possible to vary the coverage given by the guard electrodes.

Next, the common electrode panel 200 will be described with reference to FIG. 28 and FIG. 30B .

The light blocking member 220 is formed on an insulating substrate 210 made of, for example, transparent glass or plastic. The light shielding member 200 includes a plurality of straight portions on the TFT array panel 100 facing the data lines 171 and wide portions on the TFT array panel 100 facing the TFTs Qa and Qb. In contrast, the light shielding member 220 has a plurality of openings facing the pixel electrode 190 and having almost the same shape as the pixel electrode 190 .

A plurality of color filters 230 are also formed on the substrate 210 , and a coating 250 is formed on the color filters 230 and the light shielding member 220 .

A common electrode 270 is formed on the coating 250, and the common electrode 270 has a plurality of sets of cutouts 71-76b.

A group of cutouts 71-76b face the pixel electrode 190, and include central cutouts 71-73, lower cutouts 74a, 75a, 76a, and upper cutouts 74b, 75b, 76b. Each cutout 71 - 76b is placed between the cutouts 91-95b of adjacent pixel electrodes 190 or between the edge cutouts 95a, 95b and the hypotenuse of the pixel electrode 190. Moreover, each cutout 71-76b includes a section parallel to the pixel electrode 190 At least one slash portion of the lower cutout portion 93a-95a or the upper cutout portion 93b-95b.

The lower and upper cutout portions 74a-76b respectively include a diagonal line portion, a pair of transverse and longitudinal portions, or a pair of longitudinal portions. The oblique portion extends approximately from the left side, left corner, lower side, or upper side of the pixel electrode 190 to the right side of the pixel electrode 190 . The lateral portion and the vertical portion extend from each end of the oblique portion along the side of the pixel electrode 190 , overlap with the side of the pixel electrode 190 , and form an obtuse angle with the oblique portion.

Each central cutout portion 71-73 includes a central transverse portion, a pair of oblique portions, and a pair of terminal longitudinal portions. The central lateral portion extends from the center or right edge of the pixel electrode 190 along the storage electrode line 131 . The oblique portion extends from the end of the central lateral portion approximately to the left of the pixel electrode, and forms an oblique angle with respect to the central lateral portion. The terminal longitudinal portion extends from each oblique portion along the left side of the pixel electrode 190, overlaps the left side of the element electrode 190, and forms an obtuse angle with respect to each oblique portion.

The number of cutouts 71-76b may vary depending on design factors, and the light blocking member 220 may overlap the cutouts 71-76b to block light leaking through the cutouts 71-76b.

Meanwhile, since there is no electric field between the common electrode 270 and the guard electrode 88, the LC molecules of the guard electrode 88 maintain their original orientation and thus block light incident thereon. Therefore, the guard electrode can be used as a light shielding member.

The shape and arrangement of the cutouts 71-76b and 91-95b may vary.

At least one cutout 91-95b, 71-76b may be replaced by a protrusion (not shown) or a depression (not shown). The protrusion is preferably made of an organic or inorganic material and is disposed above or below the field generating electrode 191 or 270 .

Alignment layers 11, 21 are respectively coated on the inner surfaces of the panels 100, 200, and the alignment layers may be homeotropic or homogeneous.

Polarizers 12 , 22 are arranged on the outer surfaces of the panels 100 , 200 , so that the polarization axes of the two polarizers intersect, and one of the polarization axes is parallel to the gate lines 121 . When the LCD is a reflective LCD, one of the two polarizers 12, 22 may be omitted.

Preferably, the LC layer 3 has a negative dielectric anisotropy, which is vertically oriented so that the LC molecules in the LC layer 3 are oriented such that their longitudinal axes are substantially perpendicular to the panels 100 and 200 in the absence of an electric field .

In this way, the TFT array panel according to this embodiment includes TFTs Qa and Qb connected to the two sub-pixel electrodes 190a, 190b forming a single pixel electrode 190, and a pair of data lines respectively connected to the TFTs Qa, Qb 171a and 171b. Therefore, the two subpixels Pxa and PXb receive different data signals.

LCD panel assemblies according to other embodiments of the present invention will be described in detail below with reference to FIGS. 31 to 32B.

Figure 31 is a schematic layout diagram of a TFT array panel according to another embodiment of the present invention; Figure 32A is a cross-sectional view taken along the line XXXIIA-XXXIIA of the TFT array panel shown in Figure 31; Figure 32B is a TFT array shown in Figure 31 Sectional view of the panel taken along line XXXIIB-XXXIIB.

Referring to FIGS. 31 to 32 , the layered structure of the TFT array panel 100 according to this embodiment is basically the same as that shown in FIGS. 29-30B .

That is, a plurality of gate lines 121 including gate electrodes 124 and end portions 129 are formed on the substrate 110, and a plurality of storage electrode lines 131 including storage electrodes 133 are formed on the gate lines 121 and storage electrode lines 131 in sequence. Gate insulating layer 140, a plurality of semiconductor strips 151a, 151b including protrusions 154a and 154b, and a plurality of ohmic contact strips 161 including protrusions 163a and 163b and ohmic contact islands 165a and 165b. A plurality of data lines 171a, 171b comprising source electrodes 173a, 173b and ends 179a, 179b, and a plurality of drain electrodes 175a and 175b are formed on , 165b. On the data lines 171a, 171b, a drain electrode 175a and 175b, The passivation layer 180 is formed on the insulating layer 140 and the exposed parts of the semiconductor strips 151a, 151b. A plurality of contact holes 181, 182a, 182b, 185a, 185b are formed on the passivation layer 180 and the gate insulating layer 140. A plurality of sub-pixel electrodes 190 including sub-pixel electrodes 190a and 190b and cutouts 91-95b, a guard electrode 88, and a plurality of contact assistants 81, 82a, 82b are formed on the layer 180, and an alignment layer is coated thereon 11.

Unlike the TFTs shown in FIGS. 29-30B , semiconductor strips 151a, 151b have almost the same planar shape as data lines 171a, 171b, drain electrodes 175a, 175b, and underlying ohmic contacts 161a, 161b, 165a, and 165b. However, the semiconductors 151a and 151b include some exposed portions which are not covered by the data lines 171a, 171b and the drain electrodes 175a, 175b, for example, the portions between the source electrodes 173a, 173b and the drain electrodes 175a, 175b.

The manufacturing method of the TFT array panel according to this embodiment simultaneously forms data lines 171a, 171b, drain electrodes 175a, 175b, semiconductors 151a, 151b, and ohmic contacts 161a, 161b, 165a, and 165b in one photolithography step.

A photoresist mask pattern used in a photolithography process has a thickness depending on a location, and in particular, it has a thicker portion and a thinner portion. The thicker portion is located in the wiring area occupied by the data lines 171a, 171b and the drain electrodes 175a, 175b, and the thinner portion is located in the channel area of the TFT.

The location-dependent thickness of the photoresist can be obtained by several processes, for example, by providing semi-transparent areas on a thin film mask, as well as transparent areas, and light-blocking areas. The translucent area has a cutout pattern, a grid pattern, a film with intermediate transmittance or intermediate thickness. When the cutout pattern is used, preferably, the width of the cutouts or the distance between the cutouts is smaller than the resolution of a light exposer used for photolithography. Another example is the use of reflowable photoresists. In detail, once a photoresist pattern made of a reflowable material is formed using a conventional exposure mask with only transparent and opaque areas, it can flow through the reflow process to the areas without photoresist, forming thinner parts .

Thus, the manufacturing process can be simplified by omitting the photolithography step.

In the LCD, the signal controller 600 outputs image data DAT for two subpixels PXa, PXb of a pixel row, and the data driver 590 simultaneously supplies image data to the two subpixels Pxa, PXb through a pair of data lines.

Therefore, the operation period of the gate driver 490 and the data driver 590 is one horizontal period.

The inversion of the LCD according to the embodiment of the present invention will be described in detail below with reference to FIG. 33 and FIG. 25 .

Figure 33 shows the polarity of the pixel electrodes in column inversion according to an embodiment of the present invention.

In FIG. 33, the data driver 590 performs column inversion such that data voltages applied to data lines have the same polarity within one frame, and data voltages applied to two adjacent data lines have opposite polarities.

Therefore, the polarities of the first and second sub-pixel electrodes 190a and 190b of the pixel electrode 190 are opposite, while the first pixel electrode 190a of the pixel electrode 190 has the same polarity, and the second pixel electrode 190b of the pixel electrode 190 also has same polarity. For example, the subpixel electrode 190a has positive polarity (+) within one frame, and the subpixel electrode 190b has negative polarity (−) within one frame.

Thus, although the data driver 590 performs column inversion, since the pixel electrode 190 has positive and negative polarities, there is no defect of vertical stripes. In addition, pixels representing the same color have the same polarity state, thus reducing image quality degradation due to polarity differences between pixels of the same color. In addition, the polarity of the data voltage in the data line is reversed by the frame, and thus the response time of the liquid crystal and the signal delay in the data line are improved compared to the case of inverting the polarity by the row.

In this way, the voltages of the two subpixels can be precisely controlled to improve visibility, aperture ratio, and transmittance.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (28)

1. A display device, comprising: A pixel, including a first sub-pixel and a second sub-pixel; a first gate line connected to the first sub-pixel and transmitting a first gate signal; a second gate line connected to the second sub-pixel and transmitting a second gate signal; a first data line crossing the first and second gate lines, connected to at least one of the first and second sub-pixels, and transmitting a first data signal; and a second data line crossing the first and second gate lines and transmitting a second data signal, Wherein, the first sub-pixel and the second sub-pixel are supplied with data voltages having different magnitudes, and The data voltages supplied to the first and second sub-pixels are generated from a single image information. 2. The display device according to claim 1, wherein, The first sub-pixel includes a first switching element connected to the first gate line, and a first liquid crystal capacitor connected to the first switching element, and The second sub-pixel includes a second switching element connected to the second gate line, and a second liquid crystal capacitor connected to the second switching element. 3. The display device according to claim 2, wherein, the first liquid crystal capacitor includes a first subpixel electrode connected to the first switching element, and The second liquid crystal capacitor includes a second subpixel electrode connected to the second switching element. 4. The display device according to claim 3, wherein the first and second subpixel electrodes are formed at oblique angles to the first and second gate lines and the first and second data lines. The gaps are spaced apart from each other. 5. The display device according to claim 3, wherein at least one of the first and second sub-pixel electrodes has a connection with the first and second gate lines and the first and second data lines. Angled incision. 6. The display device according to claim 3, wherein the first and second sub-pixels further comprise a common electrode having a cutout portion, the cutout portion is connected to the first and second gate lines and The first and second data lines are oblique. 7. The display device according to claim 2, wherein the first switching element is connected to the first gate line and the first data line, and the second switching element is connected to the second gate lines and the first data lines. 8. The display device according to claim 7, wherein the first switching element is turned on and transmits the first data signal according to the first gate signal, and the second switching element is turned on according to the first gate signal. The second gate signal is turned on and transmits the first data signal. 9. The display device according to claim 7, wherein the first switching element is turned on and transmits the first data signal according to the first gate signal, and the second switching element is turned on according to the first gate signal. The second gate signal is turned on and transmits the first data signal. 10. The display device according to claim 2, wherein the first subpixel is connected to the first gate line and the first data line, and the second subpixel is connected to the second gate lines and the second data lines. 11. The display device according to claim 2, wherein the first subpixel further comprises a first storage capacitor connected to the first switching element, and the second subpixel further comprises a storage capacitor connected to the first switching element. A second storage capacitor on the second switching element. 12. The display device according to claim 1, wherein first and second grayscale voltage groups different from each other are generated, and the first subpixel electrode is supplied with a voltage selected from the first grayscale voltage group. voltage, and the second subpixel electrode is supplied with a voltage selected from the second grayscale voltage group. 13. The display device according to claim 1 , wherein the image information is processed to generate first and second image signals, and the first and second sub-pixel electrodes are supplied corresponding to the first and second sub-pixel electrodes. A voltage selected from a single gray scale voltage group of the second image signal. 14. The display device of claim 1, wherein the first subpixel and the second subpixel are capacitively coupled to each other. 15. A liquid crystal display comprising: A pixel, including a first sub-pixel and a second sub-pixel; a gate line connected to the first and second sub-pixels and transmitting a gate signal; a first data line crossing the gate line, connected to the first sub-pixel, and transmitting a first data voltage; and The second data line crosses the gate line, is connected to the second sub-pixel, and transmits the second data voltage. 16. The liquid crystal display of claim 15, wherein the first data voltage is different from the second data voltage, and the first and second data voltages are generated from a single image information. 17. The liquid crystal display of claim 16, wherein a polarity of the first data voltage is opposite to a polarity of the second data voltage. 18. The liquid crystal display of claim 17, wherein the polarity of the first data voltage is kept constant for a predetermined time. 19. A thin film transistor array panel, comprising: a gate line formed on the substrate; first and second data lines insulated from and crossing the gate lines; a first thin film transistor connected to the gate line and the first data line and including a first drain electrode; a second thin film transistor connected to the gate line and the second data line and including a second drain electrode; a passivation layer formed on the gate line, the first and second data lines, and the first and second thin film transistors, and has a first contact hole exposing the first data line and exposing the the second contact hole of the second data line; and A pixel electrode, including a first subpixel electrode connected to the first drain electrode through the first contact hole, and a second subpixel electrode connected to the second drain electrode through the second contact hole . 20. The thin film transistor array panel according to claim 19, further comprising an electrode insulated from the first and second sub-pixel electrodes and connected to at least one of the gate lines and the first and second data lines. An overlapping guard electrode. 21. The thin film transistor array panel according to claim 20, wherein the pixel electrode and the guard electrode are disposed on the passivation layer. 22. The thin film transistor array panel of claim 20, further comprising a storage electrode line including a storage electrode overlapping the first and second drain electrodes to form a storage capacitor. 23. The thin film transistor array panel of claim 22, wherein the guard electrode and the storage electrode are supplied with a single voltage. 24. The thin film transistor array panel of claim 23, wherein the guard electrode completely covers the first and second data lines. 25. The thin film transistor array panel according to claim 19, wherein an area of the first sub-pixel electrode is different from an area of the second sub-pixel electrode. 26. A method for driving a liquid crystal display, the liquid crystal display comprising a plurality of pixels, each of the pixels comprising a first sub-pixel and a second sub-pixel, the method comprising: transfer image data; Output the first group of grayscale voltages; converting the image data into a first data voltage selected from the first set of grayscale voltages; applying the first data voltage to the first subpixel; outputting the second set of grayscale voltages different in size from the first set of grayscale voltages by replacing the first set of grayscale voltages with a second set of grayscale voltages by using a multiplexer; converting the image data into a second data voltage selected from the second set of grayscale voltages; and Applying the second data voltage to the second sub-pixel. 27. The method of claim 26, further comprising: generating the first and second groups of grayscale voltages; Wherein, the output of the first group of grayscale voltages includes: selecting the first set of grayscale voltages by using the multiplexer, and Wherein, the output of the second group of grayscale voltages includes: The second group of gray-scale voltages is selected by using the multiplexer. 28. The method of claim 26, further comprising: storing the first and second sets of digital grayscale data; Wherein, the output of the first group of grayscale voltages includes: selecting the first set of digital grayscale data by using the multiplexer; and analog converting the first set of digital grayscale data into the first set of grayscale voltages, and Wherein, the output of the second group of grayscale voltages includes: selecting a second set of digital grayscale data by using the multiplexer; and converting the second set of digital grayscale data into the second set of grayscale voltages by analog.

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