CN1771601A - Electronic packaging structure with integrated distributed decoupling capacitors - Google Patents

Abstract

An electronic packaging structure, comprising a substrate; a first electrode layer on a first side of said substrate; dielectric material arranged in a preselected pattern on said first electrode layer); and a second electrode layer forming a plurality of second electrodes which are arranged on said preselected pattern of dielectric material to form a distributed capacitive structure together with said first electrode layer, is characterized in that a second decoupling capacitor stage is arranged on a second side of said substrate opposite said first side and is electrically connected to said distributed capacitive structure, said second decoupling stage having a capacity higher than that of said distributed capacitive structure.

Description

Electronic package structure with integrated distributed decoupling capacitors

The present invention relates to an electronic packaging structure comprising a substrate, a first electrode layer on a first side of the substrate, a dielectric material arranged in a preselected pattern on the first electrode layer and forming a plurality of second A second electrode layer of the electrode layers, said plurality of second electrode layers being arranged on said preselected pattern of dielectric material, forms a distributed capacitance structure together with said first electrode layer as a first decoupling stage. The invention also relates to an integrated circuit comprising the electronic package of the invention.

Powering a system-on-chip including high-speed digital cores operating at high currents and low voltages requires high-speed power modules and a minimum of parasitic passive components within the power supply network to avoid noise as much as possible.

A known technique for reducing the noise level is to place discrete capacitors between the relevant voltage pins. Discrete capacitors, typically mounted some distance from the semiconductor core, are electrically coupled to the semiconductor core through multiple power traces or a large power bus. These power routings typically represent highly inductive paths that should be minimized by moving the discrete capacitors as close as possible to the semiconductor chip. For high-frequency decoupling capacitors mounted closest to the core, their characteristics in terms of parasitic impedance determine the maximum current transient and thus the system speed. The better the performance of this capacitor, the more current transients can be shifted to higher values within a given tolerance to allowable voltage fluctuations and high frequency oscillations.

US 4,945,399 discloses an electronic packaging structure comprising a plurality of integrated, distributed decoupling capacitors. A metal bottom layer formed on the substrate includes at least a portion forming the first plate of the decoupling capacitor and includes at least one electrical connection for attaching the semiconductor chip. A thin layer of dielectric material covers the bottom layer. A top layer serving as a second plate of the capacitor is formed on the dielectric material and placed relative to the first plate to form a decoupling capacitor. The structure may be arranged under the die of the chip. Keep the length of the connector to a minimum in order to minimize any resulting inductance and keep the decoupling capacitors as close to the die as possible.

An object of the present invention is to provide a further improved electronic packaging structure.

In the electronic packaging structure described above, by arranging a second decoupling capacitor stage with high capacitance on a second side of the substrate opposite to the first side and electrically connecting it to the distributed capacitance structure This purpose. The capacitance of the second decoupling capacitor stage is high enough to provide a low impedance connection to the power dissipator and may be 5 to 100 times, preferably about 10 times, the capacitance of the first decoupling stage.

It should be noted that the pattern of the second electrode and the dielectric material depends on the distance from the connector to the chip to be powered.

The distributed capacitance structure with very low series inductance and a dielectric material with a very high dielectric constant of 1000 or greater can be mounted directly under the die or its substrate and supported to provide the next filter stage on the opposite side of the component. Thus, not only the distributed plate structure is coupled to the power dissipator with an optimally low inductance, but also the considerably improved second decoupling capacitor stage which produces decoupling in the high frequency range can also be coupled with an optimally low inductance way coupled to the power dissipator.

In a preferred embodiment, said distributed capacitance structure comprises alternating polarities in a first direction on said substrate and alternating polarities in a second direction on said substrate substantially perpendicular to said first direction. polarity. Thus, a fine mesh capacitive region is provided consisting of a common electrode mounted between the substrate and the dielectric material. The distributed capacitance structure includes a large number (eg, 100) of individual units connected in parallel.

To effectively achieve this effect, contact areas to said first electrode layer may be formed in said preselected pattern of holes of said dielectric material to provide one of said polarities of said distributed capacitive structure. Since the alternating polarity is arranged next to the other, high frequency peaks are filtered out as this arrangement exhibits the least inductance.

Preferably, said substrate comprises vias provided for connecting said distributed capacitance structure and said second decoupling capacitor stage. Those skilled in the art will appreciate that, if necessary, the vias equally extend through the first electrode layer and as part of a preselected pattern of the dielectric material.

The second decoupling capacitor stage may comprise a plurality of capacitors.

The substrate may be made of a conductive material, such as conductive silicon (Si).

An integrated circuit may be built comprising a processor and an electronic package of the invention, wherein preferably said second electrode layer of the electronic package faces said processor.

The electronic packaging structure of the present invention provides a module with reduced parasitic impedance in terms of inductance and resistance. The fluctuation of the supply voltage caused by the voltage drop of the resistor and the inductor is reduced, which allows the application of higher current transients. Therefore, excitation of power line oscillations occurs only at higher frequencies and reduced amplitudes. Signal integrity problems caused by EMI will be significantly mitigated.

A typical application of the invention is in a power supply network as a connection between a power supply unit such as a voltage regulation module (VRM) and a load. Typically, such a power supply network includes several mains filter stages for the sockets and decoupling capacitors as an integral part of the chip itself. Two trends were observed when traveling the route from the voltage regulation module to the chip. The capacitance of the capacitor, the impedance connecting the inductor and the resistor, and the parasitic series inductance and resistance of the capacitor become smaller. This means that less energy can be stored in the capacitor at a reduced distance to the load, however, this energy is quickly available due to the very small impedance in the immediate vicinity. Low frequency load steps representing longer continuous changes in current demand are mainly covered by large capacitors in the farther environment, however the voltage regulation module itself must be able to Follows much slower changes in load. The supply network therefore comprises an arrangement of filter stages finely tuned between one another and also to the load, the characteristics of which are always optimized for parasitic impedances. In the present invention, the first filter stage provides multiple capacitors or even distributed capacitors that are connected to the chip with a relatively low inductance and include relatively low capacitance, which means that relatively low of storable energy. Furthermore, the module already includes a second filter stage adjacent thereto (i.e. a second decoupling capacitor stage) with approximately 5 to 100 times the energy storage in the form of discrete capacitors, e.g. layer ceramic capacitors. These capacitors of the second filter stage are connected to the first filter stage with a rather low impedance compared to hitherto known structures, however, due to the through contact it is a rather high impedance to the first filter stage impedance connection.

The present invention will be described in more detail by referring to the drawings and the following description.

Figure 1 shows the construction of an electronic packaging structure according to the present invention in vertical section; and

FIG. 2 shows an item view of a part of the configuration of FIG. 1 .

In FIG. 1 , a dielectric material 1 is provided between a first electrode 2 and a plurality of second electrodes 3 . The dielectric material is, for example, a thin ceramic with a relative permittivity of 1000 or greater. Typical values for the thickness of the dielectric material are 50 nm to 500 nm. The dielectric material 1 is structured to provide access to the first electrode layer 2 so that a contact region 6 can be formed. Thereby, a connector area of alternating polarity 5a and 5b is achieved. For example, flip-chip solder bumps provide contact to each second electrode 3 and to the common first electrode layer 2 through contact areas 6 . The device is supported on a substrate 4 which may be conductive in order to reduce the resistance and inductance of the first electrode 2 and save a through connection to the electrode 10 . A plurality of discrete capacitors 9 are arranged below the substrate 4 to provide a second stage of decoupling capacitors. Alternating polarity is provided by electrodes 10 on the underside of said substrate 4 and conductive through-plating 8 at the inner walls of through-holes 11 provided in substrate 4, first electrode layer 2 and dielectric material 1 . An insulating liner 7 is introduced into each through hole to avoid contact of the plating with the first electrode layer 2 and the conductive substrate 4 .

FIG. 2 shows a top view of the structure of FIG. 1 . Extending in two directions perpendicular to each other forms a network of regions of alternating polarity 5a, 5b. The size of a single capacitor unit is defined by the pitch 12, which in turn depends on the pitch (distance between connectors of the chips to be powered).

However, the electrode connections for contacting the discrete capacitors 9 (second decoupling filter stage) at the bottom side of the substrate 4 form a checkered-like pattern showing significantly larger pitches.

Claims (9)

1. An electronic packaging structure, comprising: a substrate (4); a first electrode layer (2) on a first side of the substrate (4); arranged in a preselected pattern on the first electrode layer ( 2) a dielectric material (1); and a second electrode layer forming a plurality of second electrodes (3) arranged on said preselected pattern of the dielectric material (1) , so as to form a distributed capacitance structure together with the first electrode layer (2) as the first decoupling stage, characterized in that: the second decoupling capacitor stage (9) is arranged on the side opposite to the first side On the second side of the substrate (4) and electrically connected to the distributed capacitance structure, the capacitance of the second decoupling capacitor stage (9) is higher than the capacitance of the distributed capacitance structure. 2. Electronic package structure according to claim 1, characterized in that said distributed capacitance structure comprises alternating polarities (5a, 5b) in a first direction on said substrate (4) and in said substrate (4) Alternating polarity (5a, 5b) in a second direction on (4), said second direction being substantially perpendicular to said first direction. 3. An electronic package structure according to claim 2, characterized in that contact areas (6) to said first electrode layer (2) are formed in said preselected pattern of holes in said dielectric material (1) to One of the polarities of the distributed capacitance structure is provided. 4. The electronic package structure according to claim 1, characterized in that said substrate (4) comprises vias (11) provided for connecting said distributed capacitance structure and said second decoupling stage (9). 5. An electronic package structure according to claim 1, characterized in that said high capacitance decoupling stage (9) comprises a plurality of capacitors. 6. The electronic packaging structure according to claim 1, characterized in that the capacitance of the second decoupling stage (9) is 5 to 100 times, preferably about 10 times, that of the distributed capacitance structure. 7. The electronic package structure according to claim 1, characterized in that said substrate (4) is made of a conductive material. 8. An integrated circuit comprising a processor and an electronic package according to any one of the preceding claims. 9. The integrated circuit of claim 7, wherein said second electrode layer (3) of the electronic package structure faces said processor.