CN1758422A - Optically coupled packaging method for thick film printing circuit - Google Patents
Optically coupled packaging method for thick film printing circuit Download PDFInfo
- Publication number
- CN1758422A CN1758422A CNA2004100804165A CN200410080416A CN1758422A CN 1758422 A CN1758422 A CN 1758422A CN A2004100804165 A CNA2004100804165 A CN A2004100804165A CN 200410080416 A CN200410080416 A CN 200410080416A CN 1758422 A CN1758422 A CN 1758422A
- Authority
- CN
- China
- Prior art keywords
- glue
- optocoupler
- curing
- hours
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明涉及一种用于厚膜印刷电路的光耦封装方法，对分布在厚膜印刷电路上的光耦裸芯片用三层绝缘胶使用涂覆方式进行封装；第一层为透明胶，覆盖住印刷电路上的金丝及光耦裸芯片，固化温度自室温开始逐渐升温至125℃，固化时间为2小时，然后涂覆第二层散射胶，所述散射胶的厚度为0.1毫米－1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时；最后涂覆第三层遮光胶，所述遮光胶的厚度为0.1毫米－1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时。本发明的有益效果是，为厚膜电路提供了一种新的封装技术，解决了封装壳内厚膜电路上多个光耦之间彼此干扰的难题，并且能防止因封装材料的应力过大而将金丝拉断。The invention relates to an optocoupler packaging method for thick-film printed circuits. The optocoupler bare chips distributed on the thick-film printed circuit are encapsulated with three layers of insulating glue; the first layer is transparent glue, covering The gold wire and optocoupler bare chip on the printed circuit, the curing temperature is gradually raised from room temperature to 125°C, the curing time is 2 hours, and then the second layer of scattering glue is coated, and the thickness of the scattering glue is 0.1mm-1 mm, the curing temperature gradually rises from room temperature to 125°C, and the curing time is 2 hours; finally, a third layer of light-shielding glue is applied, the thickness of the light-shielding glue is 0.1mm-1mm, and the curing temperature gradually rises from room temperature to 125°C °C, the curing time is 2 hours. The invention has the beneficial effects of providing a new packaging technology for thick film circuits, solving the problem of mutual interference between multiple optocouplers on the thick film circuit in the packaging shell, and preventing And break the gold wire.
Description
技术领域technical field
本发明涉及一种用于厚膜印刷电路的光耦封装方法，该方法用绝缘胶对单个光耦进行封装，防止厚膜电路上多个光耦之间的彼此干扰。The invention relates to a photocoupler encapsulation method for a thick-film printed circuit. The method uses insulating glue to package a single photocoupler to prevent mutual interference between multiple photocouplers on the thick-film circuit.
背景技术Background technique
中国专利02123191公开了一种半导体封装件及其制法，该封装件具有一导线架，该导线架是由至少若干条管脚所构成，该管脚上形成一厚度小于管脚的凸出段，该凸出段第一表面上预先定义出一金线焊接区域与凸出段相对的第二表面上用以提供多条导电组件接设的焊块植接区域错位隔开；将载有多个芯片及该导电组件的导线架移入夹具内实施打线时，由于该焊块植接区域与该金线焊接区域相隔甚远，因此焊线压接时产生的向下压力可完全避开导电组件的植接位置，以防组件受压裂损；相对地，该金线焊接区域亦能远离导电组件的作业环境，避免作业中使用的溶液污损管脚预镀表面而影响金线的焊接品质。该封装可以对内部电路提供机械和环境保护，但是对厚膜电路内的多个光耦裸芯片进行单个封装时，既要控制光耦传输比的大小，又要防止封装材料因应力过大而将金丝拉断，还要防止封装壳内厚膜电路上多个光耦之间的彼此干扰，已有的封装技术无法满足上述要求，因此，需要提出一种新的厚膜印刷电路的光耦封装方法。Chinese patent 02123191 discloses a semiconductor package and its manufacturing method. The package has a lead frame, the lead frame is composed of at least several pins, and a protruding section with a thickness smaller than the pin is formed on the pin A gold wire welding area is pre-defined on the first surface of the protruding section, and the second surface opposite to the protruding section is used to provide a plurality of conductive components connected to the welding block planting area; When a chip and the lead frame of the conductive component are moved into the fixture for wire bonding, since the solder bump implantation area is far away from the gold wire soldering area, the downward pressure generated when the wire is crimped can completely avoid the conductive wire. The implanted position of the component is to prevent the component from being damaged by fracturing; relatively, the gold wire welding area can also be far away from the working environment of the conductive component, so as to prevent the solution used in the operation from contaminating the pre-plated surface of the pin and affecting the welding of the gold wire quality. This package can provide mechanical and environmental protection for the internal circuit, but when packaging multiple optocoupler bare chips in a thick film circuit, it is necessary to control the transmission ratio of the optocoupler and prevent the packaging material from being damaged due to excessive stress. Pulling off the gold wire and preventing mutual interference between multiple optocouplers on the thick film circuit in the package, the existing packaging technology cannot meet the above requirements. Therefore, it is necessary to propose a new optocoupler for thick film printed circuits. coupling packaging method.
发明内容Contents of the invention
本发明的目的在于提供一种用于厚膜印刷电路的光耦封装方法，该方法可以解决封装壳内厚膜电路上多个光耦之间的彼此干扰，并能对内部电路提供机械和环境保护。The object of the present invention is to provide a method for packaging optocouplers for thick film printed circuits, which can solve the mutual interference between multiple optocouplers on the thick film circuit in the package shell, and can provide mechanical and environmental protection for the internal circuit. Protect.
本发明的目的是由下述技术方案实现的：一种用于厚膜印刷电路的光耦封装方法，其特征在于：对分布在厚膜印刷电路上的光耦裸芯片用三层绝缘胶使用涂覆方式进行封装；第一层为透明胶，覆盖住印刷电路上的金丝及光耦裸芯片，固化温度自室温开始逐渐升温至125℃，固化时间为2小时，然后涂覆第二层散射胶，所述散射胶的厚度为0.1毫米-1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时；最后涂覆第三层遮光胶，所述遮光胶的厚度为0.1毫米-1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时。The purpose of the present invention is achieved by the following technical proposal: a kind of optocoupler encapsulation method for thick film printed circuit, it is characterized in that: use three layers of insulating glue to distribute on the optocoupler bare chip on the thick film printed circuit Coating method for encapsulation; the first layer is transparent glue, covering the gold wire on the printed circuit and the bare chip of the optocoupler, the curing temperature gradually rises from room temperature to 125°C, the curing time is 2 hours, and then the second layer is applied Scattering glue, the thickness of the scattering glue is 0.1 mm-1 mm, the curing temperature is gradually increased from room temperature to 125 ° C, and the curing time is 2 hours; finally, the third layer of light-shielding glue is coated, and the thickness of the light-shielding glue is 0.1 mm-1 mm, the curing temperature gradually increases from room temperature to 125°C, and the curing time is 2 hours.
本发明的有益效果是，为厚膜电路提供了一种新的封装技术，解决了封装壳内厚膜电路上多个光耦之间彼此干扰的难题，并且能防止因封装材料的应力过大而将金丝拉断。本发明工艺稳定，适合批量生产，降低了材料成本。The invention has the beneficial effects of providing a new packaging technology for thick film circuits, solving the problem of mutual interference between multiple optocouplers on the thick film circuit in the packaging shell, and preventing And break the gold wire. The process of the invention is stable, suitable for batch production, and reduces material cost.
附图说明Description of drawings
以下结合附图及实施例对本发明作进一步说明。The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
图1为厚膜印刷电路上的光耦封装剖面视图Figure 1 is a cross-sectional view of an optocoupler package on a thick film printed circuit
具体实施方式Detailed ways
实施例一：Embodiment one:
参见图1，一种用于厚膜印刷电路的光耦封装方法，对分布在厚膜印刷电路上的多个光耦裸芯片用三层绝缘胶使用涂覆方式进行封装；第一层为透明胶5，覆盖住印刷电路上的金丝2及光耦裸芯片1，固化温度自室温开始逐渐升温至125℃，固化时间为2小时，然后涂覆第二层散射胶4，所述散射胶的厚度为0.1毫米-1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时；最后涂覆第三层遮光胶3，所述遮光胶的厚度为0.1毫米-1毫米，固化温度自室温开始逐渐升温至125℃，固化时间为2小时。See Figure 1, an optocoupler packaging method for thick-film printed circuits. Multiple optocoupler bare chips distributed on thick-film printed circuits are packaged with three layers of insulating glue; the first layer is
在本实施例中，可以通过调整透明胶的厚度来控制光耦传输比的大小，并可通过调整三层胶的固化温度和固化时间来提高效率，并且不影响三层胶对金丝的应力。在本实施例中可以采用手工刷涂的涂覆方式，也可以采用喷涂的涂覆方式。第一层胶的厚度可以采用较厚的涂层，主要用于将印刷电路上的金丝及光耦裸芯片覆盖住，其厚度通常在0.5-2毫米之间。所述的透明胶是一种有机凝胶，其型号为GN521。所述的散射胶由下述的材料按重量比配置而成：MgO∶TiO2∶透明胶＝1∶1∶3。所述的遮光胶由下述的材料按重量比配置而成：炭粉∶透明胶＝1∶4。在本实施例中，封装的环境条件为：净化等级：100000级，温度：25℃±10℃，湿度：45-75％。In this embodiment, the transmission ratio of the optocoupler can be controlled by adjusting the thickness of the transparent glue, and the efficiency can be improved by adjusting the curing temperature and curing time of the three-layer glue without affecting the stress of the three-layer glue on the gold wire . In this embodiment, manual brushing or spraying can be used. The thickness of the first layer of glue can be a thicker coating, which is mainly used to cover the gold wire on the printed circuit and the bare chip of the optocoupler, and its thickness is usually between 0.5-2 mm. Described transparent glue is a kind of organic gel, and its model is GN521. The scattering glue is made of the following materials according to the weight ratio: MgO:TiO 2 :transparent glue=1:1:3. The light-shielding glue is prepared from the following materials in a weight ratio: carbon powder:transparent glue=1:4. In this embodiment, the encapsulation environment conditions are: purification grade: 100000 grade, temperature: 25°C±10°C, humidity: 45-75%.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2004100804165A CN1758422A (en) | 2004-10-09 | 2004-10-09 | Optically coupled packaging method for thick film printing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2004100804165A CN1758422A (en) | 2004-10-09 | 2004-10-09 | Optically coupled packaging method for thick film printing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1758422A true CN1758422A (en) | 2006-04-12 |
Family
ID=36703705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004100804165A Pending CN1758422A (en) | 2004-10-09 | 2004-10-09 | Optically coupled packaging method for thick film printing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1758422A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339764A (en) * | 2011-06-04 | 2012-02-01 | 湖北东光电子股份有限公司 | Thick-film hybrid integrated circuit surface enveloping process |
| CN103760881A (en) * | 2014-02-20 | 2014-04-30 | 北京七星华创电子股份有限公司 | Method and system for monitoring and managing use condition of materials |
| CN104282698A (en) * | 2013-07-08 | 2015-01-14 | 胜开科技股份有限公司 | Image sensor two-stage packaging method |
-
2004
- 2004-10-09 CN CNA2004100804165A patent/CN1758422A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339764A (en) * | 2011-06-04 | 2012-02-01 | 湖北东光电子股份有限公司 | Thick-film hybrid integrated circuit surface enveloping process |
| CN102339764B (en) * | 2011-06-04 | 2013-03-20 | 湖北东光电子股份有限公司 | Thick-film hybrid integrated circuit surface enveloping process |
| CN104282698A (en) * | 2013-07-08 | 2015-01-14 | 胜开科技股份有限公司 | Image sensor two-stage packaging method |
| CN104282698B (en) * | 2013-07-08 | 2017-10-20 | 胜丽国际股份有限公司 | Image sensor two-stage packaging method |
| CN103760881A (en) * | 2014-02-20 | 2014-04-30 | 北京七星华创电子股份有限公司 | Method and system for monitoring and managing use condition of materials |
| CN103760881B (en) * | 2014-02-20 | 2016-01-27 | 北京七星华创电子股份有限公司 | A kind of method for managing and monitoring of material service condition and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103985723B (en) | Method for packing and encapsulating structure | |
| US20110156251A1 (en) | Semiconductor Package | |
| WO2008093586A1 (en) | Resin-encapsulated semiconductor device and its manufacturing method | |
| CN105609490B (en) | Packaging structure of composite sensor module and manufacturing method thereof | |
| CN208460789U (en) | A kind of micro- spacing display module | |
| CN1758422A (en) | Optically coupled packaging method for thick film printing circuit | |
| CN206921851U (en) | The LED encapsulation structure of anti-vulcanization | |
| CN106356437A (en) | White LED (light emitting diode) packaging device and preparation method thereof | |
| TWI783631B (en) | Package structure of vertical chip and horizontal chip and manufacturing method thereof | |
| US20100230826A1 (en) | Integrated circuit package assembly and packaging method thereof | |
| CN203055984U (en) | COB LED packaging structure | |
| CN208111424U (en) | Chip-packaging structure | |
| CN101207105A (en) | Window-type ball grid array substrate and semiconductor package thereof | |
| CN222851446U (en) | Semiconductor device packaging structure | |
| CN214313206U (en) | Packaging structure of cavity sensor circuit | |
| CN201804912U (en) | LED encapsulation structure with high heat-conducting property | |
| CN203707165U (en) | High-bonding and high-reliability white LED chip | |
| CN101350335B (en) | Window-opening ball grid array semiconductor packaging piece and screen plate structure applied to same | |
| CN2770094Y (en) | Electric crystal structure capable of isolating electrical interference | |
| TWI275167B (en) | Package structure and manufacturing method thereof | |
| TWI401777B (en) | Die-stacked package structure with open substrate and packaging method thereof | |
| CN201032631Y (en) | Window type field grid array semiconductor packaging piece | |
| JP2006080316A (en) | Solid-state element device | |
| TWI241694B (en) | Packaging structure of image sensing chip and its packaging method | |
| TW533518B (en) | Substrate for carrying chip and semiconductor package having the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |