CN1747150A - Method for making separate programming virtual ground SONOS type memory - Google Patents

Abstract

The invention provides a method for manufacturing a separate programming virtual grounding SONOS type memory, which provides a semiconductor substrate, wherein the semiconductor substrate comprises a doped well positioned in the semiconductor substrate and a plurality of selection grid structures. Then, a plurality of sacrificial sidewall substructures are formed, and a doped region is formed in the semiconductor substrate between the selection gate structures. Then, the sacrificial spacer structures are removed, and a composite dielectric layer is formed on the surface of the selection gate structure and the semiconductor substrate. And finally, forming a plurality of character lines on the surface of the composite dielectric layer.

Description

Method for making separate programming virtual ground SONOS type memory

technical field

The invention relates to a method for making non-volatile memory, especially a method for making SPVGSONOS type memory.

Background technique

Non-volatile memory is widely used due to its characteristic that stored data will not be lost due to interruption of power supply. And according to the number of data bits stored in the unit storage unit, it can be divided into single-bit storage (single-bit storage) non-volatile memory, such as Nitride Read-Only-Memory (NROM for short), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memory or Silicon-Oxide-Nitride-Silicon-Oxide-Silicon Nitride-Oxide-Silicon, referred to as SONOS) memory, and dual-bit storage (dual-bit storage) non-volatile memory, such as split program virtual ground (split program virtual ground) SONOS type (abbreviated as SPVG SONOS) memory or split Programming virtual ground (split program virtual ground) MONOS type (abbreviated as SPVG MONOS) memory, wherein the cell storage unit of SPVG SONOS type memory and SPVG MONOS type memory can store two-bit information, so compared with the general single-bit Storing non-volatile memory can store a larger amount of information, and has gradually become the mainstream of non-volatile memory.

Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the schematic diagrams of a SPVG SONOS type memory 10, wherein Fig. 1 is a schematic diagram of the SPVG SONOS type memory 10 when programming (programming) operation, Fig. 2 is the SPVG SONOS type memory 10 It is a schematic diagram during an erasing operation, and in order to clearly illustrate the structure and operation principle of the SPVG SONOS type memory 10, only a single memory cell is shown in FIGS. 1 and 2 . As shown in Figure 1, the SPVG SONOS memory 10 is formed on a P-type doped well (P well) 12, which mainly includes a select gate (select gate) 14, and two N-type buried bits Buried bit lines are located in the P-type doped wells 12 on opposite sides of the select gate 14, serving as the source 16 and the drain 18 respectively. A gate insulation layer 20 is included between the selection gate 14 and the P-type doped well 12 , and a capping layer 22 is included above the selection gate 14 . In addition, the sidewall of the select gate 14 sequentially includes a bottom silicon oxide layer 24, a silicon nitride layer 26 and a top silicon oxide layer 28, wherein the silicon nitride layer 26 is used as a storage for trapping electrons or holes. medium. In addition, a word line 30 is included above the top silicon oxide layer 28 .

As shown in FIG. 1, the SPVG SONOS type memory 10 utilizes a source-side injection (source-side injection) mechanism when performing a programming operation, and its voltage operation is to apply a high positive voltage to the word line 30, such as 6 to 9V. Voltage, apply a low positive voltage such as 1V to the select gate 14, apply a positive voltage such as 4.5V to the source 18, and keep the voltage of the P-type doped well 12 and the drain 16 at 0V. Under this condition, the electrons passing through the channel below the select gate 14 will be trapped and confined in the silicon nitride layer 26 on one side of the source 18 (as shown by the arrow in the figure), In this way, it can be changed to different threshold voltages to achieve the function of storing data. In addition, electrons can be confined in the silicon nitride layer 26 on one side of the drain 16 through a similar reverse voltage operation to store another bit of data, forming a dual-bit storage memory.

As shown in FIG. 2, when the SPVG SONOS type memory 10 is performing an erase operation, a band-to-band hot hole injection (band-to-band hot hole injection) mechanism is used, and its voltage operation is to apply a high negative voltage to the word line 30. , such as the voltage of -6 to -9V, a positive voltage is applied to the source 18, such as 4.5V, the voltage of the selection gate 14 is lower than the initial voltage, and the P-type doped well 12 and the drain 16 The voltage is maintained at 0V. Under this condition, the holes in the P-type doped well 12 will be injected into the silicon nitride layer 26 on one side of the source electrode 18 and neutralize the electrons confined in the silicon nitride layer 26 to achieve the effect of erasing data. In addition, the electrons confined in the silicon nitride layer 26 on one side of the drain 16 can also be neutralized by a similar voltage operation.

Please refer to FIG. 3 to FIG. 6. FIG. 3 to FIG. 6 are schematic diagrams of conventional methods for fabricating SPVG SONOS-type memory. For convenience of description, only part of the memory cells are shown in the figure. As shown in Figure 3, at first, a semiconductor substrate 50 is provided, which includes a P-type doped well 52, a plurality of select gate structures 54 are formed on the surface of the P-type doped well 52, and each select gate structure 54 is formed from the following The top layer includes a gate insulating layer 56, a selection gate 58 and a top cover layer 60 in sequence, wherein the gate insulation layer 56 is formed by a silicon oxide layer formed by a thermal oxidation process or a deposition process, and the select gate 58 is a polysilicon layer, and the capping layer 60 is a silicon nitride layer or a metal silicide (polycide).

As shown in FIG. 4 , a bottom silicon oxide layer 64 , a silicon nitride layer 66 and a top silicon oxide layer 68 are sequentially formed on the surface of the semiconductor substrate 50 and the select gate structure 54 to form a silicon oxide-nitride Silicon oxide-silicon oxide (ONO) composite dielectric layer 62. Then, a silicon oxide layer 70 is deposited on the surface of the top silicon oxide layer 68 to form a subsequent sacrificial spacer.

Then, as shown in FIG. 5 , an etch-back process is performed to completely etch the silicon oxide layer 70 downward to form sacrificial sidewall substructures 72, and simultaneously etch through the composite dielectric layer 62 between the sacrificial sidewall substructures 72, Up to the surface of the semiconductor substrate 50 , an opening 74 is formed above the P-type doped well 52 between the selection gate structures 54 . Next, an ion implantation process is performed, and ion implantation is performed through each opening 74 to form a plurality of N-type doped regions 76 in the P-type doped well 52 for use as buried bit lines. Then an insulating layer (not shown) is deposited on the surface of the top silicon oxide layer 68 and the N-type doped regions 76, and an etch-back process is performed to form a blocking film (blocking) above each N-type doped region 76. film)78. As shown in FIG. 6, an etching process is performed to remove the sacrificial sidewall substructure 72, and finally a polysilicon layer 80 is deposited on the entire surface, and a word line 80 is defined by a lithography and etching process to complete the conventional SPVG SONOS type memory. make.

However, the conventional method for making SPVG SONOS type memory is to form the composite dielectric layer 62 first, and then perform the ion implantation process to form the N-type doped region 76, so not only must the N-type doped region 76 be formed before , remove the composite dielectric layer 62 between the sacrificial sidewall substructures 72 first, and also form a barrier film 78 before forming the word line 80, or form another oxide film after removing the sacrificial sidewall substructures 72 silicon layer, so as to prevent the word line 80 from forming a short circuit with the N-type doped region (buried bit line) 76, so that the SPVG SONOS memory cannot operate normally. Furthermore, even though the prior art has utilized the formation of the barrier film 78 to avoid short-circuit problems, the compound dielectric layer 62 above the N-type doped region 76 is incomplete, or due to factors such as residual etching stress and etching uniformity, etc. When the SPVG SONOS type memory is erased, the word line 80 and the embedded bit line need a larger voltage difference, or the phenomenon of leakage current is prone to occur, so it is very easy to cause the word line and the embedded bit line Tunneling and other situations occur on the element line, which leads to a decrease in the reliability of the SPVG SONOS memory.

Contents of the invention

Therefore, the main purpose of the present invention is to provide a method for manufacturing SPVG SONOS memory, so as to solve the insurmountable problems of conventional technologies and improve the reliability and yield of SPVG SONOS memory.

For reaching above-mentioned object, the present invention provides a kind of method of making SPVG SONOS type memory. Firstly, a semiconductor substrate is provided, the semiconductor substrate includes at least one doped well of the first conductivity type located in the semiconductor substrate, and a plurality of parallel and non-contact selection gate structures located on the surface of the semiconductor substrate. Next, a plurality of sacrificial spacers are formed on the opposite sidewalls of each of the selection gate structures, and an ion implantation process is performed using each of the sacrificial sidewall substructures as a shield, so as to form a plurality of sacrificial spacers on each of the selection gate structures. A second conductivity type doped region is respectively formed in the semiconductor substrate between the electrode structures. The sacrificial sidewall substructures are then removed, and a composite dielectric layer is formed on the surface of the semiconductor substrate and the select gate structure. Finally, a plurality of word lines which are not in contact and are perpendicular to each of the select gate structures are formed on the surface of the composite dielectric layer.

The present invention also provides a method for manufacturing a double-bit storage non-volatile memory, which includes: providing a semiconductor substrate, and a plurality of parallel and non-contact selection gate structures are provided on the surface of the semiconductor substrate; A sacrificial sidewall substructure is formed on the opposite sidewalls of the selection gate structure; an ion implantation process is performed, using each of the selection gate structures and each of the sacrificial sidewall substructures as a shield, so as to form a sacrificial sidewall substructure on each of the selection gates Forming a doped region in the semiconductor substrate between the structures; removing the sacrificial sidewall substructure; forming a composite dielectric layer on the semiconductor substrate and covering the surface of each selection gate structure; in the composite dielectric layer A plurality of word lines which are not in contact and are orthogonal to each of the select gate structures are formed on the surface.

Description of drawings

Fig. 1 and Fig. 2 are the schematic diagrams of a SPVG SONOS type memory;

Fig. 3 to Fig. 6 are the schematic diagram of the method for conventionally making SPVG SONOS type memory;

7 to 11 are schematic diagrams of a method for fabricating an SPVG SONOS memory according to a preferred embodiment of the present invention.

Symbol Description:

10 SPVG SONOS memory 12 P-type doped well

14 Select Gate 16 Drain

18 Source 20 Gate Insulator

22 Top Cover Layer 24 Bottom Silicon Oxide Layer

26 Silicon nitride layer 28 Top silicon oxide layer

30 Character Line 50 Semiconductor Substrate

52 P-type doped well 54 Select gate structure

56 Gate Insulator 58 Select Gate

60 Top Cover Layer 62 Composite Dielectric Layer

64 Bottom silicon oxide layer 66 Silicon nitride layer

68 Top Silicon Oxide Layer 70 Silicon Oxide Layer

72 sacrificial sidewall substructure 74 opening

76 N-type doped region 78 Barrier film

80 character line 100 semiconductor substrate

102 P-type doped well 104 Select gate structure

106 Gate insulating layer 108 Select gate

110 roof layer 112 sacrificial sidewall substructure

114 Opening 116 N-type doped region

118 composite dielectric layer 120 bottom silicon oxide layer

122 Silicon nitride layer 124 Top silicon oxide layer

126 character line

Detailed ways

Please refer to Figures 7 to 11, Figures 7 to 11 are schematic diagrams of a method for manufacturing SPVGSONOS type memory in a preferred embodiment of the present invention, wherein in order to clearly demonstrate the characteristics of the present invention, Figures 7 to 10 are schematic cross-sectional views of some memory cells , and Figure 11 is a schematic diagram of the appearance of the SPVG SONOS memory. As shown in FIG. 7, firstly a semiconductor substrate 100 is provided, and at least one P-type doped well 102 is formed in the semiconductor substrate 100, and then a plurality of select gate structures 104 are formed on the surface of the P-type doped well 102, and each The select gate structure 104 includes a gate insulating layer 106 , a select gate 108 and a top cap layer 110 in sequence from bottom to top. The gate insulating layer 106 is made of a silicon oxide layer formed by a thermal oxidation process or a deposition process, the select gate 108 is a polysilicon layer, and the top cover layer 110 is a silicon nitride layer or a metal Silicide (polycide), etc., in order to protect the select gate 108 and reduce the sheet resistance. In addition, the selection gate 108 can also be made of other conductive materials, such as using a metal layer to form an SPVG MONOS type memory.

As shown in FIG. 8, a silicon oxide layer (not shown), a silicon nitride layer (not shown) or a polysilicon layer (not shown) is deposited on the surface of the semiconductor substrate 100 and the select gate structure 104. , and use a back etch process to etch down the silicon oxide layer (not shown) comprehensively until the sacrificial sidewall substructure 112 is formed on the sidewall of each select gate structure 104, and at the same time exposes each adjacent The P-type doped well 102 between the sidewall substructures 112 is sacrificed to form an opening 114 . Subsequently, an ion implantation process is performed to form an N-type doped region 116 in the P-type doped well 102 through each opening 114 for use as a buried bit line. In addition, after the N-type doped region 116 is formed, a drive-in process can be performed to diffuse dopants in the N-type doped region 116 . It is worth noting that this embodiment uses the SPVG SONOS memory in the form of NMOS as an example to illustrate the method of the present invention, so the P-type doped well 102 and the N-type doped region 116 are formed in the semiconductor substrate 100. If the SPVG SONOS type memory to be fabricated due to the requirement or other design considerations is a PMOS type, it is only necessary to form N-type doped wells and P-type doped regions in the semiconductor substrate 100 with different dopants.

It should be noted that, in the present invention, a liner oxide (not shown) may also be formed first after the selection gate 108 is prepared. Then, a silicon oxide layer (not shown), a silicon nitride layer (not shown) or a polysilicon layer (not shown) is deposited on the surface of the semiconductor substrate 100 and the select gate structure 104, and the liner oxide layer is used to (not shown) as an etch-stop layer in the etch-back process, a sacrificial sidewall substructure 112 is formed. As for the material of the sacrificial sidewall substructure 112 , depending on the presence or absence of the lining oxide layer (not shown), the composition of the cap layer 110 and the semiconductor substrate 100 , a combination with a relatively high etching selectivity can be selected. In addition, the liner oxide layer can also be used as a sacrificial layer for the ion implantation process of the N-type doped region 116 to protect the lattice structure on the surface of the N-type doped region 116 .

As shown in FIG. 9 , the sacrificial sidewall substructures 112 on the sidewalls of each selection gate structure 104 are subsequently removed, and a complex is formed on the surface of the P-type doped well 102, the selection gate structure 104, and the surface of the N-type doped region 116. The dielectric layer 118 serves as a storage medium for electrons. Wherein in this embodiment, the composite dielectric layer 118 is a silicon monoxide-silicon nitride-silicon oxide (ONO) dielectric layer, which includes a bottom silicon oxide layer 120, a silicon nitride layer 122 and an upper silicon oxide layer 124. However, other composite dielectric layers commonly used as electron storage media, such as silicon nitride-silicon oxide (NO) dielectric layer, silicon oxide-silicon nitride (ON) dielectric layer, SiO ₂ /Ta ₂ O ₅ , SiO ₂ /Ta ₂ O ₅ /SiO ₂ , SiO ₂ /SrTiO ₃ , SiO ₂ /BaSrTiO ₂ , SiO ₂ /SrTiO ₃ /SiO ₂ , SiO ₂ /SrTiO ₃ /BaSrTiO ₂ , SiO ₂ /Hf ₂ O ₅ /SiO ₂ etc., can be applied here as needed.

Finally, as shown in FIG. 10 and FIG. 11, a conductive layer (not shown), such as a polysilicon layer, a metal silicide or a metal layer, is deposited on the surface of the composite dielectric layer 118, and a lithography and etching process is used. A plurality of word lines 126 parallel to and orthogonal to the selection gate structure 104 are defined to complete the fabrication of the SPVG SONOS memory of the present invention.

As can be seen from the above, the method for manufacturing the SPVG SONOS type memory of the present invention is to use the sacrificial sidewall substructure to form a doped region in the semiconductor substrate, and then form a composite dielectric layer on the surface of the semiconductor substrate and the select gate structure. Therefore, the composite dielectric layer will not be damaged and has good electron trapping ability, and can effectively avoid the short circuit between the word line and the embedded bit line. In contrast, the conventional method of manufacturing SPVG SONOS memory is to form the doped region after the composite dielectric layer is formed; therefore, openings must be formed in the composite dielectric layer first, and after the doped region is formed, then A blocking film is used to seal the opening after the doped region is formed, so as to avoid the short circuit between the word line and the buried bit line. In addition, since the structure of the composite dielectric layer is damaged when the opening is formed, it will lead to disadvantages such as difficult control of the programming voltage or erasing voltage of the SPVG SONOS memory, which seriously affects the reliability.

Claims (16)

1. A method of making separate programming virtual ground SONOS type memory, which comprises: A semiconductor substrate is provided, which includes at least one doped well of the first conductivity type located in the semiconductor substrate, and a plurality of parallel and non-contacting selection gate structures located on the surface of the doped well of the first conductivity type; forming a sacrificial sidewall substructure on opposite sidewalls of each of the select gate structures; Performing an ion implantation process, using each of the selection gate structures and each of the sacrificial sidewall substructures as a shield, respectively forming a second conductivity type doping well in the first conductivity type doping well between each of the selection gate structures. Miscellaneous area; removing the sacrificial sidewall substructure; forming a composite dielectric layer on the semiconductor substrate and covering the surface of each selection gate structure; A plurality of word lines which are not in contact and are perpendicular to each of the selection gate structures are formed on the surface of the composite dielectric layer. 2 . The method for fabricating a separate programming virtual ground SONOS memory according to claim 1 , wherein each of the select gate structures sequentially includes a gate insulating layer, a polysilicon layer and a top cover layer from bottom to top. 3. The method for fabricating a separate programming virtual ground SONOS memory according to claim 1, wherein the doped region of the second conductivity type is used as a buried bit line. 4. The method for fabricating a separate programming virtual ground SONOS memory according to claim 1, wherein the composite dielectric layer is a silicon monoxide-silicon nitride-silicon oxide dielectric layer. 5. The method for fabricating a separate programming virtual ground SONOS memory according to claim 1, wherein the doped well of the first conductivity type is a P-type doped well. 6 . The method for fabricating a separate programming virtual ground SONOS memory according to claim 5 , wherein each doped region of the second conductivity type is an N-type doped region. 7. A method for making a double-bit storage non-volatile memory, comprising: A semiconductor substrate is provided, and the surface of the semiconductor substrate is additionally provided with a plurality of parallel and non-contact selection gate structures; forming a sacrificial sidewall substructure on opposite sidewalls of each of the select gate structures; performing an ion implantation process, using each of the select gate structures and each of the sacrificial sidewall substructures as a shield to form a doped region in the semiconductor substrate between each of the select gate structures; removing the sacrificial sidewall substructure; forming a composite dielectric layer on the semiconductor substrate and covering the surface of each selection gate structure; A plurality of word lines which are not in contact and are perpendicular to each of the selection gate structures are formed on the surface of the composite dielectric layer. 8 . The method for manufacturing a dual-bit storage non-volatile memory according to claim 7 , wherein each of the select gate structures sequentially includes a gate insulating layer and a conductive layer from bottom to top. 9. The method of manufacturing a dual-bit storage non-volatile memory according to claim 8, wherein the conductive layer is a polysilicon layer, and the dual-bit storage non-volatile memory is a separate programming virtual ground SONOS type memory. 10. The method of manufacturing a dual-bit storage non-volatile memory according to claim 8, wherein the conductive layer is a metal layer, and the dual-bit storage non-volatile memory is a separate programming virtual ground MONOS type memory. 11. The method for manufacturing a dual-bit storage non-volatile memory according to claim 7, wherein each of the select gate structures further comprises a capping layer disposed above the conductive layer. 12. The method for manufacturing a dual-bit storage non-volatile memory according to claim 7, wherein the surface of the semiconductor substrate further comprises a liner oxide layer disposed on the semiconductor substrate and covering the surface of each of the select gate structures. 13. The method for manufacturing a dual-bit storage non-volatile memory according to claim 7, wherein the doped region is used as a buried bit line. 14. The method for manufacturing a dual-bit storage non-volatile memory according to claim 7, wherein the composite dielectric layer is a silicon monoxide-silicon nitride-silicon oxide dielectric layer. 15. The method for manufacturing a dual-bit storage non-volatile memory according to claim 7, wherein the semiconductor substrate further includes at least one doped well, and the select gate structures are all arranged on the surface of the doped well . 16. The method of manufacturing a dual-bit storage non-volatile memory according to claim 15, wherein the doped well is a P-type doped well, and each of the doped regions of the second conductivity type is an N type doped region.

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