CN1745468B - Large-area nano-enabled macroelectronic substrate and its application - Google Patents

Abstract

A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Description

Large-area nano-enabled macroelectronic substrate and its application

technical field

The invention relates to a semiconductor device, in particular to the use of a nanowire thin film in the semiconductor device.

Background technique

Attention in industry is the development of low-cost electronics, especially the development of low-cost, large-area electronic devices. The acquisition of such large-area electronics could be a revolution of sorts in technological fields from civilian to military. Examples of applications for this device include drive circuits for active matrix liquid crystal displays (LCD) and other types of matrix displays, large libraries, credit cards, for expensive RFID and inventory tags, security screens/surveillance or highway Traffic surveillance systems, large area sensor arrays, etc.

Electronics is moving toward two extremes when it comes to physical size. According to Moore's law, the rapid miniaturization of microelectronics has led to an increase in computing power while reducing cost. At the same time, developments are being made in the field of macroelectronics, in which electronic devices are integrated on large-area substrates (eg, having dimensions measured in square meters). At present, Macroelectronics is mainly based on amorphous silicon (a-Si) or polycrystalline silicon (p-Si) thin film transistors (TFT) on glass, and finds important applications in various fields, including flat panel displays (FPD), solar cells , an image sensor array and a digital x-ray imager.

However, current techniques are limited in application. For example, the use of plastics as substrates for macroelectronics has attracted increasing attention because of various advantageous features, including flexibility, impact resistance, low weight, and low cost. However, fabricating high-performance TFTs on plastic is difficult because the process steps must be performed below the glass transition temperature of the plastic. Much effort has been devoted to research on new materials (such as organic and organic-inorganic hybrids) or new fabrication strategies suitable for TFTs on plastics, but with limited results. Organic TFTs have the potential to be used in roll-to-roll fabrication processes on plastic substrates, but only have a limited carrier mobility of about 1 cm ² /V·s (square centimeter per volt·second). Limitations caused by material and/or substrate processing temperature (especially on plastics) lead to low device performance, limiting the device to low frequency applications. Therefore, applications requiring even modest computing, control or communication functions cannot be addressed by existing TFT technology.

Industrial semiconducting nanowires (NWs) and single-walled carbon nanotubes can be used to fabricate nanoscale field effects with electronic properties comparable to, and in some cases exceeding, those of the highest quality single crystal materials Transistors (FETs). In particular, a carrier mobility of 300 cm ² /V s is required for p-SiNWs, 2000–4000 cm ² /V s for n-Indium InPNWs, and up to 20000 cm ² /V s for single-walled carbon nanotubes. s carrier mobility. These nanoFETs extend Moore's law towards the molecular level. However, they are currently struggling to realize product-scale nanoelectronics because of the complexity and scale limitations of the device fabrication process.

Thus, there is a need for higher performance conductive or semiconductive materials and devices, as well as methods and systems for fabricating low cost, high performance electronic devices and components.

Furthermore, there is a need for a high performance TFT that can be applied to plastics and other substrates that require low processing temperatures.

There is also a need for a more advanced fabrication-scale method of fabricating nanoscale semiconductor devices than can be used as high-performance TFTs.

Contents of the invention

A method, system, and apparatus for an electronic substrate having one or more semiconductor devices formed thereon are presented. Thin-film transistors formed of semiconductor nanowires on a substrate. The thin film of nanowires is formed with sufficient nanowire density to achieve operable current values. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed on the semiconductor device regions, thereby providing electrical connections to the plurality of semiconductor devices.

In the first aspect of the present invention, a semiconductor device is formed. A plurality of nanowires are deposited on the substrate as a thin film. First and second electrical contacts are formed on the substrate. At least one nanowire couples the first electrical contact to the second electrical contact. In the context of the present invention, the deposited nanowires may be semiconductive, magnetic, ferroelectric, pyroelectric, piezoelectric, metallized or transition metal oxide nanowires.

In another aspect of the invention, a thin film is fabricated for use in one or more semiconductor devices. A first plurality of p-doped nanowires is formed. A second plurality of n-doped nanowires is formed. A first plurality of nanowires and a second plurality of nanowires are deposited on a substrate to form a nanowire film comprising n-doped and p-doped nanowires. Nanowire thin films exhibit the characteristics of n-doped and p-doped nanowires.

In another aspect of the invention, nanowire heterostructures are combined to form electronic devices. A plurality of nanowires is formed such that each nanowire has at least one first portion doped with a first dopant and at least one second portion doped with a second dopant along its long axis. The spacing between successive junctions of each nanowire between the first and second portions is substantially equal to the first distance. A pair of electrical contacts are formed on the substrate. The distance between the electrical contacts is approximately equal to the first distance. A plurality of nanowires is deposited onto a substrate. At least one nanowire of the plurality of nanowires couples the first electrical contact to the second electrical contact.

In another solution of the present invention, a light-emitting thin film is fabricated by combining the nano-miscellaneous structure. At least one light emitting semiconductor material. A plurality of nanowires are formed from the selected at least one light emitting semiconductor material. Each nanowire is doped such that each nanowire includes at least one P-N junction. A plurality of nanowires is deposited onto a substrate.

In another aspect of the invention, the nanowires are arranged on a target surface. The first surface of the fluid mask closely fits the target surface such that at least one channel formed in the first surface of the fluid mask covers a portion of the target surface. A liquid containing a plurality of nanowires flows through at least one channel. Nanowires contained in a liquid flowing through the at least one channel are allowed to be disposed on a portion of the target surface covered by the at least one channel.

In yet another aspect of the invention, the nanowires are applied to the target surface. The solution source provides the nano solution. Nanosolutions include liquids containing a plurality of nanowires. A nozzle is coupled to a solution source. The nozzle has at least one outlet. The nozzle directs the nanosolution through the output port and onto the target surface. The nanowires of the nanosolution are guided onto the target surface so as to be aligned substantially parallel to each other on said target surface, or randomly oriented to each other.

In yet another aspect of the present invention, conductive nanowires are designed with high electron mobility. Select a semiconductor material. The maximum diameter of a nanowire formed from a selected semiconductor material that provides a substantial limit of electrons is determined. In the example scenario, the diameter is determined by calculating the maximum diameter as follows:

in:

h = Planck's constant = 4.14×10 ^-15 eV-sec;

m _eff = effective mass of the selected semiconductor material

N = predetermined coefficient

k _b = Boltzmann's constant = 8.62 x 10 ^-15 eV°K; and

T = working temperature;

where at room temperature, k _b T = .0259eV.

In another aspect of the invention, the nanowires are constructed so as to use electrons as conduction carriers such that phonon scattering of the electrons in the nanowires is substantially reduced or completely eliminated. In one approach, the nanowires are doped with an n-type dopant material, thereby being configured to use electrons as conduction carriers. In another approach, the nanowires are doped with a p-type dopant material. By applying a sufficient bias voltage to the nanowire film, the nanowires are made to operate in reverse mode, whereby electrons serve as conduction carriers.

In yet another aspect of the invention, nanowires are fabricated with reduced surface scattering. Select a semiconductor material. A plurality of nanowires are formed from the selected semiconductor material. A circumferential surface of each nanowire of the plurality of nanowires is coated with an insulating layer.

In yet another aspect of the invention, nanowires are fabricated with reduced surface scattering. Select a semiconductor material. A plurality of nanowires are formed from the selected semiconductor material. Each nanowire of the plurality of nanowires is doped such that each nanowire includes a core-shell material. The shell is the doped outer layer of each nanowire that surrounds the respective core. The charge carriers of each nanowire are thereby substantially confined to the core during operation.

In another aspect, the present invention provides a thin film transistor using nanowires, nanorods, or nanoribbons and provides fabrication scaled methods for fabricating such transistors on various substrates. In particular, a completely new concept of macroelectronics has been developed by using oriented semiconductor nanowire or nanoribbon films to fabricate thin film transistors (TFTs) with wire/ribbon axes parallel to each other. These new TFTs have a conductive channel formed by parallel multiple single-crystal nanowires (like log bridges) or single-crystal nanoribbons that is compatible with source-to-drain for high carrier mobility. All paths intersect.

In yet another aspect of the present invention, a method of NW-TFT fabrication is provided, wherein a high-temperature active semiconductor material synthesis process (for example, for forming nanowires or nanobelts) is performed before the active semiconductor material is applied to the device substrate. ). Afterwards, the formed NW-TFT is applied to the device substrate via a solution assembly process, providing a general technique for applying any semiconductor material to any substrate type including plastic substrates.

According to the solution of the present invention, p-channel and n-channel TFTs can be formed. In the example scheme, a compensated inverter assembled from p-channel and n-channel TFTs using a combination of nanowires and nanoribbons is presented here.

According to other solutions of the present invention, a system and method for further improving performance are introduced here. For example, the inventive scheme allows NW-TFT performance to match or exceed that of bulk single crystal materials. In the example scheme, by fabricating novel core-shell NW structures and fully exploiting quantum electronic effects at reduced dimensions, the carrier mobility can be enhanced beyond that of bulk single crystal materials. Furthermore, the scheme of fabricating NW-TFTs according to the scheme of the present invention represents a general platform for various macroelectronic applications. In the inventive scheme, NWs made of optically active materials with various bandgaps are used to fabricate high-performance, optically active films for multicolor solid-state light-emitting diode (LED) displays. Furthermore, according to the inventive scheme, NW-TFTs can be deposited from solution onto large area substrates, for example using low-cost, low-temperature processing, including microcontact or inkjet printing techniques.

In another aspect of the invention, electronic devices may be formed using structures comprising a plurality of nanowire film layers. A first plurality of nanowires is deposited on the substrate to form a first nanofilm layer. A second plurality of nanowires is deposited on the first nanofilm layer, thereby forming a second nanofilm layer. A junction, such as a p-n junction, is thus formed at the intersection between the nanowires of the first and second thin film layers. Contacts can be formed to form electronic devices based on the properties of the junction. The nanowires of the first thin film layer are preferably aligned parallel to each other, and the nanowires of the second thin film layer are preferably aligned parallel to each other. However, in an alternative, the nanowires of the first and/or second film layer are randomly oriented.

In another aspect of the invention, an electronic device is formed that includes a hybrid nano-single crystal semiconductor structure. Formation of single crystal semiconductor strips/thin films. A plurality of nanowires are deposited on top of the strips. A junction, such as a p-n junction, is formed at the intersection between the nanowire and the single crystal semiconductor strip. Contacts can be formed to build electronic devices based on the properties of these junctions. The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but may also be randomly oriented.

In yet another aspect of the invention, an electronic device is formed that includes a hybrid nano-amorphous/polycrystalline semiconductor structure. An amorphous or polycrystalline semiconductor film is deposited on a substrate. A plurality of nanowires are deposited on the thin film pattern. A junction, such as a p-n junction, is formed at the intersection between the nanowire and the amorphous/polycrystalline semiconductor film pattern. Based on the properties of these junctions contacts can be formed to form electronic devices. The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but may also be randomly oriented.

In yet another aspect of the present invention, semiconductor nanowires emitting red, green, and blue light in predetermined ratios may be mixed in the solution. The line mix is flowed over single crystalline, amorphous or polycrystalline semiconductor strips/films. Contacts are formed to fabricate light-emitting electronic devices. Depending on the mixture of luminescent nanowires, light of any color, including white light, can be emitted by light-emitting electronics.

Thus, nanowires, nanorods, nanoribbons, and nanotube films can realize various new capabilities according to the scheme of the present invention. Among the scenarios, these include: moving microelectronics from single crystal substrates to glass and plastic substrates; integrating macroelectronics, microelectronics and nanoelectronics at the device level; and integrating different semiconductor materials on one substrate . These aspects of the invention impact a wide range of existing applications from flat panel displays to image sensor arrays and enable a whole new range of versatile flexible, wear-resistant, disposable electronics for computational storage and communication .

These and other objects, advantages and features will be better understood from the following detailed description of the invention.

Description of drawings

The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the invention and, together with the description, further serve to explain the principles of the invention and to enable those skilled in the art to make and use the invention.

Figure 1 shows a schematic diagram of a portion of a nanowire film according to an exemplary embodiment of the present invention.

FIG. 2 illustrates a semiconductor device including a nanowire film according to an exemplary embodiment of the present invention.

3A-3D illustrate nanowires doped according to various exemplary embodiments of the invention.

4A and 4B illustrate examples of semiconductor devices doped according to exemplary doping embodiments of the present invention.

FIG. 5 shows a flowchart providing exemplary steps for fabricating a plurality of semiconductor devices in accordance with an embodiment of the present invention.

6A-6F represent various stages in the fabrication of a substrate for having a plurality of semiconductor devices thereon in accordance with an embodiment of the present invention.

FIG. 7 shows a flowchart providing exemplary steps for fabricating an electronic device comprising a nanowire thin film of the present invention, according to an embodiment of the present invention.

8A shows a close-up view of an exemplary portion of a nanowire film comprising a homogeneous mixture of n-doped nanowires and p-doped nanowires, according to an embodiment of the invention.

Figure 8B shows an exemplary portion of a nanowire film including n-doped nanowires and p-doped nanowires.

Figure 8C shows a thin film of nanowires including n-doped nanowires and p-doped nanowires.

Figure 9 shows a flowchart providing example steps for fabricating the nanowire films of the present invention, according to an embodiment of the present invention.

Figure 10 shows a nanowire as a nanowire heterostructure according to an exemplary embodiment of the present invention.

FIG. 11A shows a typical two-terminal electronic device including a plurality of nanowires according to an embodiment of the present invention.

Figure 1 IB shows an example of a p-n-p transistor incorporating a nanowire heterostructure.

Figure 12 shows a flowchart providing example steps for fabricating electronic devices incorporating nanowire heterostructures, according to an embodiment of the present invention.

Figure 13A shows a discrete pixel or light source with a pair of electrodes, a first electrical contact and a second electrical contact, according to an embodiment of the invention.

Figure 13B shows a column of discrete pixels or light sources each similar to a pixel or light source according to an embodiment of the invention.

Figure 13C illustrates a large area light source including multiple light source columns in accordance with an embodiment of the present invention.

FIG. 14 shows a flowchart providing exemplary steps for fabricating a light-emitting device incorporating a light-emitting nanowire heterostructure, according to an embodiment of the present invention.

15A and 15B show bottom and cross-sectional views of an exemplary fluid mask according to an embodiment of the present invention.

Figure 16 illustrates a nanowire positioning system incorporating a fluid mask according to an exemplary embodiment of the present invention.

17A and 17B show plan and cross-sectional views of nanowire flow through a fluid mask according to an example embodiment of the present invention.

Figure 18A shows an exemplary semiconductor wafer mated with a fluid mask in accordance with an embodiment of the present invention.

Figure 18B shows a portion of the surface of the wafer of Figure 18A having nanowires disposed thereon as a result of the workings of the present invention.

Figure 18C shows an array of integrated circuits formed on a wafer with nanowires disposed thereon as a result of the work of the present invention.

FIG. 19A shows an integrated circuit that may be an example of one of the integrated circuits of the wafer shown in FIG. 18C according to an embodiment of the present invention.

19B shows a close-up view of a portion of the integrated circuit of FIG. 19A showing details of exemplary conductive traces in accordance with an embodiment of the invention.

Figure 19C shows nanowires deposited on the integrated circuit portion of Figure 19B by manipulating an exemplary fluid mask of the present invention.

FIG. 19D shows an integrated circuit that may be an example of one of the integrated circuits of the wafer shown in FIG. 18C according to an embodiment of the present invention.

19E shows a close-up view of a portion of the integrated circuit of FIG. 19D showing details of exemplary conductive traces in accordance with an embodiment of the invention.

Figure 19F shows nanowires deposited on the integrated circuit portion of Figure 19E by manipulating an exemplary fluid mask of the present invention.

Figure 20A shows the curves related to Figures 19A-C.

Figure 20B shows the curves related to Figures 19D-F.

21 shows a flowchart providing example steps for disposing nanowires on a target surface using a fluid mask in accordance with an embodiment of the present invention.

Figure 22 shows a block diagram of an exemplary nanowire jet application system in accordance with an embodiment of the present invention.

Figure 23 shows a detailed view of a nozzle outputting a stream of nanowires onto an exemplary target surface in accordance with an embodiment of the invention.

Figures 24 and 25 represent plan views of a target surface with a plurality of nanowires disposed thereon as a result of the operation of the present invention.

26 represents a plan view of a target surface with multiple electrical contacts formed thereon in electrical contact with nanowires according to an embodiment of the present invention.

Figure 27 shows a flowchart providing example steps for disposing nanowires on a target surface using jetting techniques, according to an example embodiment of the present invention.

FIG. 28 represents a graph providing a relationship between a maximum allowable diameter and an effective mass m _eff for a semiconductor material according to an embodiment of the present invention.

Figure 29 shows a table listing information on various exemplary semiconductor materials.

30 shows a flowchart providing example steps for designing conductive nanowires with high electron mobility according to an embodiment of the present invention.

Figure 31 shows a table listing information about example III-V semiconductor type materials.

32 and 33 show flowcharts providing example steps for fabricating nanowires with reduced surface scattering according to example embodiments of the present invention.

Figure 34A is a schematic diagram of an amorphous or polycrystalline SiTFT.

34B is a schematic diagram of a nanowire TFT according to an embodiment of the present invention.

34C is a schematic diagram of a nanoribbon TFT according to an embodiment of the present invention.

35A is a flowchart of a method for NW-TFT fabrication according to an embodiment of the present invention.

Figure 35B is an optical micrograph of a NW thin film according to an embodiment of the present invention.

Figure 35C is a schematic diagram of a NW-TFT with gold electrodes according to an embodiment of the present invention.

Figure 35D is a photophotograph of a NW-TFT with a parallel array of NWs bridged from source to drain according to an embodiment of the present invention.

Fig. 36A is a graph showing the relationship between typical drain current (I _DS ) and drain-source bias voltage (V _DS ) under different gate voltages (V _GS ) in each stage of 1V of NW-TFT according to an embodiment of the present invention of the graph.

FIG. 36B is a graph showing I _DS versus V _GS for a NW-TFT according to an embodiment of the present invention.

36C is a graph representing a histogram of threshold voltage distributions for NW-TFTs according to an embodiment of the present invention.

FIG. 36D is a graph showing linear scaling versus drain current when the device is turned on (V _gs =10V) for a NW-TFT according to an embodiment of the present invention.

37A is a schematic diagram of an NW-TFT on a plastic substrate according to an embodiment of the present invention.

Figure 37B is a schematic diagram of several NW-TFTs on a plastic substrate according to an embodiment of the present invention.

Fig. 37C shows the relationship between the drain current (I _DS ) and the drain-source bias voltage (V _DS ) under different gate voltages (V _GS ) in each stage of 1V of the NW-TFT according to an embodiment of the present invention schematic diagram.

37D is a schematic diagram showing the transfer characteristics of the same NW-TFT before and after slight flexing of the plastic substrate according to an embodiment of the present invention.

38A is a schematic diagram of a NW-TFT on a plastic substrate with an electrolyte gate according to an embodiment of the present invention.

38B is a graph of the I _DS -V _DS relationship as a function of various electrolyte gate voltages for a NW-TFT on a plastic substrate according to an embodiment of the present invention.

38C is a graph of the I _DS -V _GS relationship for a V _DS of 10 mV for a NW-TFT on a plastic substrate with an electrolyte gate according to an embodiment of the present invention.

39A is a schematic diagram of a CdS nanoribbon TFT according to an embodiment of the present invention.

39B is a graph of the I _DS -V _DS relationship as a function of various gate voltages for a CdS nanoribbon TFT according to an embodiment of the present invention.

39C is a graph of the I _DS -V _GS relationship for a V _DS of 1 V for a CdS nanoribbon TFT according to an embodiment of the present invention.

FIG. 40 is a schematic diagram of a compensated inverter fabricated using a p-channel NW-TFT with gain characteristics and an n-channel CdS nanoribbon TFT according to an embodiment of the present invention.

Figure 41A shows a scanning electron micrograph image of synthesized silicon nanowires according to an exemplary embodiment of the present invention.

Figure 41B shows a lattice decomposition transmission electron microscopy image of an individual silicon nanowire according to an exemplary embodiment of the present invention.

Figure 42 shows a flow diagram of a process for synthesizing and realizing a high mobility nanowire thin film transistor according to an exemplary embodiment of the present invention.

Figure 43 shows a silicon nanowire core-shell structure with a single crystal core and a dielectric overcoat, according to an exemplary embodiment of the present invention.

44A-C show schematics of thin film transistors (TFTs) fabricated from amorphous silicon, polysilicon, and aligned nanowire films.

Figure 45 shows a schematic diagram of a fluidic unit for aligning nanowires over a large area according to an embodiment of the present invention.

Figure 46 shows a schematic diagram of aligning nanowires over a large area using a Langmuir-Blodgett film according to an exemplary embodiment of the present invention.

Figure 47 shows plan and perspective views of a nanowire field effect transistor according to an exemplary embodiment of the present invention.

48A and 48B show perspective views of partially gated nanowire thin film transistors in accordance with embodiments of the present invention.

The present invention is described below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. In addition, the leftmost digit(s) of a reference number indicates the drawing in which the reference number first appears.

Detailed ways

introduction

It should be understood that the particular embodiments shown and described herein are examples of the invention and do not limit the scope of the invention. Indeed, conventional electronics, fabrication, semiconductor devices and other functional aspects of nanowire (NW), nanorod, nanotube, and nanoribbon technologies and systems (and the individual working elements of the systems) may not be detailed here for the sake of brevity. element). Furthermore, for purposes of clarity, the present invention is frequently described herein as applicable to nanowire and semiconductor transistor devices. Also, while the number of nanowires and the spacing of the nanowires are provided for the particular embodiments discussed, these implementations are not limiting and wide ranges of nanowire numbers and spacing can be used. It should be understood that although frequently referenced to nanowires, the techniques described herein are also applicable to nanorods, nanotubes, and nanoribbons. It should also be understood that the fabrication techniques described herein may be used to fabricate any type of semiconductor device and other electronic component types. Furthermore, these techniques should be suitable for use in electronic systems, optical systems, consumer electronics, industrial electronics, wireless system space applications, or any other application.

As used herein, the term "nanowire" generally refers to any elongated conductive or semiconductive material (or other materials described herein) comprising at least one cross-sectional dimension of less than 500 nm, preferably less than 100 nm, and having a diameter greater than 10. An aspect ratio (length:width) preferably greater than 50, more preferably greater than 100. Examples of such nanowires include semiconducting nanowires, carbon nanotubes and other elongated conductive or semiconductive structures of similar dimensions as described in Nos. WO02/17362, WO02/48701 and 01/03208.

As used herein, the term "nanorod" generally refers to any elongated conductive or semiconductive material (or other material described herein) that is similar to a nanowire but has an aspect ratio (length:width) smaller than that of a nanowire . It should be noted that two or more nanorods can be coupled together along their longitudinal axes such that the coupled nanorods span all paths between the electrodes. Alternatively, two or more nanorods may be substantially aligned substantially along their longitudinal axes, but not coupled together such that there is a small gap between the ends of the two or more nanorods. In this case, electrons can flow from one nanorod to another by hopping from one nanorod to another across a small gap. Two or more nanorods may be substantially aligned such that they form paths for electrons to travel between the electrodes.

While the example embodiments described herein primarily employ CdS and Si, other types of materials for nanowires and nanoribbons can be used, including semiconducting nanowires or nanoribbons, including semiconductor materials selected from the group consisting of, for example, Si , Ge, Sn, Se, Te, B, C (including diamond), P, BC, BP (BP6), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/ BP/BAs, AlN/AlPAlAs/AlAsSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlPAlAs/AlAsSb, GaN/GaP/GaAs/GaSb, InN/InP/ InAs/InSb, ZnO/ZnS/ZnSe/ZnTe/CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN ₂ , CaCN ₂ , ZnGeP ₂ , CdSAs ₂ , ZnSnSb ₂ , CuGeP ₃ , CuSi ₂ P ₃ , (Cu, Ag)(Al , Ga, In, Tl, Fe)(S, Se, Te) ₂ , Si ₃ N ₄ , GeN ₄ , Al ₂ O ₃ , (Al, Ga, In)2(S, Se, Te) ₃ , Al2CO and A suitable combination of two or more of these semiconductors.

In some aspects, the semiconductor may include a dopant selected from: a p-type dopant selected from Group III of the Periodic Table of the Elements; an n-type dopant selected from Group V of the Periodic Table of the Elements; , the p-type dopant of Al and In; the n-type dopant selected from P, As and Sb; the p-type dopant selected from group II in the periodic table; the group selected from Mg, Zn, Cd and Hg p-type dopant; p-type dopant selected from group IV of the periodic table; p-type dopant selected from C and Si; or n-type selected from Si, Ge, Sn, S, Se and Te dopant.

Additionally, the nanowires or nanoribbons may include carbon nanotubes or nanotubes formed from conductive or semiconductive organic polymer materials such as pentacene and transition metal oxides.

Thus, although the term "nanowire" is used for descriptive purposes throughout the description herein, the description herein also includes nanotubes (eg, nanowire-like structures having coaxially formed hollow tubes). Nanotubes can be formed as combinations/films of nanotubes, as described herein for nanowires, alone or in combination with nanowires, thereby providing the properties and advantages described herein.

Furthermore, it should be noted that the nanowire films of the present invention may be "heterogeneous" films that incorporate semiconducting nanowires and/or nanotubes, and/or nanorods, and/or nanobelts, and/or different groups of Any combination of points and/or structural features. For example, "heterogeneous membranes" may include nanowires/nanotubes, and nanotubes of varying diameters and lengths, and/or "heterostructures" of nanotubes with varying properties.

In the context of the present invention, although the focus of the detailed description relates to the use of nanowire, nanorod, nanotube or nanoribbon films on plastic substrates, the substrate to which these nanostructures are to be affixed may comprise other materials, including but Not limited to "homogeneous substrates, such as wafers of solid material, such as silicon, glass, quartz, polymers, etc.; large rigid plates of solid material, such as glass, quartz, plastics, such as polycarbonate, etc., or may include additional elements, For example structurally, componently, etc. Flexible substrates such as plastic rolls such as polyolefins, amides and others, transparent substrates or combinations of these features may also be used. For example, the substrate may include as the final desired device Other electrical or structural elements that are part of the .Specific examples of such elements include electronic circuit elements such as electrical contacts, other wires or conductive paths, including nanowires or other nanometer-sized conductive elements, optical and/or optoelectronic elements (e.g., lasers , LEDs, etc.), and structural elements (eg, microcantilevers, recesses, columns, etc.).

By substantially "aligned" or "oriented" it is meant that the longitudinal axes of a majority of the nanowires in a mass or population of nanowires are oriented within 30 degrees of a single direction. Although a majority of nanowires is considered to be greater than 50% of the nanowire population, in various embodiments, 60%, 75%, 80%, 90%, or other percentages of nanowires may be considered a majority so oriented. In some preferred aspects, a majority of the nanowires are oriented within 10 degrees of a predetermined direction. In additional embodiments, a majority of the nanowires can be oriented within other amounts or ranges of degrees of a predetermined orientation, including random orientations and isotropic orientations.

It should be understood that the spatial expressions used herein (e.g., "above", "below", "above", "below", "top", "bottom", etc.) Spatially arranged in any orientation or manner.

The materials used for the nanowires described here also possess the inherent mechanical flexibility of high-mobility semiconductor materials, allowing the practical fabrication of flexible high-performance electronic devices. Due to the extremely small diameter and large aspect ratio (greater than 1000 in some embodiments), nanowires have excellent mechanical flexibility and strength. Individual nanowires can be easily bent with a radius of curvature r < 10 μm before breaking. Due to the alignment of each individual nanowire on these high-density substrates in the same direction, but the physical correlation of the surrounding wires, this flexibility is maintained in the nanowire films of the present invention, including dense, inorganic and aligned nanowires Thin film (DION film). Even without bending the individual nanowires within the device, the fact that each nanowire is only 100 μm long allows a macroscopic r<<1 mm.

Examples of Nanowire Films

The present invention aims to provide the use of nanowires in systems and devices in order to improve the performance of the systems and devices. For example, the present invention provides for the use of nanowires in semiconductor devices. According to the present invention, a plurality of nanowires are formed into a high mobility film. The nanowire film is used in electronic devices, thereby enhancing the performance and manufacturability of the devices.

Figure 1 shows a close up view of a nanowire film 100 according to an example embodiment of the invention. The semiconductor nanowire film 100 can be used to replace amorphous silicon or organic films in conventional electronic devices, thereby achieving improved device behavior while allowing for a straight-forward and inexpensive manufacturing process. Despite the use of thin films of nanowires, the present invention is particularly well suited for fabricating high performance, low cost devices on large and flexible substrates.

It should be noted that nanowire films 100 as described herein can be formed over a wide range of possible surface areas. For example, nanowire films of the present invention can be formed with functional areas greater than 1 mm ² , greater than 1 cm 2 , greater than 10 cm ² , greater than 1 m ² , and even larger or smaller areas.

As shown in FIG. 1, nanowire film 100 includes a plurality of individual nanowires arranged closely together. The nanowire thin film 100 may have a thickness variation equal to or greater than that of a single nanowire. In the example of FIG. 1 , the nanowires of nanowire film 100 are aligned such that their long axes are substantially parallel to each other. Note that in alternative embodiments, the nanowires of the nanowire film 100 are not aligned, but may be oriented in different directions randomly or otherwise relative to each other. In alternative embodiments, the nanowires of nanowire film 100 may be isotropically oriented, providing high mobility in all directions. It should be noted that the nanowires of the nanowire film 100 can be aligned in any manner relative to the direction of electron flow in order to enhance the properties desired for a particular application.

FIG. 2 shows a semiconductor device 200 including a nanowire thin film 100 according to a second embodiment of the present invention. In FIG. 2 , a semiconductor device 200 is shown as a transistor having a source 202 , a gate 204 , and a drain 206 formed on a substrate 208 . Nanowire film 100 is coupled between source 202 and drain 206 over a portion of gate 204 . Nanowire thin film 100 essentially functions as a channel region for a transistor of semiconductor device 200 and allows semiconductor device 200 to operate with enhanced characteristics, as further described herein. Various substrate types that may be suitable for substrate 208 are described herein.

It should be noted that for illustration purposes, semiconductor device 200 is shown in FIG. 2 as a transistor. Those skilled in the art will appreciate from the teachings herein that the nanowire film 100 may be incorporated into semiconductor device types other than transistors, including diodes.

In an embodiment, the nanowires of the nanowire film 100 are single crystal semiconductor nanowires spanning all paths between the source 202 and the drain 206 . As a result, electrical carriers can be transported through single-crystalline nanowires, resulting in high mobility that is practically impossible to obtain with current amorphous and polycrystalline silicon technologies.

As noted above, the nanowires of nanowire film 100 may be oriented or aligned. For example, the nanowires of nanowire film 100 shown in FIG. 2 may be aligned parallel to the length of the channel between source 202 and drain 206, or may be otherwise aligned.

The nanowire thin film 100 may be formed with a sufficient number of nanowires to provide predetermined characteristics for the semiconductor device 200 . For example, nanowire film 100 may be formed from a sufficient number of nanowires to achieve a desired current density or value for a particular semiconductor device. For example, in the transistor example of FIG. 2, the nanowire film 100 may be formed to have a current value in the channel greater than about 100 nanoamperes.

In an embodiment, the nanowire thin film 100 may be formed to have asymmetric mobility. For example, this can be achieved by asymmetrically aligning the nanowires of the nanowire film 100 and/or by doping the nanowires in a specific way. Such asymmetric mobility may be generated more in the first direction than in the second direction. For example, asymmetric mobility can be generated on the order of 10, 100, 1000, and 10,000 times greater in the first direction than in the second direction, or have any other asymmetric mobility between, greater or less than these values Rate.

The nanowires of nanowire film 100 can be doped in various ways, generally to enhance performance. The nanowires may be doped before or after inclusion in the semiconductor device 200 . In addition, nanowires may be doped differently along portions of their long axes, and may be doped differently than other nanowires in nanowire film 100 . Some examples of doping schemes for individual nanowires and for nanowire films are provided below. However, it will be apparent to those skilled in the art from the teachings herein that nanowires and nanowire films may be doped in other ways and in any combination of the ways described herein.

Figure 3A shows the nanowire 300 as a uniformly doped single crystal nanowire. Such single crystal nanowires can be doped into p- or n-type semiconductors in a suitably controlled manner. Doped nanowires such as nanowire 300 exhibit improved electronic properties. For example, such nanowires can be doped to have carrier mobility levels comparable to alternative single crystal materials. Furthermore, and without being bound to any particular theory of operation, due to the one-dimensional nature and reduced scattering probability of the electron wave traversing inside the nanowire channel, even more efficient than bulk single crystal materials can be achieved for such nanowires. high mobility. Carrier mobility values up to 1500 cm ² /V·s have been shown for single p-row Si (silicon) nanowires and up to 4000 cm ² /V·s for n-type InP nanowires Submobility values.

Figure 3B shows a nanowire 310 doped according to a core-shell structure. As shown in FIG. 3B , the nanowire 310 has a doped surface layer 302 , which can vary in thickness value, comprising only a molecular monolayer on the surface of the nanowire 310 . This surface doping can separate impurities from the nanowire's conductive channel and suppress impurity-related scattering events, thereby greatly increasing carrier mobility. For example, when nanowires are doped according to a core-shell structure, "ballistic" transport is where electrical carriers are transported through the nanowires with essentially no resistance. Further details of the doping of the nanowires will be provided below.

FIG. 3C shows another type of nanowire 320 uniformly doped and coated with a layer 304 of dielectric material according to a core-shell structure. The dielectric material layer 304 can be selected from various dielectric materials, such as SiO ₂ or Si ₃ N ₄ . The use of dielectric material layer 304 may simplify the fabrication of semiconductor device 200, as described herein. Layer 304 of dielectric material may be formed on nanowire 320, as further described below.

Figure 3D shows a nanowire 330 doped with a doped surface layer 302 and also coated with a dielectric material layer 304 according to the core-shell structure shown in Figure 3B, as shown in Figure 3C.

4A and 4B illustrate an example of a semiconductor device 200 according to a doped embodiment of the present invention. As shown in FIG. 4A , the top surface of substrate 208 is coated with doped layer 402 . The doped layer 402 includes electron donor or electron acceptor doping materials. The performance of the semiconductor device 200 can be controlled by introducing the doped layer 402 . Electron acceptors or electron acceptor materials introduce negative or positive charges into the nanowires in order to realize n- or p-channel transistors, respectively. Since the dopants are separated from the actual conducting channel, very high mobility values can be achieved in this structure of the semiconductor device 200 .

As shown in FIG. 4B , doped layer 402 covers a region of substrate 208 substantially localized around nanowire film 100 . In an embodiment, the doped layer 402 applied to the semiconductor device 200 may be patterned to have two or more regions doped according to different n or p row characteristics. For example, in the embodiment of FIG. 4B , doped layer 402 has a first portion 404 doped with n-type characteristics and a second portion 406 doped with p-type characteristics. In this embodiment, depending on the type of electronic and optoelectronic devices, including light emitting diodes (LEDs), p-n junctions can be realized.

As mentioned above, the doped layer 402 may be introduced onto the substrate 208 either before or after the actual fabrication of the semiconductor device 200 .

Nanowire aggregates fabricated with these materials are useful building blocks for high-performance electronic devices. Aggregates of nanowires oriented in substantially the same direction will have high mobility values. Furthermore, the nanowires are flexible to process in solution and thus can be fabricated cheaply. Aggregates of nanowires can be easily assembled from solution onto any type of substrate to realize nanowire thin films. For example, nanowire films for use in semiconductor devices can be formed to include 2, 5, 10, 100, and any other number of nanowires between or greater than these amounts for use in high performance electronic devices.

It should be noted that nanowires can also be used to fabricate high-performance composites when they are combined with polymers/materials such as organic semiconducting materials that can be flexibly sprayed onto any type of substrate. Nanowire/polymer composites can offer properties superior to pure polymer materials. Further details of the nanowire/polymer composites are provided below.

As noted above, nanowire film aggregates or films may be aligned substantially parallel to each other, or may remain misaligned or random. Non-aligned aggregates or thin films of nanowires provide electronic properties comparable to or superior to polysilicon materials, which typically have mobility values in the range of 1-10 cm ² /V·s.

Aggregates or thin films of aligned nanowires provide materials with properties comparable to or superior to single crystal materials. Furthermore, nanowire aggregates or films comprising aligned ballistic nanowires (eg, core-shell nanowires as shown in Figure 3B) can provide significantly improved performance over single crystalline materials.

According to the present invention, aligned and non-aligned and composite and non-composite nanowire films can be fabricated in various ways. Exemplary examples for the assembly and fabrication of these types of nanowire films are provided below.

Randomly oriented nanowire films can be obtained in various ways. For example, nanowires can be dispersed in a suitable solution. The nanowires are then deposited onto the desired substrate using spin coating, drop-dry or dip-dry methods. These treatments can be performed multiple times in order to ensure a high degree of coverage. Randomly oriented nanowire films/polymer composites can be fabricated in the same manner, as long as the solution in which the nanowires are dispersed is a polymer solution.

Aligned nanowire films can be obtained in various ways. For example, aligned nanowire films can be fabricated by using the following techniques: (a) Langmuir-Blodgett film alignment; (b) fluid flow schemes, as in U.S. Serial No. 10/239000 filed October 2002 ( Attorney Doket No. 01-000540), and the entire contents of which are incorporated herein by reference; and (c) applying a mechanical shear force. For example, mechanical shear forces are used by placing the nanowires between the first and second surfaces and then moving the first and second surfaces in opposite directions, thereby aligning the nanowires. By using these techniques and then spin-coating the desired polymer onto the resulting nanowire film, aligned nanowire films can be obtained. For example, nanowires can be deposited in a liquid polymer solution and then aligned according to one of these or other alignment processes, after which the aligned nanowire film is cured (eg, UV cured, crosslinked, etc.). Aligned nanowire films/polymer composites can also be obtained by mechanically stretching randomly oriented nanowire films/polymer composites.

Fabrication of electronic devices incorporating nanowire thin films

Embodiments for fabricating electronic devices and systems incorporating nanowire thin films according to the present invention are further described below. The embodiments described herein are illustrative only and not limiting. As described in this section, the electronic devices and systems of the present invention can be fabricated in other ways, as will be readily apparent to those skilled in the art from the teachings herein.

FIG. 5 shows a flowchart 500 providing exemplary steps for fabricating a plurality of semiconductor devices incorporating nanowire thin films of the present invention. The steps of FIG. 5 do not have to be performed in the order shown, which can be easily done by those skilled in the art based on the teachings herein. Other structural embodiments will also be apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 500 begins at step 502 . In step 502, a nanowire film is formed on the substrate with sufficient nanowire density to achieve an operating current value. For example, as described above, according to the present invention, a nanowire thin film can be formed on a substrate by various means. The nanowire film is formed with sufficient nanowire density so that an operating current value is achieved. Adequate operating current values are usually determined on an application basis. For example, the current value can be in the nanoampere range, including 2 nanoamperes, as well as higher and lower current values. The nanowire films described herein can be formed in various ways to obtain the desired operating current value. Nanowire films can be aligned or non-aligned, and can be composite or non-composite.

For example, a minimum number of nanowires may be included in a nanowire film for a given area on the substrate in order to achieve a desired operating current density. Accordingly, each semiconductor device formed will have a sufficient number of nanowires to carry current at operating current values. For example, the desired number of nanowires per unit area can be 1 nanowire, 2 nanowires, and any other greater number of nanowires, including 5, 10, 100 or more.

In step 504, a plurality of semiconductor device regions are defined in the nanowire film. For example, referring to the single semiconductor device 200 shown in FIG. 2, the entire nanowire film formed in step 502 is patterned to form a localized nanowire film 100 for each region of the substrate in which the semiconductor device is being formed. In alternative embodiments, the nanowire film need not be patterned. Note that on a particular substrate, semiconductor device regions may all define the same semiconductor device type, or may define two or more different semiconductor device types.

In step 506, contact (eg, electrode) regions are formed in the semiconductor device region, thereby providing electrical connections to the plurality of semiconductor devices. A semiconductor device may have any number of desired contact regions formed to provide electrical connections. For example, a diode or other two-terminal device may have an anode and a cathode formed. For example, referring again to the single semiconductor device 200 shown in FIG. 2 , three contacts are formed: source 202 , gates 2 - 4 , and drain 206 . Other semiconductor devices may have a greater or lesser number of contact regions formed.

It should be noted that various contact area types may be formed in step 506 . Contact areas can be ohmic and non-ohmic. For example, non-ohmic Schottky diode blocking contacts can be used as electrodes. Schottky diode blocking contacts are often used for III-V semiconductor materials when it is difficult to fabricate high-quality gate dielectrics. The source 202 , gate 204 , drain 206 are formed of conductive materials such as metals, alloys, silicide polysilicon, and the like, including combinations thereof, as will be apparent to those skilled in the art.

In some embodiments, the flowchart 500 of FIG. 5 may include the step of doping the nanowires. The nanowires may be doped before forming into a thin film or after forming into a thin film. The nanowire film can be doped after being formed on the substrate. Nanowires can be doped in various ways, including those described with reference to Figures 3A-3D. For example, the core of the nanowire can be doped and/or the shell of the nanowire can be doped. Furthermore, individual nanowires and/or nanowire films may be differently doped in different regions along their respective lengths.

Additionally, in some embodiments, the flowchart 500 of FIG. 5 may include the step of forming a dielectric layer on the nanowire. The dielectric layer can be formed by oxidizing the nanowires or by forming a dielectric layer. For example, other non-oxidizing high dielectric _constant materials may be used, including silicon nitride, _Ta2O5 , _TiO2 , _ZrO2 , _HfO2 , _{Al2O3 ,} and others. Nitriding of nanowires can be achieved in a similar manner to that employed in the oxidation of nanowires. These materials can be adapted for nanowires by chemical vapor deposition (CVD), solution phase overcoating, or simply by spin coating a suitable precursor onto the substrate. Other known techniques may also be used.

The steps of Figure 5 can be used to fabricate single or multiple semiconductor devices on a substrate. 6A-6F illustrate various stages of fabrication of a substrate 600 having a plurality of semiconductor devices thereon in accordance with an embodiment of the present invention. The steps of flowchart 500 shown in FIG. 5 will be referred to below in relation to the processes shown in FIGS. 6A-6F.

FIG. 6A shows a perspective view of a substrate 600 . Substrate 600 may be any substrate type, including silicon, glass, quartz, polymer, and any other substrate type described herein or known. Substrate 600 may be large or small area, and may be rigid or flexible, such as a flexible plastic or film substrate type. Substrate 600 may be opaque or transparent, and may be composed of conductive, semiconductive, or nonconductive materials.

FIG. 6B shows the patterning of a plurality of gates 204 on a substrate 600 . Gate 204 may be patterned, for example, using standard photolithography, inkjet printing, or microcontact printing processes, or by other processes. The patterning of the plurality of gates 204 shown in FIG. 6B may be performed, for example, during step 506 of the flowchart 500 shown in FIG. 5 .

FIG. 6C shows the deposition of a dielectric layer 602 on a substrate 600 . The dielectric layer 602 electrically insulates the plurality of gates 204 . Depositing the dielectric layer 602 on the substrate 600 may be performed using evaporation, solution casting of polymer or oxide dielectrics, and by other processes. Note that it is not necessary to deposit the dielectric layer 602 on the substrate 600 if the nanowires to be deposited on the substrate 600 are insulated by their own dielectric layer. For example, nanowires 320 and 330 shown in FIGS. 3C and 3D have a layer of dielectric material 304 pre-formed on their surfaces. Direct contact devices without a dielectric layer are also conceivable.

FIG. 6D shows the deposition of a nanowire film 604 on a substrate 600 . Deposition of the nanowire film 604 can be performed using various procedures described herein, including spin casting, Langmuir-Blodgett alignment, mechanical alignment, and fluidic alignment techniques. The deposition of the nanowire film 604 shown in FIG. 6D may be performed, for example, during step 502 of the process 500 shown in FIG. 5 .

FIG. 6E shows the patterning of the nanowire film 604 into a plurality of nanowire films 100 . Patterning of the nanowire film 604 can be performed using various processes, including photolithography. It should be noted that, as shown in Figures 6D and 6E, the deposition and patterning of the nanowire film 604 can be performed simultaneously using various processes such as inkjet printing or microcontact printing methods. Patterning the plurality of nanowire films 604 into the plurality of nanowire films 100 shown in FIG. 6E may be performed, for example, during step 504 of process 500 shown in FIG. 5 .

FIG. 6F shows patterning of a plurality of sources 202 and a plurality of drains 206 on a substrate 600 to form a plurality of semiconductor devices 200 . Source and drain patterning can be performed using a process similar to that used to pattern the plurality of gates 204 as shown in FIG. 6B . The patterning of the plurality of sources and drains shown in FIG. 6F may be performed, for example, during step 506 of process 500 shown in FIG. 5 .

It should be noted that the order of patterning the gate 204, source 202, and drain 206 can be changed. For example, gate 204, source 202, and drain 206 may be patterned simultaneously with each other or patterned differently. They can both be patterned before or after depositing the nanowire film 604 . The source 202 and drain 206 can be patterned prior to depositing the nanowire film 604, while the gate 204 can be patterned thereafter. Alternatively, the gate 204 can be patterned before depositing the nanowire film 604, and the source 202 and drain 206 can be patterned thereafter. Either of source 202 and drain 206 may also be patterned before depositing nanowire film 604, while the other is patterned thereafter.

It should be noted that in some embodiments more than one layer of nanowire film may be applied to the substrate in a given area. Multiple layers may be allowed for greater conductivity and may be used to modify the electrical properties of individual semiconductor devices. Multiple layers can be the same or different from each other. For example, two or more nanowire films with nanowires aligned in different directions, differently doped, and/or differently insulated may be used in certain semiconductor devices. The contact region of a particular semiconductor device can be coupled to any one or more layers of the multilayer nanowire film. It should be noted that nanowire films can be formed as monolayer nanowires, sub-monolayer nanowires, and nanowires larger than a monolayer, if desired.

Substrate nanowire materials for large-area macroelectronics

As noted above, electronic and photovoltaic films can be formed on macroelectronic (ie, large area electronic) substrates using nanowires fabricated from semiconducting materials. Furthermore, according to an embodiment of the present invention, nanowires may be composed of other materials, and films may be formed using these nanowires in the same manner as nanowires composed of semiconductor materials.

In embodiments of the present invention, nanowires may be composed of materials such as magnetic materials, ferroelectric materials, pyroelectric materials, piezoelectric materials, metals/alloys, and transition metal oxides. Furthermore, the corresponding thin films can be composed of magnetic nanowires, ferroelectric nanowires, pyroelectric nanowires, piezoelectric nanowires, metal/alloy and transition metal oxide nanowires. These thin films thus exhibit properties corresponding to magnetic, ferroelectric, pyroelectric, metallized or transition metal oxide materials and can be formed on large area substrates, which may be flexible or inflexible. Thus, completely new materials/devices can be formed according to the present invention.

For example, the nanowire 300 shown in FIG. 3A may be a nanowire composed of magnetic, ferroelectric, pyroelectric, piezoelectric, metallized, or transition metal oxide materials. Furthermore, for example, the nanowire film 100 shown in FIG. 1 may thus be a magnetic nanowire film, a ferroelectric nanowire film, a pyroelectric nanowire film, a piezoelectric nanowire film, a metallized nanowire film, or a transition metal oxide nanowire film. film or any combination thereof.

As such, devices such as semiconductor device 200 as shown in FIG. 2 may be formed using nanowire thin films composed of one or more of these materials. These devices may or may not require electrical contacts, depending on the type of nanowire material, such as magnetic nanowires.

For example, as described herein, semiconducting nanowire films may be used in electronic devices, such as semiconductor device 200 shown in FIG. 2 . Semiconductor device 200 is a three-terminal transistor device having a source 202 , a gate 204 and a drain 206 . As shown in FIG. 2 , nanowire film 100 couples source 202 to drain 206 . The gate 204 is formed adjacent to the nanowire film 100 . During operation, when a sufficient voltage is applied to the gate 204 , current can be conducted between the drain 206 and the source 202 . In an alternate embodiment, gate 204 need not be present, and device 200 operates as a two-terminal device, such as a diode. For example, source 202 and drain 206 may be cathodes and anodes in such alternative embodiments.

In an embodiment, when the nanowire film 100 is composed of one of magnetic, ferroelectric, pyroelectric, piezoelectric, metallized, or transition metal oxide materials, certain nanowires may be present during operation of an electronic device incorporating the film. properties of the material.

For example, in embodiments, permanent or non-permanent electrical polarization may be generated in the ferroelectric nanowire film when an electric current is applied to the ferroelectric nanowire film.

In another example embodiment, when an electric current is applied to the piezoelectric nanowire film, stress may be induced in the piezoelectric nanowire film, which may manifest as shape change, motion, and/or vibration of the piezoelectric nanowire film . Such nanowire films may have applications, for example, in the audio and other technical fields. Transition metal oxide materials are typical materials that can be used to fabricate piezoelectric nanowires.

In another example embodiment, when an electric current is applied to the thermoelectric nanowire film, heat may be transferred through the thermoelectric nanowire film. Such thermoelectric nanowire films may have many applications, such as in the field of temperature control and heating, in particular, where spatially localized heating and/or cooling is desired.

Magnetic nanowires may not have to be coupled to electrical contacts in order to work. A thin film of magnetic nanowires can be formed on a surface, thereby imparting magnetic properties to the surface. The dimensions of the nanowire film can be determined according to the particular application.

Metal nanowires can be formed into thin films for applications that require efficient conductors. In addition, electronic devices such as inductors, transformers, and electromagnets can be formed from thin films of metal nanowires.

FIG. 7 shows a flowchart 700 providing example steps for fabricating electronic devices incorporating nanowire thin films of the present invention, according to an embodiment of the present invention. Other structural embodiments will be apparent to those skilled in the art on the basis of the following description. These steps are described in detail below.

Process 700 starts at step 702 . In step 702, a plurality of {magnetic; ferroelectric; pyroelectric; piezoelectric; metallized; or transition metal oxide} nanowires are deposited onto a substrate. For example, the substrate is substrate 208 shown in FIG. 2 . In addition, the plurality of nanowires may be the nanowire film 100 described above, wherein the nanowires of the film are composed of magnetic, ferroelectric, pyroelectric, piezoelectric, metallized or transition metal oxide materials. The nanowires may be deposited onto the substrate such that the nanowires are randomly aligned relative to each other, or aligned such that their longitudinal axes are substantially parallel.

In step 704, first and second electrical contacts are formed on the substrate. For example, the first and second electrical contacts may be source 202 and drain 206 , as shown in FIG. 2 . In such an embodiment, the gate may also be formed on the substrate. Alternatively, the first and second electrical contacts may be cathodes and anodes. In other embodiments, the first and second electrical contacts may be of other contact types. Furthermore, other numbers of contacts/additional contacts may be formed on the substrate.

Steps 702 and 704 can be performed in any order. The effect of steps 702 and 704 is that at least one nanowire couples the first electrical contact to the second electrical contact. Subsequent processing steps can be performed as desired, such as those described herein, including patterning of the nanowires, doping of the nanowires, and bonding/fixing the nanowires to the substrate and contacting the electrical contacts.

Large-area macroelectronic materials that conduct electrons and holes with high mobility

When two types of p and n dopants can be doped into a semiconductor, such as silicon, the presence of two types of carriers in the same material leads to recombination and extinction of carriers, resulting in poor mobility. Thus, the combination of p-dopants and n-dopants in one semiconductor by conventional means is undesirable.

According to an embodiment of the present invention, p-doped nanowires and n-doped nanowires can be fabricated separately and deposited as a homogeneous mixture onto a surface, such as a macroelectronic substrate. On a macroscopic level, the resulting material appears to contain high concentrations of both n and p dopants. However, the individual carrier types are physically separated from each other (ie, they are different nanowires), and as a result, they do not substantially interact (ie, the carriers do not substantially annihilate each other). Thus, by creating a mixture of such p- and n-doped nanowires in response to their being n- and p-doped, macroelectronic devices can be fabricated. For example, the final nanowire film comprising n- and p-doped nanowires can exhibit the properties of n- and p-doped nanowires.

For example, diodes, transistors, and other electronic devices described or known herein can be fabricated to include combinations of p-doped and n-doped nanowires. For example, the semiconductor device 200 shown in FIG. 2 may include a nanowire film 100 including a combination of p-doped nanowires and n-doped nanowires. N-doped and p-doped nanowires can be combined in thin films in various ways. Some of these ways are described below.

For example, FIG. 8A shows a close-up view of an example portion of a nanowire film 800 that includes a homogeneous mixture of n-doped nanowires 802 and p-doped nanowires 804 . Film 800 can be used in various electronic device types. It should be noted that in the example of FIG. 8A, n-doped nanowires 802 and p-doped nanowires 804 may be formed and mixed prior to deposition on the substrate, or may be mixed onto the substrate. Furthermore, while random orientation of the nanowires is shown in Figure 8A, the present invention includes the use of partially and substantially parallel oriented nanowires, as described above.

In another example embodiment, FIG. 8B shows an example portion of a nanowire film 810 including n-doped nanowires 802 and p-doped nanowires 804 . For example, thin film 810 may be formed on a substrate. As shown in FIG. 8B , a first region of the film 810 includes a plurality of n-doped nanowires 802 and a second region 814 of the film 810 includes a plurality of p-doped nanowires 804 . In the example of FIG. 8B, the first region 812 and the second region 814 are substantially non-overlapping. Thus, as shown in the example of FIG. 8B, n-doped nanowires 802 and p-doped nanowires 804 may be deposited on the substrate using spatial or areal separation, substantially or even entirely, separately. N-doped nanowires and p-doped nanowires can be spatially or regionally separated in any structure, including forming separate strips, spots, etc. of n-doped nanowires and p-doped nanowires on a substrate.

In another exemplary embodiment, FIG. 8C shows a nanowire film 820 including n-doped nanowires 802 and p-doped nanowires 804 . As shown in FIG. 8C , a first sublayer 822 of the thin film 820 includes a plurality of n-doped nanowires 802 , and a second sublayer 824 of the thin film 820 includes a plurality of p-doped nanowires 804 . Thus, as shown in the example of FIG. 8C, n-doped nanowires 802 and p-doped nanowires 804 may be deposited on the substrate in two or more separate layers.

In embodiments of the invention, n-doped nanowires 802 and p-doped nanowires 804 may be mixed within one layer, separated regionally, and/or separated into separate layers in any combination.

FIG. 9 shows a flowchart 900 providing exemplary steps for fabricating the nanowire films of the present invention, according to an embodiment of the present invention. The steps of FIG. 9 do not have to be performed in the order shown, as will be apparent to those skilled in the art based on the teachings herein. Other structural embodiments will also be apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

The process 900 starts at step 902 . In step 902, a first plurality of p-doped nanowires is formed. For example, the first plurality of nanowires are p-doped nanowires 804, as shown in Figures 8A-8C. P-doped nanowires can be formed in any manner, as described or known herein. For example, p-doped nanowires can be grown as later p-doped intrinsic nanowires, or can be grown from p-doped semiconductor materials. Furthermore, the p-doped nanowires can all be composed of the same semiconductor material (eg, both are p-doped silicon), or there can be nanowires composed of different semiconductor materials (ie, some p-doped silicon nanowires and p-doped doped CdS nanowires).

In step 904, an n-doped second plurality of nanowires is formed. For example, the second plurality of nanowires are n-doped nanowires 802, as shown in Figures 8A-8C. The n-doped nanowires can be formed in any manner, as described or known herein. For example, n-doped nanowires can be grown as later n-doped intrinsic nanowires, or can be grown from n-doped semiconductor materials. Furthermore, the n-doped nanowires may all be composed of the same semiconductor material (eg, both are n-doped silicon), or there may be nanowires composed of different semiconductor materials (ie, some n-doped silicon nanowires and n-doped doped CdS nanowires).

In step 906, a first plurality of nanowires and a second plurality of nanowires are deposited onto the substrate, thereby forming a nanowire film comprising n-doped and p-doped nanowires. For example, in embodiments, the first and second plurality of nanowires may be deposited separately or simultaneously. The first and second plurality of nanowires can be mixed to form a single or multilayer homogeneous mixture. Alternatively, the first and second plurality of nanowires may be deposited onto two or more separate regions of the substrate, and/or into two or more separate sublayers of the film.

In an embodiment, when the n-doped nanowires and the p-doped nanowires are in a separate layer, the process 900 may include the step of forming another layer material. For example, the intermediate layer may be an insulating layer, such as a plastic layer, a glass layer, an air layer, or other insulating layer types.

In this way, semiconductor devices/materials can be formed with p-doped and n-doped characteristics. In embodiments, such devices/materials may be considered to have n and p characteristics over length dimensions greater than a factor X, where X depends on nanowire size, nanowire density, and/or other factors. Prior to the present invention, such devices/materials did not exist.

Macroelectronic devices fabricated with nanowire heterostructures

In another embodiment of the present invention, electronic devices such as p-n diodes, transistors, and other electronic device types can be fabricated using nanowire heterostructures. As described herein, nanowire heterostructures are nanowires that typically include multiple p-n junctions along the length of the nanowire. In other words, nanowire heterostructures include alternating portions or segments along their different lengths. For example, a nanowire heterostructure may have alternating portions that are differently doped and/or composed of different materials.

By forming nanowires with distinct sections, the fabrication of semiconductor devices can be greatly simplified. For example, in embodiments where the portions are doped differently, since the nanowires are doped, it is not necessary to use expensive photolithography or ion implantation processes to dope the regions of the substrate on which the nanowires will be affixed, as is conventional. Furthermore, the ohmic contact to the substrate can be improved by using doped nanowires compared to intrinsic nanowires. In addition, compared to conventional nanowires, nanowire heterostructures do not have to be carefully placed on the substrate because they are usually longer than the distance between electrodes on the substrate. Thus, most of them will span the distance between the electrodes and thus make contact with the electrodes relative to conventional nanowires.

In embodiments where the parts are of different materials, many applications are possible. For example, a nanowire heterostructure may include a first heavily p-doped silicon portion, a second heavily n-doped GaN portion, and a third heavily n-doped silicon portion. This will be used to simplify the electrical connection to the GaN LED. Any other combination of doping and materials can be employed in the nanowire heterostructure.

In a first embodiment, nanowire heterostructures are grown to have multiple p-n junctions along their length. (Note that the following discussion will apply to other different points along the length of the nanowire, including different materials, etc. For illustration purposes, the discussion will focus on different doped moieties.) For example, FIG. Nanowire 1000 of nanowire heterostructure. As shown in FIG. 10, the nanowire 1000 has a plurality of n-doped portions 1010a, b and a plurality of p-doped portions 1020a, b. Accordingly, a plurality of p-n junctions 1030a, b, c exist at the intersection of the p-doped portion 1010 and the n-doped portion 1020 . Furthermore, each doped portion of nanowire 1000 has a length 1002 .

In an embodiment, the length of the doped portion of the nanowire 1000 may be uniform or non-uniform. Preferably, the doped portion of the nanowire heterostructure of the present invention has a length approximately equal to the distance between the electrodes (i.e., in other words, the p-n junctions are spaced) in the final device in which the nanowire will be used heterogeneous structure. For example, in an embodiment, the length of the doped portion may be equal to, or slightly greater than, the distance between the electrodes. In this way, when nanowire heterostructures are deposited onto a substrate, on average, one p-n junction per nanowire heterostructure will be located between the electrodes of the final device, and each nanowire heterostructure will The structure will be able to span the distance between the electrodes. Furthermore, due to the number of doped moieties in each nanowire, the overall length of each nanowire heterostructure will tend to be much greater than the distance between electrodes. These properties will create an efficient p-n diode between each electrode pair, resulting in a red electronic device. Furthermore, fabrication constraints are reduced by using nanowire heterostructures, since nanowire heterostructures can be deposited onto the substrate with the required fine precision, and can even be deposited randomly. The repeating structure of the nanowire heterostructure statistically allows sufficient p-n junctions of the randomly deposited nanowire heterostructure to be located between electrical contacts to fabricate an operable device. This fabrication advantage of nanowire heterostructures is further illustrated below.

Using nanowire heterostructures, macroscopic heterostructure electronic devices can be fabricated. For example, FIG. 11A shows an exemplary two-terminal electronic device 1100 comprising a plurality of nanowires 1000 in accordance with an embodiment of the present invention. As shown in FIG. 11A, nanowires 1000a-e are deposited on first electrical contact 1102 and on second electrical contact 1104 in a non-aligned manner. For example, device 1100 can be a diode, and first and second electrical contacts 1102 and 1104 can be cathodes and anodes. As shown in the embodiment of FIG. 11A , the distance between the first electrical contact 1102 and the second electrical contact 1104 is approximately equal to the length 1002 (e.g., center to center or between inner edges), which is the distance between the nanowires 1000a-e. The length of the doped portion. Furthermore, the overall length of the nanowires 1000a - e is greater than the distance between the first electrical contact 1102 and the second electrical contact 1104 . As shown in Figure 1 IA, the nanowires 1000c, 1000d, and 1000e do not couple the first and second electrical contacts 1102 and 1104 together. However, due to their location, nanowires 1000a and 1000b couple first and second electrical contacts 1102 and 1104 together. Additionally, nanowires 1000a and 1000b have respective p-n junctions between first and second electrical contacts 1102 and 1104 . Thus, device 1100 can operate as a diode constructed as in FIG. 11A.

It should be noted that in the example of FIG. 11A, the p-n junctions 1030a and 1030b of the nanowires 1000a and 1000b, respectively, point opposite to each other. In other words, the n-doped portion of nanowire 1000a and the p-doped portion of nanowire 1000b are in contact with first electrical contact 1102, and the p-doped portion of nanowire 1000a and the n-doped portion of nanowire 1000b are in contact with second electrical contact 1104. touch. As such, the p-n junctions 1030a and 1030b of the nanowires 1000a and 1000b are conductive and non-conductive, respectively, in opposite directions from each other. Such an arrangement of the nanowires 1000a and 1000b may occur, for example, during random deposition of the nanowire heterostructure onto the substrate. However, in some applications, the first and second electrical contacts 1102 and 1104 will have a voltage applied to only allow current to flow in one direction, allowing only one of the p-n junctions 1030a and 1030b of the nanowires 1000a and 1000b, respectively. Work. For example, nanowires 1000a and 1000b may be luminescent nanowires (as described further below). Thus, when a sufficiently high voltage is applied to the first electrical contact 1102 relative to the second electrical contact 1104, the p-n junction 1030b of the nanowire 1000b will conduct and emit light. When the high voltage is removed from the first electrical contact 1102, neither of the nanowires 1000a and 1000b emits light. As such, having additional nanowire heterostructures oriented in the opposite direction to the direction of current flow will not interfere with operation in this application. However, the present embodiment produces a novel light emitting diode that emits light even when reverse biased (ie, when p-n junction 1030a is forward biased and p-n junction 1030b does not emit light). However, in other applications, p-n junctions with oppositely directed nanowire heterostructures are undesirable. Thus, in these applications it is desirable to deposit nanowires in a manner that does not cause oppositely directed p-n junctions.

For example, in another embodiment, the nanowires 1000 may be aligned relative to each other and to a predetermined electrode pattern such that their p-n junctions 1000 are aligned. For example, this can be achieved by chemically patterning the substrate so that the nanowires 1000 are only bonded or fixed to defined locations. Also, this can be done in other ways.

In a similar manner to the fabrication of two-terminal devices, more complex devices such as p-n-p or n-p-n bipolar transistors can be formed by fabricating nanowire heterostructures with Periodically spaced p-n-p repeats of the distance between. In one embodiment, for devices with more than one interface per device, it is desirable that while the nanowire heterostructure has a built-in period substantially equal to the distance between the electrodes, the full length of the device within each period relative to the full The span is very small. This would help reduce the number of nanowires that bridge the gap between electrodes using only half a p-n-p segment at each end, rather than the entire p-n-p segment in the middle.

For example, FIG. 11B shows a nanowire heterostructure incorporating a drain 1152, a gate 1154, and Source 1156 of p-n-p transistor 1150 . As shown in FIG. 11B , a p-n junction exists in each nanowire 1000a - c between the drain 1152 and the gate 1154 . In one embodiment, for example, the gate 1154 may be separated from the nanowires 1000a-c by a dielectric/insulator layer (not shown in Figure 1 IB). Thus, by electrode nanowire heterostructures on electrodes 1152, 1154, and 1156, p-n-p transistor 1150 may be formed.

Using nanowire heterostructures, virtually any type of electronic device can be formed from any material. For example, devices can be fabricated using nanowire heterostructures formed from any material, including electronic, semiconducting, optical, optoelectronic, piezoelectric, pyroelectric, ferroelectric, and other materials.

As described above, nanowire heterostructures can be grown. Alternatively, photolithography, ion implantation, or other doping processes can be used to fabricate differently doped regions of the nanowire heterostructure to form macroscopic p-n junctions. In embodiments, this process may be performed as part of the patterning process accompanying the fabrication of the electrodes.

Note that in embodiments, the nanowire heterostructure may have more than two different dopant types. For example, nanowire 1000 has two repeating dopant type sections: n-doped and p-doped sections (ie, repeating n:p doping pattern). Additionally, the nanowire heterostructure can be other numbers of repeating dopant type sections including: p:n:p, n:p:n, p:i:p, n:i:n, p ⁺ :p: n, n ⁺ :p:p, p ⁺ :n:p, n ⁺ :p:n and any other repeating graphics.

FIG. 12 shows a flowchart 1200 providing example steps for fabricating electronic devices incorporating nanowire heterostructures in accordance with an embodiment of the present invention. The steps of FIG. 12 do not have to be executed in the order shown, as those skilled in the art can easily figure out based on the teachings herein. Other structural embodiments will also be apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

The process 1200 starts at step 1202 . In step 1202, a plurality of nanowires are formed such that each nanowire has along its long axis at least one first portion doped with a first dopant and at least one second portion doped with a second dopant. Sections, each nanowire having a spacing between successive junctions of the first and second sections that is substantially equal to the first distance. For example, a plurality of nanowires may be formed similar to nanowire 1000 of FIG. 10 . As shown in FIG. 10, a nanowire 1000 is formed having a p-doped portion 1010 and an n-doped portion 1020 doped with n- and p-type dopant materials, respectively. Furthermore, as shown in FIG. 10 , nanowire 1000 has a spacing between p-n junctions 1030 of length 1002 . Nanowire heterostructures can be formed to any length, with any number of alternating doped sections.

In step 1204, a pair of electrical contacts is formed on the substrate, wherein the distance between the electrical contacts is approximately equal to the first distance. For example, in an embodiment, the electrical contacts are first and second electrical contacts 1102 and 1104, as shown in FIG. 11A. As shown in FIG. 11A , the distance between first and second electrical contacts 1102 and 1104 is approximately equal to length 1002 . Alternatively, in an embodiment, the pair of electrical contacts is a drain 1152 and a gate 1154 as shown in FIG. 11B .

In step 1206, a plurality of nanowires is deposited on the substrate, wherein at least one nanowire of the plurality of nanowires couples the first electrical contact to the second electrical contact. For example, as shown in Figure 1 IA, a plurality of nanowires 1000a-e are deposited onto a substrate. As shown in Figure 1 IB, a plurality of nanowires 1000a-c are deposited onto a substrate. The plurality of nanowires can be deposited on the substrate by any means described herein or known. The plurality of nanowires can then be affixed to the electrical contacts according to any affixing means.

Luminescent film using nanowire red electronics

In embodiments, nanowires made of fluorescent semiconductor materials, phosphorescent, electroluminescent, cathodoluminescent, or other light-emitting materials can be deposited onto glass, plastic, or other substrate types, allowing low-cost, large-area light emitting, Emit white light or light of any other color. For example, an aligned monolayer of semiconducting nanowires can be formed on a substrate for this purpose. These nanowires can be fabricated from fluorescent materials such as CdSe, GaN, InP or any other conventional or non-traditional electroluminescent semiconductor material.

However, in order to form a light emitting diode (LED), a p-n junction must exist in each nanowire, between each pair of electrodes. It is difficult and expensive to fabricate if each nanowire has to be macroscopically doped using, for example, post-fabrication ion implantation.

Thus, according to the present invention, nanowires can be formed/grown to have p-n junctions in them in the manner described above for nanowire heterostructures. As mentioned above, each nanowire can be formed with one or more p-n junctions. The p-n junctions are preferably spaced about the same distance as the electrodes to which they will be fixed in the final display/lighting device. Thus, as described above, when a large number of nanowire heterostructures are deposited onto a substrate, there will be a distribution of p-n junctions between the electrodes, but none of the p- or n-doped regions will span the entire distance between the electrodes. On average, each nanowire will span the entire gap or distance between the electrodes and will have a p-n junction between the electrodes. This produces an efficient LED in each nanowire, where the p-n orientation is the correct bias direction for macroelectronic LEDs. This can be done over a very large area, on a flexible substrate, if desired, by patterning the array of anodes and cathodes, or source/drain. It should be noted that a specific aspect of the invention is that if the nanowires are deposited such that the positions of the ends are random, approximately half of the nanowires on a particular surface will have p-n junctions in the proper orientation, thus in a particular direction Light will be produced when a bias is applied, while the other half will not emit light. When biased in the opposite direction, the roles are reversed for different parts of the nanowire, so that the second half of the nanowire emits light while the first half does not. In this way, this technology realizes bipolar LEDs. Conventional unipolar LEDs can also be fabricated using the present invention by using partial end alignment as described above.

The color or wavelength of light emitted by the nanowire depends at least in part on the type of material from which the nanowire is made and the diameter of the nanowire. In an embodiment, by using a single nanowire material and nanowire diameter for nanowires used in display/lighting devices, a monochromatic light source can be fabricated. In another embodiment, by using a mixture of nanowires made of different materials and/or having different diameters, a multicolor light source can be fabricated. For example, if red, blue and green nanowires are included in the mixture, a white light source can be produced.

The luminescent nanowire films of the present invention allow higher quality color purity light emission, and allow improved color index over conventional light emitters. In embodiments of the present invention, these factors are much higher for thin-film light-emitting nanowire films than OLED-based types of thin-film light emitters because of the ability to mix many pure colors.

Quantum confinement effects in nanowires can be advantageously exploited in order to control the emission wavelength of electroluminescent nanowires as a function of diameter while maintaining the same material composition. This can be used to simplify electrical connections to such hybrid films, since the composition of each light-emitting element in the hybrid film is the same.

It should be noted that the electrodes of the luminescent nanowire heterostructure can be arranged in any pattern, as desired for a display or illumination pattern. For example, FIG. 13A shows discrete pixels or light sources 1300 having a pair of electrodes, first electrical contact 1302 and second electrical contact 1304, in accordance with an embodiment of the invention. The first and second electrical contacts 1302 and 1304 may be the anode and cathode of an LED, or may be a pair of electrodes of a light emitting transistor. A plurality of luminescent nanowires 1310a-e are also present in the light source 1300. Luminescent nanowires 1310 a - e doped the same as nanowire 1000 of FIG. 10 and fabricated from a luminescent material are coupled between first and second electrical contacts 1302 and 1304 . When a sufficient voltage is applied to the first electrical contact 1302 relative to the second electrical contact 1304, the p-n junction 1320 of each luminescent nanowire 1310a-e emits light. Although aligned nanowires 1310a-e are shown in FIG. 13A, in alternative embodiments, the nanowires 1310 need not be aligned and may, for example, be randomly distributed.

In another exemplary embodiment, FIG. 13B shows a column of discrete pixels or light sources 1300a - c each similar to pixel or light source 1300 . In the same way, any number of pixels or light sources 1300 can be arranged in rows, columns or in a two-dimensional array for use in eg displays with a large number/multiple pixels. It should be noted that, as shown in Figure 13B, the light sources 1300a-c may have a common second electrical contact 1304, if desired, and may be independently controlled by the first electrical contacts 1302a-c, respectively. Alternatively, a separate second electrical contact is also possible.

In another exemplary embodiment, FIG. 13C illustrates a large area light source 1320 comprising a plurality of light source columns 1350 in accordance with an embodiment of the invention. Light source 1320 includes elongated first and second electrical contacts 1324 and 1326 arranged to illuminate p-n junctions in columns 1350a-c (or rows), thereby providing illumination over a large area. The first and second electrical contacts 1324 and 1326 can be of any length, can have any number of bends and/or track "fingers", and can be interlocked in any number of columns and/or rows to allow nanowire They are bridged to provide light (and/or other diode functions) over a relatively large area.

It should be noted that the spacing between electrodes can be chosen for optimum electrical performance. The length of the electrodes can be arbitrarily long to maximize the total fluorescence/illumination output and reduce the number of processing steps required.

In another embodiment, the nanowires 1310 may be aligned relative to each other and to predetermined electrodes such that their p-n junctions 1320 are aligned. For example, this can be accomplished by chemically patterning the substrate so that the nanowires 1310 are only bonded or fixed to defined locations. This can produce more efficient light emitting devices with less statistical variation between formed light source devices. Alternatively, nanowires 1310 may be randomly deposited or isotropically oriented. In such embodiments, relatively few efficient light emitting devices can be produced (e.g., fewer nanowires 1310 can couple to electrodes and thus be inoperable), and relatively more light emitting devices can be produced between formed light source devices. statistical changes.

In addition, the light source may include the nanowire 1310 , a sub-monolayer nanowire 1310 , or a multilayer nanowire 1310 formed in a film that is a monolayer (ie, one nanowire thick layer) of the nanowire 1310 .

Furthermore, light-emitting films can be fabricated without the need to create p-n junctions within the nanowires. This can be achieved by post-deposition lithography and implantation, or by fabricating Schottky diodes at the semiconductor-electrode interface.

Figure 14 shows a flowchart 1400 providing example steps for fabricating a light emitting device incorporating a light emitting nanowire heterostructure in accordance with an embodiment of the present invention. The steps of FIG. 14 do not have to be performed in the order shown, as would be readily understood by those skilled in the art based on the teachings herein. Other structural embodiments are also readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 1400 begins at step 1402 . In step 1402, at least one light emitting semiconductor material is selected. For example, the semiconductor material may include one or more fluorescent materials, or other luminescent materials such as CdSe or InP, which are suitable for luminescent nanowire applications. A single material can be chosen for a monochromatic light source, or multiple materials can be chosen to make different nanowires, allowing multicolor light sources to be made.

It should be noted that some materials emit light at the nanometer scale, although the material does not emit light at larger dimensions. These materials are suitable for use in luminescent nanowires. For example, some bulk semiconductor materials do not emit light, but nanoscale particles of the same material do. This includes silicon, a semiconductor that normally does not emit light, but begins to emit light below a certain critical dimension. Any of these light emitting semiconductor material types are suitable for use in the present invention.

It should be noted that process 1400 may optionally include a step of selecting a nanowire diameter.

In step 1404, a plurality of nanowires are formed from the selected at least one light emitting semiconductor material. For example, the plurality of nanowires are nanowires 1310a-e, as shown in Figure 13A. Note that any number of luminescent nanowires can be fabricated for a particular operation, including 10s, 100s, 1000s, quantities of millions, and others. In an embodiment, note that step 1404 may include the step of forming one or more nanowires of the plurality of nanowires having a selected diameter.

In step 1406, each nanowire is doped such that each nanowire includes at least one p-n junction. In an embodiment, each nanowire is doped with a plurality of alternating n and p doped portions. For example, the nanowires are doped in the same manner as shown for nanowires 1000 shown in FIG. 10 and nanowires 1310a-e shown in FIG. 13A. Nanowires can be doped to have any number of alternating n and p doped sections.

It should be noted that in an embodiment, steps 1404 and 1406 are performed simultaneously, wherein n and p doped regions are formed in the nanowires as they are grown. Alternatively, steps 1404 and 1406 can be performed separately. Furthermore, in an embodiment, each nanowire is formed with a distance between successive junctions of alternating doped portions substantially equal to the first distance.

At step 1408, a plurality of nanowires are deposited onto the substrate. For example, a plurality of nanowires are deposited onto a substrate, as shown in Figures 13A-13C. The nanowires can be deposited in any manner and on any substrate type described or known herein. The substrate can be of any size, small or large, such as large area macroelectronic substrates. In an embodiment, the substrate has first and second electrical contacts formed thereon. In an embodiment, at least one nanowire of the plurality of nanowires couples the first electrical contact to the second electrical contact. Furthermore, electrical contacts can be spaced apart by the distance between p-n junctions in the nanowire.

It should be noted that in an alternative embodiment for a light emitting semiconductor device, a nanowire is deposited onto the substrate, which couples the first electrical contact to the second electrical contact. At least one of the first and second electrical contacts is a metal contact. During operation of the light emitting device, due to the Schottky effect, light can be emitted from the junction of the nanowire and the electrical contact of the metal in the same way as a Schottky diode works. In such embodiments, the nanowires used in the device need not be nanowire heterostructures, but can be uniformly doped/undoped nanowires if desired.

Nanowire Solution Fluid Mask Embodiment

As mentioned above, many electronic and other types of devices can incorporate nanowires. In this subsection, a technique for precisely positioning the nanowires is required.

In a large-scale manufacturing environment, a nanowire placement technique is required for devices manufactured in large quantities. For example, for each device fabricated, nanowires must be disposed on the surface of the device in order to make electrical contacts as desired. However, these devices must be fabricated using commercial/economic practices. The nanowires must be precisely positioned and placed on the surface in sufficient numbers/density. In some cases, the nanowires must be placed in alignment with each other. As such, techniques for placing nanowires in accordance with these fabrication requirements in a commercial/economically practical manner are desired.

Furthermore, after fabrication of the nanowires, it is desirable to test some of the fabricated nanowires in a quality control environment. For example, it may be desirable to test whether a nanowire is sufficiently conductive, to measure the impedance of the nanowire and/or to measure other electrical/mechanical properties of the nanowire. As such, it is desirable to place the nanowires on the surface in contact with the test electrodes using commercial practice.

According to the invention, the nanowires in solution flow on the surface. The nanowire solution flows over the surface in such a way that one or more nanowires of the solution remain or adhere to the surface. The nanowire solution flow is then removed, and one or more nanowires remain on the surface, thereby forming one or more electrical contacts and/or other connection types.

In one embodiment, a fluid mask is used to direct the flow of nanowires onto the indicated portion of the surface. The fluid mask thus allows the placement of nanowires on indicated portions of the surface. In an embodiment, the nanowires are placed in alignment with each other using a fluid mask. In other embodiments, the nanowires are placed without a fluid mask.

In an embodiment, the invention allows the placement of nanowires with a low probability of small parallel circuits. In other words, the present invention allows depositing nanowires at a desired density so that an electrical connection can be made through one nanowire, if desired. In addition, devices are available which also enable fast measurement of line and contact resistance in wet chemical and dry environments.

This section presents examples of fluidic techniques and fluidic mask embodiments for disposing nanowires on surfaces. For use in electronic devices, in electrical test structures, and in any other device or system, the nanowires can be positioned through a fluid mask on a semiconductor wafer, electronic substrate, or any other surface. The specific examples described herein are provided for purposes of illustration, not limitation. Other embodiments of fluid masks will be readily apparent to those skilled in the art based on the teachings herein. These alternative embodiments are within the scope and spirit of the invention.

15A and 15B illustrate bottom and cross-sectional views of an exemplary fluid mask 1500 in accordance with an embodiment of the present invention. As shown in FIGS. 15A and 15B , fluid mask 1500 includes body 1502 . Body 1502 includes input port 1510 and output port 1520 . The first surface 1504 of the body 1502 is configured to mate with a target surface. For example, the target surface may be the surface of a wafer, the surface of a substrate, such as a macroscopic electronic substrate, or the surface of any other structure. For example, the target surface may be the surface of a semiconductor wafer having an array of integrated circuits formed thereon. Fluid mask 1500 can be applied to the surface of a semiconductor wafer to locate nanowires on any or all integrated circuits. Fluid mask 1500 may be sized to cover the entire wafer, or any portion thereof.

As shown in FIG. 15A, the first surface 1504 has a plurality of channels 1506a-1506e formed therein. The channels 1506 may be substantially parallel to each other, as shown in Figure 15A, or they may be formed in one or more different directions, as desired for the deposition of nanowires. As shown in FIG. 15A, the first surface 1504 also has first and second feeder channels 1530a and 1530b formed therein. . First feed channel 1530 a is an input feed channel coupled between input port 1510 and a first end of channel 1506 . Second feed channel 1530b is an output feed channel coupled between the second end of channel 1506 and output port 1520 . First and second feed channels 1530a and 1530b are optionally present. Additionally, the first and second feeder channels 1530a and 1530b may be exposed on the first surface 1504 (as shown in FIG. 15A ) or may be inside the fluid mask 1500 when present. In embodiments where one or both of first and second feed channels 1530a and 1530b are absent, each channel 1506 may be directly coupled to input port 1510 and/or output port 1520 . Alternatively, each channel may have an input port 1510 and/or an output port 1520 .

As shown in Figures 15A and 15B, the input port 1510 is coupled to the first ends of the channels 1506a-e through a first feeder channel 1530a, and the second port 1520 is coupled to the channels 1506a-e through a second feeder channel 1530b. the second end of . An input port 1510 is formed in the body 1502 to deliver nanowire flow to the channels 1506a-e. An output port 1520 is formed in the body 1502 to remove nanowire flow from the channels 1506a-e. In this way, the flow of nanowires is directed to the input port 1510 of the body 1502 and flows through the first feeder channel 1530a. The first feeder channel 1530a distributes the flow of nanowires to the channels 1506a-e. The second feeder channel 1530b collects the flow of nanowires from the channels 1506a-e. The nanowire stream flows from the second feeder channel 1530b to the output port 1520 where the nanowire stream is removed from the fluid mask 1500 . Each channel 1506a-e covers a portion of the target surface when the first surface 1504 is mated with the target surface. Channels 1506a-e are formed in the first surface 1504 such that the nanowires allowing nanowire flow are disposed on the portion of the target surface covered by the channels 1506a-e.

The length, width and/or depth of the channel 1506 can be selected in order to control nanowire flow and optimize/control the placement and orientation of the nanowires on the target surface. These parameters can be optimized for a particular length/width of the nanowire stream. Furthermore, these parameters can be optimized for specific target conduction paths on the target surface. For example, fluidic mask 1500 may have channels of any width, including widths in the range of a few, tens, hundreds, and thousands of microns. For example, for a 15 μm long nanowire, the channel width may be in the range of 1-1000 μm, including 100 μm, 500 μm, 700 μm and other width channels therebetween. Additionally, the channel 1506 may include multiple channel segments separated by conduits (ie, tubes or tunnels in the fluid mask 1500 ) that extend into the interior of the fluid mask 1500 . In this way, the channel 1506 can place the nanowires along the channel 1506 on discrete, separate regions of the target surface.

Fluid mask 1500 may be formed from a variety of materials, including metals or metal/alloys, plastics, polymers, glass, substrate materials, and combinations of other materials. Fluid mask 1500 may be formed by molding, machining, etching, and/or other means. Fluid mask 1500 can be made to any size desired. For example, a four inch diameter or square fluid mask can be used to interface with a four inch substrate or wafer.

Various systems may be used in conjunction with fluid mask 1500 for positioning nanowires according to embodiments of the present invention. For example, FIG. 16 shows a nanowire positioning system 1600 incorporating a fluid mask 1500 according to an example embodiment of the invention. As shown in FIG. 16 , system 1600 includes fluid mask 1500 , target surface 1602 , nanowire solution source 1604 , and nanowire solution container 1606 . Additionally, as shown in FIG. 16 , nanowire solution source 1604 contains nanowire solution 1650 . Nanowire solution 1650 is typically a liquid solution containing a plurality of nanowires. The composition of the nanowire solution 1650 may be selected so as to facilitate transport of the nanowires from the flow of nanowires through the fluid mask 1500 to the target surface 1602 .

As shown in FIG. 16 , first surface 1504 of fluid mask 1500 engages target surface 1602 . Fluid mask 1500 is configured to cooperate with target surface 1602 to substantially form a leak-tight seal therebetween. In this way, the nanowire solution 1650 will be substantially contained within the enclosure formed between the fluid mask 1500 and the target surface 1602 when flowing therethrough. In an embodiment, first surface 1504 of fluid mask 1500 is substantially flat or planar (excluding channel 1506 and feeder channel 1530 when present) so as to mate with flat or planar target surface 1602 , thereby forming a seal. However, in alternate embodiments, the first surface 1504 may be contoured to match the target surface 1602 . Additionally, the fluid mask 1500 and target surface 1602 may have interlocking tabs and grooves allowing them to fit/align properly with each other. Fluid mask 1500 and target surface 1602 may alternately be mated/aligned optically and/or mechanically. A sealing material may be used between the fluid mask 1500 and the target surface 1605 to help maintain a seal, although such sealing material is not required in all applications.

Nanowire solution source 1604 is coupled to input port 1510 of fluid mask 1500 , nanowire solution source 1604 delivers nanowire solution 1650 to input port 1510 to deliver a flow of nanowires through fluid mask 1500 , across target surface 1602 . Nanowire solution container 1606 is coupled to output port 1520 of fluid mask 1500 to receive and remove nanowire flow from fluid mask 1500 and, in an embodiment, may store received nanowire solution 1650 . In an embodiment, nanowire solution source 1604 may deliver a pressurized flow of nanowires through fluid mask 1500 . Furthermore, in an embodiment, the nanowire solution source 1604 can precisely control the flow rate of the nanowire solution 1650 through the fluid mask 1500 .

17A and 17B illustrate plan and cross-sectional views of a flow 1702 of nanowires flowing through a fluid mask 1500 according to an example embodiment of the invention. The direction/path of flow 1702 through fluid mask 1500 is generally indicated by arrows. Additionally, additional arrows 1710 indicate that some nanowires of the nanowire stream 1702 exit the nanowire solution 1650 to localize on the target surface 1602 . In an embodiment, the nanowires are positioned on the target surface 1602 through the channel 1506 in an orientation substantially parallel to the direction of the flow 1702 .

Figure 18A shows a plan view of an example semiconductor wafer 1800 mated with a fluid mask 1500 (only the channel locations of the fluid mask 1500 are shown in Figure 18A). The positions of the channels 1506a-e of the fluid mask 1500 relative to the wafer 1800 are indicated by dashed lines. Each channel 1506a-e is configured to cover a corresponding one of the portions 1802a-e of the wafer 1800.

Figure 18B shows nanowire regions 1810a-e (ie, nanowire deposition regions) on the surface of a wafer 1800 having nanowires disposed thereon as a result of the operation of the present invention.

Figure 18C shows a further detail view of an example wafer 1800 on which an array of integrated circuits 1820a-n are formed. Integrated circuit 1820 may be any integrated circuit type and any size, including 0.5 cm ² . As shown in Figure 18C, a portion of each integrated circuit 1820a-n is covered by a portion of one of the nanowire regions 1810a-e. Thus, nanowires are disposed on portions of each integrated circuit 1820a-n by the fluid mask of the present invention. For example, integrated circuits may each include a plurality of conductive traces. Nanowires of nanowire regions 1810 a - e form one or more connections between conductive traces of each integrated circuit 1820 .

For example, FIG. 19A shows an integrated circuit 1900 that may be an example of one of integrated circuits 1820 . As shown in Figure 19A, a portion 1802 of an integrated circuit 1900 is covered by a channel of a fluid mask. FIG. 19B shows a close-up view of a portion 1920 of integrated circuit 1900 showing a detail view of an example of conductive trace 1902 . FIG. 19C shows a schematic view of a portion 1920 after deposition of nanowires 1910 in nanowire region 1810 by working of fluid mask 1500 . As shown in FIG. 19C , after operation of fluid mask 1500 , nanowires 1910 are disposed to form electrical connections between individual ones of conductive traces 1902 . For example, as shown in FIG. 19C , nanowire 1910 a forms a connection between a trace finger of ground signal trace 1904 and trace finger 1956 .

It should be noted that the density of nanowires 1910 deposited on an integrated circuit or other surface can be controlled in various ways, including: varying the flow rate of nanowires through fluid mask 1500; selecting the nanowires in nanowire solution 1650; control the composition of the nanowire solution 1650 (eg, select the type of alkaline solution, etc.); select the length of time for which the nanowire flow is applied, etc. The density of nanowires 1910 can thereby be controlled, thereby statistically controlling how many nanowires 1910 will be allowed to form each connection on integrated circuit 1900 . Furthermore, the spacing between the electrodes, the thickness of the electrodes, the width of the channel 1506, etc. can be used to control how many nanowires 1910 will be allowed to form each connection.

In addition, note that the nanowires 1910 can be deposited onto the substrate using the fluid mask 1500 either before or after the pattern of the integrated circuit 1900 is formed on the substrate. For example, if the nanowires 1910 are deposited first, the traces of the integrated circuit 1900 are then formed on the substrate, on the nanowires 1910 .

Figure 20A shows a graph 2000 related to Figures 19A-C. Curve 2000 represents various probabilities involved in forming the electrical connections of integrated circuit 1900 in accordance with the present invention. The Y-axis of the curve 2000 represents probability, and the X-axis of the curve 2000 represents the number of nanowires per length (1/μm). The example of curve 2000 relates to nanowires of a length example of 15 μm applied to an integrated circuit 1900 with a trace spacing of 12 μm in the nanowire deposition region. Line 2002 represents the probability of an open circuit. Line 2004 represents the probability of an individual nanowire forming a conductive path between conductive traces. Line 2006 represents the probability of more than one nanowire forming a conductive path between conductive traces. As shown by line 2004 in FIG. 20A , for a trace spacing of 12 μm, and for nanowires with an average length of 15 μm, the maximum probability for a single nanowire forming a conductive path between conductive traces is around 0.35, after applying Nanowire solution in the range of 0.3-0.4 nanowires/length, where:

Nanowire/length (1 μm) = density of nanowires in nanowire solution (1/μm ² )×electrical contact width (μm).

FIG. 19D shows another example of integrated circuit 1950, which may be an example of integrated circuit 1820. As shown in Figure 19D, a portion 1802 of the integrated circuit 1950 is covered by the channels of the fluid mask. FIG. 19E shows a close-up view of a portion 1960 of integrated circuit 1950 . FIG. 19F shows a schematic view of a portion 1960 after deposition of nanowires 1910 in nanowire region 1810 by manipulating fluid mask 1500 . After fluid mask 1500 is operated, nanowires 1910 are positioned to form electrical connections between individual ones of conductive traces 1952 of integrated circuit 1950 as shown in FIG. 19F . For example, nanowire 1910a forms a connection between trace fingers 1954 and 1956 .

FIG. 20B shows a curve 2050 similar to curve 2000 related to FIGS. 19D-19F . Line 2052 represents the probability of a single nanowire forming a conductive path between conductive traces/electrodes. Line 2054 represents the probability of more than one nanowire forming a conductive path between conductive traces. As shown by line 2052 in FIG. 20B , for a trace spacing of 4 μm, and nanowires with an average length of 15 μm, the maximum probability of a single nanowire forming a conductive path between conductive traces is around 0.06, at an applied on the order of 0.05 nanowires/length of the nanowire solution. By varying the electrical contact spacing, nanowire length, and/or other parameters, the probabilities shown in Figures 20A and 20B can be varied and optimized for a particular application.

Note, for example, that the aforementioned integrated circuits may be any type of integrated circuit device for use in a final product. Alternatively, these integrated circuits could be used to test fabricated nanowires. For example, nanowires can be placed on integrated circuits (or other circuit types) using the fluid masks of the present invention to test whether the nanowires are sufficiently conductive, measure the impedance of the nanowires, and/or measure other electrical/mechanical properties of the nanowires. Attributes. For example, two-point and four-point test probe devices can be used to measure nanowires on integrated circuits. For example, the integrated circuit 1950 of Figure 19D may be used in a four test probe system. Test probes may be coupled to the two pads near the outer edge of the integrated circuit 1950 to test the nanowires coupling the traces corresponding to the two pads together. A pair of probes that measure resistance or other parameters between the pads can be coupled to the pads due to the nanowires while the other pair of probes is used to deliver the test current. In the same manner, the integrated circuit of Figure 19A can be used in a two test probe system, where the traces shown in Figure 19C are coupled to ground or other reference potential. Alternatively, integrated circuits 1900 and 1950 may be used as electronic devices with nanowires flowed over them to make electrical connections, diodes, transistors, and the like.

FIG. 21 shows a flowchart 2100 providing an example of steps for positioning nanowires on a target surface using a fluid mask according to an example embodiment of the invention. Other structural and operational embodiments will be apparent to those skilled in the art based on the following discussion, and the steps are detailed below.

The process 2100 starts at step 2102 . In step 2102, a fluid mask is mated to a target surface. For example, in an embodiment, the fluid mask is the fluid mask 1500 shown in Figures 15A and 15B. As shown in FIG. 16A , first surface 1504 of fluid mask 1500 mates with target surface 1602 .

In step 2104, a liquid containing a plurality of nanowires is flowed through at least one channel in the surface of the fluid mask. For example, as shown in FIGS. 17A and 17B , the liquid containing a plurality of nanowires is a nanowire solution, such as nanosolution 1650 . As shown in FIG. 17A , nanowire solution 1650 flows through fluid mask 1500 in the direction of flow 1702 . Nanowire stream 1702 flows through one or more channels, such as channels 1506a-e shown in fluid mask 1500 of FIG. 15A. As shown in Figure 18A, channel 1506 covers portion 1802 of the target surface instance.

In step 2106, the nanowires contained in the liquid flowing through the at least one channel are allowed to be disposed on the portion of the target surface covered by the at least one channel. For example, nanowires are allowed to be disposed on target surface 1602 from stream 1702 as represented by arrow 1710 in FIG. 17B . In an embodiment, the nanowires disposed on the target surface 1602 form at least one electrical connection between conductive structures on the target surface 1602 . In embodiments, the nanowire density in the nanowire solution may be selected to allow a sufficient number of nanowires to be disposed on the covered portion of the target surface to form an electrical connection.

In step 2108, flow of liquid through at least one channel is discontinuous. In this way, the nanowires are allowed to remain disposed on parts of the target surface. For example, as shown in FIG. 18B , nanowires remain disposed on portions of target surface 1602 , as shown by nanowire region 1810 .

In an embodiment, the flowchart 2100 may include an additional step in which the nanowires are immobilized (or bonded) on the target surface 1602 . For example, the nanowire solution can be cured on the target surface 1602, thereby bonding the nanowires to the target surface 1602. Alternatively, epoxy or other adhesive material may be added to the nanowires on the target surface 1602 to secure them thereto.

Spraying Nanowires on a Substrate

As mentioned above, techniques for positioning nanowires on substrates, especially on large area substrates, are desirable. One reason for this requirement is that it is very difficult or impossible to apply conventional photolithographic techniques to large area substrates.

According to embodiments of the present invention, nanowires are immobilized onto surfaces, including large area substrates, using sputtering techniques. The nanowires can be sprayed onto the surface to form electrical connections between electrodes, or for other reasons. The nanowires can be sprayed onto the electrical contacts on the surface, or the nanowires can be sprayed onto the surface first and then can be metallized or the electrical contacts formed directly thereon.

According to an embodiment of the invention, a jetting technique is used to direct a stream of nanowires to the indicated portion of the surface. For example, a nozzle is used to spray a solution of nanowires onto the surface, thereby positioning the nanowires on indicated portions of the surface. In an embodiment, the nanowires are positioned in alignment with each other using jetting techniques. In other embodiments, the sprayed nanowire solution is not aimed at the nanowires.

This section describes jetting techniques and example nozzle embodiments for placing and positioning nanowires on surfaces. The nanowires can be positioned through the nozzles on semiconductor wafers, electronic substrates, or any other surface used in electronic devices, electrical test structures, and any other devices or systems. The particular embodiments described herein are provided for purposes of illustration, not limitation. Alternative embodiments for nozzle/spray techniques will be apparent to those skilled in the art based on the teachings herein. These alternative embodiments are within the scope and spirit of the invention.

Figure 22 shows a block diagram of an exemplary nanowire jet application system 2200 in accordance with an embodiment of the invention. System 2200 includes nozzle 2202 , target surface 2204 , nanowire solution source 2206 , and nanowire solution conduit 2208 . The system 2200 can also have other structures, which are easily understood by those skilled in the art.

As shown in FIG. 22 , nanowire solution source 2206 contains nanowire solution 2210 . Nanowire solution 2210 is typically a liquid solution containing a plurality of nanowires. The composition of nanowire solution 2210 may be selected to optimize nanowire flow through solution conduit 2208 and/or nozzle 2202 onto target surface 2204 . For example, the viscosity of the nanowire solution 2210 can be selected to enhance nanowire flow onto the target surface 2204 . The composition of the nanowire solution 2210 may be selected according to the size of the nanowires in the nanowire solution 2210 . The target surface 2204 may be the surface of a wafer, the surface of a substrate, such as a macroscopic electronic substrate, or the surface of any other structure described herein or known.

Nanowire solution source 2206 provides nanowire solution 2210 to nozzle 2202 through nanowire solution conduit 2208 . Nanowire solution conduit 2208 may be any type of conduit for a fluid or solution, including tubes, pipes, and/or valves. It should be noted that in some embodiments, where nanowire solution source 2206 is directly coupled to nozzle 2202, nanowire solution conduit 2208 is not required.

Nozzle 2202 is coupled to nanowire solution source 2206 to receive a flow of nanowires. Nozzle 2202 directs and/or controls the flow of nanowires onto target surface 2204 . FIG. 23 shows a detailed view of a nozzle 2202 that outputs a stream of nanowires 2302 onto an exemplary target surface 2204 . In FIG. 23 , target surface 2204 is substrate 2306 supported by substrate carrier 2308 . The nozzle 2202 may have any number of one or more openings for providing a flow of nanowires onto the target surface 2204 . For example, nozzle 2202 may have one opening. Alternatively, as shown in FIG. 23, the nozzle 2202 may have a plurality of openings 2304a-e. Openings 2304 may be openings arranged in a row or column, may be openings arranged in a two-dimensional array, or may be arranged in any other manner. Additionally, opening 2304 may have any shape, including circular, oval, rectangular, or other shapes. The openings 2304 may be of any width, including widths within multiples of 10's and 100's of microns. For example, the size of opening 2304 may be used to indicate the size of a droplet of nanowire solution 2210 applied to target surface 2204 .

Controlled pressurization, aerosol, or jetting sources can be used to eject a stream of nanowires from the nozzle 2202 at a predetermined flow rate. The pressure required to eject the nanowires from the nozzle at a particular velocity can be determined on an application-to-application basis.

Figure 24 shows a plan view of a target surface 2204 with a plurality of nanowires 2402 positioned thereon as a result of application of the present invention. Nanowires 2202 are deposited from nanowire stream 2302 through nozzle 2203 . As shown in Figure 24, the nanowires 2402 are positioned on the target surface 2204 in a single, substantially uniform distribution of nanowires. Nanowires 2402 can be positioned over a single distribution area by using one opening 2304 in nozzle 2202 or by using multiple openings 2304 in nozzle 2202 with adjacent or Overlapping coverage area. Furthermore, the nanowires 2402 are positioned on the target surface 2204 in an aligned manner (ie, parallel to each other). In an embodiment, the nanowires 2402 are aligned with each other by using the nozzle 2202 . The nanowires 2402 can be aligned through the nozzle 2202, depending on the size of the opening 2304 in the nozzle 2202, the viscosity of the nanowire solution 2210, the size of the nanowires 2402, and other factors described herein. For example, a droplet of nanowire solution 2210 applied to target surface 2204 may have a surface tension aligned with nanowire 2202 .

Figure 25 shows a plan view of a target surface 2204 having a plurality of nanowires 2502 as a result of application of the present invention. Nanowires 2502 are deposited from nanowire stream 2302 through nozzle 2202 . As shown in FIG. 25, nanowires 2502 are positioned on target surface 2204 in a plurality of distribution regions 2504a-d. The nanowires 2502 can be positioned in the plurality of distribution regions 2504a-d by using one opening in the nozzle 2202 or by using a plurality of openings 2304 in the nozzle 2202, wherein the one opening 2304 is directed/moved so as to be in a plurality of non- Nanowires are deposited in overlapping regions, the plurality of openings 2304 having non-adjacent or non-overlapping coverage regions on the target surface 2204 . Furthermore, the nanowires 2502 are positioned in the target surface 2204 in an aligned manner (ie, parallel to each other). In an embodiment, the opening 2304 may be configured such that the nanowires are randomly aligned (ie, not necessarily parallel to each other) on the target surface 2204 .

Electrical contacts may be formed on target surface 2204 before or after nanowires 2402 are deposited through nozzle 2202 . FIG. 26 shows a plan view of the target surface 2204 of FIG. 24 with a plurality of electrical contacts 2602a-e formed thereon in electrical contact with the nanowires 2402 . The nanowires 2402 form electrical connections between adjacent pairs of electrical contacts 2602a-e. Electrical contacts 2602 may be any contact type. For example, adjacent pairs of electrical contacts 2602 may be anodes and cathodes. Alternatively, three adjacent electrical contacts 2602 may serve as the drain, gate, and source of the transistor.

Any type of nanowire described herein or known can be deposited using the jetting technique of the present invention. The density of the nanowires in the nanowire solution 2210 can be controlled to produce a desired density of nanowires deposited on the target surface 2204 . Furthermore, once the nanowires have been deposited on the target surface 2204 using jetting techniques, the nanowires/nanowire solution may be cured or disposed on the target surface 2204 by any means described herein or known. After the nanowires have been deposited on the target surface 2204, any processing for defining features in the nanowire film on the target surface 2204 may be used, including, for example, photolithography and cleaning techniques. Additionally, the target surface 2204 can be prepared/treated to enhance nanowire adhesion/attachment by any means described herein or known.

The size/diameter of the opening 2304 can be configured to enhance nanowire flow onto the target surface 2204, such as depositing the nanowires in an aligned manner. In an embodiment, the width of the one or more openings 2304 may be greater than or equal to the length of the nanowires to be spray deposited. Alternatively, the width of one or more openings may be less than the length of the nanowire. In an embodiment, the width of the opening 2304 may be in the range of 1 μm to 1000 μm, although widths outside this range may also be used, depending on the particular application. Additionally, opening 2304 may have any shape, including circular, oval, rectangular, or other shapes.

FIG. 27 shows a flowchart 2700 providing example steps for positioning nanowires on a target surface in accordance with an example embodiment of the invention. Other structural and operational embodiments will be readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 2700 begins at step 2702 . In step 2702, a nanowire solution is provided. For example, the nanowire solution is nanowire solution 2210, as shown in FIG. 22 . As noted above, in an embodiment, nanowire solution 2210 is a liquid solution containing a plurality of nanowires.

In step 2704, the nanowire solution is directed onto the target surface through at least one output of the nozzle. For example, FIG. 23 shows a flow of nanowires 2302 , including nanowire solution 2210 , directed onto target surface 2204 through openings 2304 a - e of nozzle 2202 .

In step 2706, the nanowires are attached to the target surface. For example, step 2706 may include a step where nanowire solution 2210 includes a curable material and is cured on target surface 204 . In an embodiment, an electrical charge may be applied to the target surface 2204, creating an electrostatic attraction that helps the nanowires adhere from the nanosolution 2210 to the target surface 2204 and remain in place during the application of the nanowire solution in step 2704. Charged polymers, chemicals, pigments, or reagents may also be applied to the surface. For example, a material can be applied to the substrate, resulting in a positively charged substrate. A positively charged substrate attracts negatively charged nanowires, such as silicon nanowires coated with an oxide (eg, _SiO2 ). Such as aminopropyltriethoxysilane (APTES), polylysine with positively charged amino groups, silane-containing amines or polymer-containing amines can be applied to the surface to produce this effect, e.g. silicon or other material substrates.

In an embodiment, step 2704 includes the step of aligning the nanowires substantially parallel to each other on the target surface. For example, Figure 24 shows a target surface 2204 having a plurality of nanowires 2402 disposed thereon in alignment with each other as a result of the present invention.

In an embodiment, step 2704 includes the step of directing the nanowire solution to overlapping portions of the target surface. For example, Figure 24 shows nanowires 2402 positioned in a distribution area. Alternatively, step 2704 may include the step of directing the nanowire solution to multiple non-overlapping portions of the target surface. For example, Figure 25 shows nanowires 2502 positioned on a target surface 2204 in a plurality of non-overlapping distribution regions 2504a-d.

In an embodiment, step 2704 may include the step of applying pressure to force the nanowire solution to flow through at least one output port of the nozzle onto the target surface.

In an embodiment, the target surface 2204 may be a very large surface, such as a large area macroscopic electronic substrate. In such embodiments, the target surface may be received as a continuous plate on a conveyor-type system or other substrate supply system. Thus, in an embodiment, process 2700 may include the step of adjusting the position of the plate relative to the nozzle. For example, the plate may be conveyed from rollers that are continuously fed through the nozzle 2202 . This relative movement between the nozzle 2202 and the target surface 2204 can be used to align the nanowires on the target surface 2204, for example.

Reduction of phonon scattering of electrons in nanowires by selection of nanowire semiconductor materials

Silicon is a suitable semiconductor material for nanowires, partly due to its compatibility within the semiconductor industry. However, silicon has defects where surface states (~10 ¹⁰ cm ^-2 ) prevail and there is a limit to the wire diameter of achievable nanowires needed to eliminate phonon scattering of electrons.

Thus, according to the present invention, alternative materials for making nanowires are disclosed. The materials described here have advantages including reduced nanowire phonon scattering and increased diameter range.

There are at least two ways to reduce or eliminate phonon scattering of electrons. To reduce or eliminate phonon scattering in nanowires, the energy separated between subbands of the nanowire material should be (1) greater than the phonon energy; and (2) greater than 3*K _b T, where K _b is Maxwell A constant (8.62×10 ^-5 eV/°K.), "3" is a predetermined coefficient, and T is the absolute temperature at which the nanowire device works. For operation at room temperature, (2) is usually the more stringent requirement since most semiconductor materials have phonon energies less than 3*K _b T _rt , where T _rt is room temperature and K _b T _rt = .0259eV, thus 3* K _b T _rt = 0.777.

Quantum confinement of electrons in a semiconductor material involves the confinement of electrons in subbands within the conduction band of the semiconductor material. Electrons in this material are confined to specific energy levels of subbands. However, electrons can move from one subband energy level to another. The spacing or energy difference between subbands can be calculated. For nanowire materials with an isotropic electron (or hole) effective mass m _eff , the energy separation between the ground state and the first excited state is given by:

$\mathrm{\&Delta;E}\&ap;\frac{8.9{\mathrm{<figure-callout\; id="2"\; label="h"\; filenames="HSB00000035644000361.png,HSB00000035644000423.png"\; state="\{\{state\}\}">h</figure-callout>}}^2}{{2\mathrm{<figure-callout\; id="2"\; label="m\; eff\; r"\; filenames="HSB00000035644000361.png,HSB00000035644000423.png"\; state="\{\{state\}\}">m</figure-callout>}}_{\mathrm{eff}}{r}^{}{}^2}$ Equation 1

in:

h = Planck's constant ÷ 2π

m _eff = effective mass of the selected semiconductor material; and

r is the radius of the nanowire.

Quantum confinement of electrons in semiconductor materials remains unchanged when electrons cannot scatter between subbands. However, phonon scattering in semiconductor materials scatters electrons between subbands of the semiconductor material, which can reduce the mobility of electrons in the nanowire. In order to maintain quantum confinement of electrons, phonon scattering of electrons in semiconductor materials must be prevented in order to prevent electrons from scattering between subbands. As described below, quantum confinement of electrons can be preserved by selecting a semiconductor material with a known effective mass _m and forming nanowires from this semiconductor material so as to have a diameter that prevents electrons from moving between subband energy levels due to acoustic self-scattering .

The effective mass m _eff of different semiconductors makes some of them more preferable than others for reducing or eliminating phonon scattering. Furthermore, nanowires with a smaller effective mass m _eff are allowed to have larger diameters. The larger diameter of the nanowires allows for better control during nanowire growth and provides additional strength to the nanowires.

By setting Equation 1 equal to Nk _b T _rt , the following equation can be formed which is used to calculate the maximum diameter of a nanowire fabricated from a semiconductor material having an effective mass m _eff , thus having a substantially reduced or eliminated Phonon scattering.

        等式2

Equation 2

in:

h = Planck's constant ÷ 2π

＝6.626×10 ^-34 J-sec÷(2×3.1416)

(or 4.14×10 ^-15 eV-sec÷2×3.1416)

= 1.0545×10 ^-34 J-sec (6.589×10 ^-16 eV-sec);

m _eff = effective mass of the selected semiconductor material;

N = predetermined coefficient;

K _b = Maxwell's constant = 1.38 x 10 ^-23 J/°K (8.62 x 10 ^-5 eV/°K); and

T = working temperature;

Wherein at room temperature, K _b T = 4.144×10 ⁻²¹ J (.0259 eV).

Thus, Equation 2 can be rewritten as:

$<span\; class="notranslate">\; =</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1.194</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; 10</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 47</span>}}}{{\mathrm{<span\; class="notranslate">\; N\; m</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}}}$

The predetermined coefficient N is a coefficient that may be chosen so as to provide statistical assurance regarding electron confinement and phonon scattering reduction. For example, the predetermined coefficient N may be chosen to have any value greater than zero. In an embodiment, the predetermined coefficient N is chosen to have a value greater than or equal to three. In another embodiment, the predetermined coefficient N is chosen to have a value greater than or equal to five.

Curve 2800 shown in FIG. 28 represents the maximum allowable diameter and effective mass m _eff of the semiconductor material. In the Y-axis of curve 2800 a normalized effective mass m _eff /m ₀ is shown for the maximum allowable diameter (nm) of the nanowires represented on the Y-axis. As shown by curve 2800, as the normalized effective mass m _eff /m ₀ decreases, the maximum allowable diameter of the nanowire increases. As the normalized effective mass m _eff /m ₀ decreases below 0.2, the maximum allowable diameter of the nanowires increases dramatically.

Table 2900 shown in FIG. 29 lists various exemplary semiconductor materials in first column 2902 . Listed in the second column 2904 is the effective mass of the semiconductor material of the first column 2902 , and listed in the third column 2906 is the energy gap of the semiconductor material of the first column 2902 . As mentioned above, semiconductor materials with relatively small effective masses m _eff are advantageous because they allow larger nanowire diameters. As an example of favorable choices in table 2900, GaAs, InSb (for infrared detectors) and InAs stand out, each of which has a relatively small effective mass m _eff , thus allowing relatively large nanowire diameters.

For example, applying the data of column 2904 to curve 2800 of FIG. 28, the maximum allowable diameter for silicon (Si) nanowires with substantially reduced or eliminated phonon scattering is ~6mn. For gallium arsenide (GaAs), the maximum allowable diameter of a nanowire with substantially reduced or eliminated phonon scattering is ~20mn.

Additionally, the data from table 2900 can be applied to Equation 2 to calculate the appropriate nanowire diameter for a particular semiconductor material. For example, as shown for GaAs in column 2904, m _eff /m ₀ equals .067, where m ₀ is the free electron residual mass (9.11×10 ⁻³¹ kg). This value is applied to Equation 2 as follows:

$<span\; class="notranslate">\; =</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1.194</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; 10</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 47</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0.67</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9.11</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; 10</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; )</span>}}$

$<span\; class="notranslate">\; \&Congruent;</span>\mathrm{<span\; class="notranslate">\; 8.07</span>}\mathrm{<span\; class="notranslate">\; nm</span>}$

in

m ₀ = remaining mass of free electrons = 9.11×10 ⁻³¹ kg; and

N=3.

Thus, for GaAs, diameters as high as 16.14 can be used with reduced or eliminated phonon scattering.

In this way, the nanowires can be used individually, or in groups/thin films where the nanowires are formed to have a diameter less than or equal to the maximum diameter determined for the semiconductor material of the nanowires, thereby allowing each nanowire to hold a substantial electronic Quantum confinement (i.e., essentially reducing or completely eliminating phonon scattering of electrons).

Also, in an embodiment, each nanowire may be formed to have a length less than or equal to (≦) a predetermined length, so that ballistic transport of electrons may be generated through each nanowire.

FIG. 30 shows a flowchart 3000 providing example steps for designing conductive nanowires with high electron mobility, according to an example embodiment of the invention. Other structural and operational embodiments will be readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 3000 begins at step 3002 . In step 3002, a semiconductor material is selected. For example, the semiconductor material can be selected from table 2900 of FIG. 29, or can be any other semiconductor material described or known herein.

In step 3004, the maximum diameter of the nanowire made of the selected semiconductor material is determined, providing fundamental quantum confinement of electrons. For example, the diameter can be selected by looking at curve 2800 of FIG. 28 or by calculating the maximum diameter using Equation 2.

In step 3006, a plurality of nanowires are formed from the selected semiconductor material, each nanowire of the plurality of nanowires being formed to have a diameter that is less than or equal to a predetermined maximum diameter.

Reducing phonon scattering of electrons in nanowires using doping strategies

According to the present invention, phonon scattering of electrons in nanowires can be reduced or eliminated by nanowire semiconductor doping strategies. The effect of doping (whether n-type or p-type) may affect the phonon scattering of electrons in the nanowire, as well as the physical strength of the wire. In embodiments of the present invention, as further described below, the semiconductor may be doped with electrons or holes as conduction carriers, thereby improving performance.

Most semiconductors have a degenerate band at the valence band maximum with heavy and light holes. The smallest energy separation between valence bands comes from heavy holes with larger effective masses. Thus, in preferred embodiments, the nanowires are constructed such that electrons are the conducting carriers in the nanowires, since the effective mass of the holes is greater than the effective mass of the electrons.

Nanowires are constructed to use electrons as conducting carriers, which can be achieved by directly n-doping the nanowires and/or applying a bias gate voltage on the p-doped wires. Table 3100 shown in FIG. 31 lists example III-V semiconductor type materials in column 3102 . Column 3104 contains the corresponding effective masses of electrons for the material of column 3102 . Columns 3106 and 3108 contain the corresponding effective masses for light holes and heavy holes, respectively, for the material of column 3102 . For all semiconductor materials listed in table 3100, the effective masses of electrons shown in column 3104 are less than the effective masses contained in column 3106 for light and heavy holes. As such, n-doping of nanowires made of these semiconductor materials will result in lower phonon scattering than p-doping.

Note that table 3100 listing III-V semiconductor type materials is provided for representational purposes, and that the present invention is applicable to semiconductor material types other than III-V semiconductor types.

In addition, the mechanical strength of n-doped silicon is greater than that of p-doped silicon, which is more favorable for selecting n-doping of nanowires than p-doping of nanowires. For further details, reference is made to B. Busham and X. Li, Journal of Material Research, Vol. 12, p. 54 (1997).

Alternatively, the nanowires can be doped with a p-type dopant material, and the nanowires can be configured such that electrons become conductive carriers. For example, a nanowire film incorporating p-doped nanowires can operate in reverse mode by applying a sufficient bias voltage to the nanowire film. This allows electrons to be used as conducting carriers in the p-doped nanowires, reducing or eliminating phonon scattering in the p-doped nanowires. For example, in transistor embodiments, a bias voltage may be applied to multiple nanowires as a gate bias for the transistors, thereby causing the nanowires to operate in a reverse mode.

Reduction of surface states in nanowires using core-shell materials

Another factor towards achieving increased electron mobility, including electron ballistic transport in nanowires, is the reduction of surface and bulk (ie, nanowire core) impurity scattering. Surface scattering is especially pronounced in nanowires, where large surface-to-bulk ratios exist.

Surface scattering can be reduced by forming an outer layer of the nanowires, such as by passivating annealing of the nanowires, and/or using a core-shell structure with the nanowires. For example, FIG. 3B shows an example of a nanowire 310 doped according to a core-shell structure. An insulating layer, such as an oxide coating, may be formed as a shell on the nanowire. Furthermore, annealing the nanowires in hydrogen (H ₂ ), for example, for silicon nanowires with an oxide coating, can greatly reduce the surface states. In another example, for nanowires with a compound semiconductor in the nanowire core, such as GaAs, the use of an AlGaAs (or the same compound for other compound semiconductor types) shell can effectively confine the electron wave function and serve to reduce the surface state.

In an embodiment, the core-shell combination is constructed to meet the following constraints: (1) the shell energy level should be higher than the core energy level, so that the conductive carriers are confined in the core; and (2) the core and shell materials should have Good lattice matching with few surface states and few surface charges.

It should be noted that in embodiments, the thickness of the shell and the wire diameter can be varied in order to increase carrier mobility and reduce surface states in the nanowire.

FIG. 32 shows a flowchart 3200 providing example steps for fabricating nanowires with reduced surface scattering, according to an example embodiment of the invention. Other structural and operational embodiments will be readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 3200 begins at step 3202 . In step 3202, a semiconductor material is selected. Any semiconductor material, including those described herein or known, can be chosen.

In step 3204, a plurality of nanowires are formed from the selected semiconductor material. For example, nanowires can be grown or formed from selected semiconductor materials.

In step 3206, the circumferential surface of each nanowire of the plurality of nanowires is coated with an insulating layer. For example, in an embodiment, the insulating layer may be a dielectric material. In another embodiment, the insulating layer may be an oxide. Each nanowire can be oxidized to form an insulating layer. In an embodiment, each oxidized nanowire may be annealed. For example, each oxidized nanowire can be annealed in an H2 environment to passivate the dangling bonds at the interface of the oxide layer and the non-oxidized portion of each oxidized nanowire. For example, silicon nanowires can be oxidized, resulting in an oxide layer of _SiO2 . In another example, nanowires formed from compound semiconductor materials may be oxidized in oxygen or an oxygen composition that is conductive to form an oxide on the material. For example, GaAs nanowires can be oxidized in an oxygen and arsenic environment, resulting in an oxide layer such as _{an As2O3} layer. Other compound semiconductor materials may also be oxidized, or oxidized in other ways.

FIG. 33 shows another flowchart 3300 providing example steps for fabricating nanowires with reduced surface scattering, according to an example embodiment of the invention. Other structural and operational embodiments will be readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 3300 begins at step 3302 . In step 3302, a semiconductor material is selected. Any semiconductor material, including those described or known herein, can be chosen.

At step 3304, a plurality of nanowires are formed from the selected semiconductor material. For example, nanowires can be grown or formed from selected semiconductor materials.

In step 3306, each nanowire of the plurality of nanowires is doped such that each nanowire includes a core-shell structure, where the shell is the doping of each nanowire surrounding the respective core of each nanowire. outer layer. For example, the nanowire is nanowire 310, as shown in Figure 3B. The doped outer layer is the doped surface layer 302 . In an embodiment, the effect of step 3306 is to substantially confine the charge carriers of each nanowire to the axially disposed core during operation.

In an embodiment, step 3306 may include selecting a dopant material for the doped outer layer of each nanowire such that the doped outer layer will have an energy level higher than that of the respective core.

In an embodiment, step 3306 may include a step wherein the dopant material is selected for the doped outer layer such that the lattice structure of the doped outer layer substantially matches the lattice structure of the core.

Nanowires and Nanowire Thin Film Transistors

Figures 34A-34C represent concepts involving high mobility nanowire and nanoribbon TFTs. FIG. 34A shows an amorphous (a-Si) or polysilicon (poly-Si) TFT. As can be seen from Figure 34A, electrical carriers have to cross multiple grain boundaries, resulting in low carrier mobility. Fig. 34B shows a NW-TFT according to an embodiment of the present invention. Unlike a-Si or poly-Si, where carriers have to cross multiple grain boundaries resulting in low mobility, NW-TFTs have a conductive trench formed by multiple single-crystal NW paths in parallel (similar to logic bridges) road. In this way, electrons/holes travel with high mobility within the single crystal in all paths from source to drain. Also, as shown in FIG. 34C , according to an embodiment of the present invention, a single crystal semiconductor nanoribbon having characteristics similar to a plurality of parallel nanowires can also be used to fabricate a TFT with high performance.

Fabrication of NW-TFT devices

FIG. 35A shows a flowchart 3500 providing example steps for fabricating a NW-TFT in accordance with an embodiment of the present invention. Other structural and operational embodiments will be readily apparent to those skilled in the art based on the following discussion. These steps are described in detail below.

Flowchart 3500 begins at step 3510 . In step 3510, single crystal nanowires are synthesized. For example, p-type silicon nanowires with controlled diameters can be synthesized by decomposing SiH ₄ and B ₂ H ₆ in a guided fabrication metrology reactor using gold colloidal particles (eg, available through British Biocell International) as catalysts. In an exemplary embodiment, growth may be performed at a temperature between 420-480° C., using a total pressure of 30 Torr and a silane partial pressure of about 2 Torr, for a growth time of 40 minutes. The ratio of _SiH4 and _B2H6 can be _varied in order to control the doping level. A ratio of 6400:1 was used when synthesizing the nanowires, and this value will be measured below, although other ratios could also be used. In an exemplary application of step 3510, nanowires synthesized by this process have lengths in the range of 20-40 μm, with nearly monodisperse diameters determined by Au colloidal particles. In the presently exemplified application, the synthesized nanowires have a core-shell structure with a monocrystalline silicon core surrounded by an amorphous silicon oxide shell with a thickness of 2-3 nm.

In step 3520, the nanowires are suspended in solution. In an example embodiment, sonication can be used to transfer the synthesized nanowires into ethanol, resulting in a stable nanowire suspension. Alternatively, the nanowires can be delivered to and suspended in other suitable solution types.

In step 3530, the nanowires are assembled into a thin film. In this example, after dispersion into solution, the nanowires were assembled onto a selected substrate using a fluid flow directed in an alignment method, resulting in an aligned nanowire film. The nanowire suspension was allowed to pass through the fluidic channel structure formed between the polydimethylsiloxane (PDMS) mold and the flat substrate surface, thereby obtaining NW arrays on the surface. The average NW space in the film is controlled by changing the NW concentration in the solution and/or the total flow time. With this approach, alignment can easily be extended over 4 inch wafers or even larger areas by using longer or larger flow channel dies. An example of such a fluid channel structure is as described above as a fluid mask 1500 as shown in Figures 15A and 15B.

Figure 35B shows an optical micrograph of an exemplary nanowire film with a monolayer of parallel oriented nanowires and an average nanowire spacing of approximately 500-1000 nm. The micrograph of Figure 35B also shows that several nanowires intersect at the top of the nanowire film, although in alternative embodiments, the film can be made without nanowires intersecting at the top of the nanowire film. The scale bar shown in Figure 35B is 100 [mu]m long. Inset 3502 in Figure 35B provides higher magnification and includes a 20 μm scale bar.

In step 3540, a thin film transistor device is fabricated. A thin film transistor device incorporates the nanowire thin film fabricated in step 3530 . Any type of thin film transistor device can be fabricated.

In step 3550, thin film transistor devices are integrated for specific macroelectronic applications. In an exemplary embodiment, standard photolithographic or E-beam printing processes can be performed on NW films to define source and drain electrodes and fabricate TFTs on macroelectronic substrates.

Fig. 35C shows an exemplary TFT in which the scale bar is 100 µm. Different materials can be used for these electrodes, including gold electrodes, which are shown in Figure 35C for an exemplary TFT device, and serve as light-band color rods. For the Curie TFT 3504 shown in the inset in FIG. 35C , a back-gate device structure on a silicon substrate is shown. The underlying silicon is used as the back gate, 100nm thick silicon nitride (SiN _x ) is used as the gate insulating material, and Ti/Au (60nm/60nm) films deposited using an e-beam evaporator are used as the source and drain pole.

Figure 35D provides an optical photograph of a NW-TFT showing a parallel array of NWs bridging source and drain electrodes 3506 and 3508. The scale bar in Figure 35D is 5 μm long.

Step 3560 is the end step of flowchart 3500 .

Performance Characteristics - P-Channel Silicon Nanowire Thin Film Transistor (NW-TFT)

In the following examples, electrical characterization of NW-TFTs was performed in air environment, in a dark box and at room temperature. Figure 36A shows a graph of drain current (I _DS ) versus drain-source bias (V _DS ) at varying gate voltages (V _GS ) in steps of 1 V starting with The upper curve for V _GS = -10V. In this example, the TFT consists of ninety-one substantially parallel 20 nm diameter nanowires and has a 5 μm channel length. Figure 36A shows the behavior of a typical p-channel transistor operating in accumulation mode as the drain current I _DS increases linearly with V _DS at low V _DS and tends to saturate at higher V _DS . By applying a negative gate voltage, the leakage current increases as the main carriers (holes) increase in the channel. Applying a positive gate bias depletes the holes in the channel and turns the device off.

The I _DS vs. V _GS curve at V _DS =-1V shown in FIG. 36B shows that no current flows when the gate voltage is more positive than the threshold point, and that I _DS increases approximately linearly when the gate voltage increases in the negative direction. A linear extrapolation of the linear region results in a threshold voltage of 0.45V. Inset curve 3602 shown in FIG. 36B represents -I _DS versus V _GS at V _DS =-IV plotted on an exponential scale. Figure 36B highlights an on-off ratio close to ¹⁰⁸ and a sub-threshold swing of about 500 mV/s. The linear profile data was collected at a V _GS scan rate of 500 mV/s and the exponential profile data was collected at a V _GS scan rate of 15 mV/s to minimize capacitive loading current at higher gate voltages. The apparent threshold voltage in the inset curve is shifted to 3.5 V due to hysteresis effects.

The hysteresis effect is generally observed in the I _DS -V _GS of the current of the NW-TFT. This hysteresis effect can be eliminated or minimized by tightly controlling the NW synthesis and device fabrication processes, thereby minimizing ionic contamination. Hysteresis plays a role in determining the threshold voltage. Due to hysteresis effects, the apparent threshold voltage can vary depending on the measurement conditions and the voltage history experienced by the device prior to measurement.

To minimize threshold voltage variation due to hysteresis effects, devices were tested using the same conditions (using a relatively very large gate voltage sweep speed of 500 mV/s to minimize the effect of mobile ions). Voltage history variation can also be minimized by first cycling the gate voltage (from 10 to -10V) at least three times before collecting data for each device. In this way, the proper threshold voltage distribution can be determined (FIG. 36B primarily plotted and FIG. 36C). On the other hand, in order to accurately measure the off-state current, a slower gate voltage sweep speed (15mV/s) is used to minimize the capacitive current. In this case, the device experienced a high positive gate voltage for an extended period of time (approximately 5-10 minutes) and shifted the apparent threshold towards a corrected value (inset Figure 36B).

For macroelectronic applications, a number of key transistor parameters characterize TFT performance, including transconductance, mobility, on/off current ratio, threshold voltage, and subthreshold swing. High transconductance is important for transistor performance and for the voltage gain of transistor-based devices, including amplifiers and logic circuits. The slope in the linear region of -I _DS vs. V _GS represents a transconductance of about 11 μS at V _DS =-1V, g _m =dI _DS /dV _GS . Assume that the effective channel width is equal to the NW diameter d multiplied by the number N, ie NWs:W _eff =N·d=1.8 μm. Comparing a-Si TFT and poly-Si TFT, a normalized transconductance of about 6 μS/μm can be obtained. This is significantly better than the transconductance of amorphous silicon TFT and p-channel poly-Si TFT, where the transconductance of amorphous silicon TFT is about 0.01 μS/μm,

The transconductance of p-channel poly-Si TFT is about 0.3 to 0.8 μS/μm. Furthermore, this is comparable to the transconductance of a monocrystalline p-channel silicon-on-insulator (SOI) MOSFET, which is about 5-12 μS/μm. It should be noted that using thinner dielectrics with higher dielectric constants can further improve the NW TFT transconductance.

Additional simulations were performed using standard MOSFET equations to further evaluate the carrier mobility in the NWTFT under study. In the low-bias linear region of the _IDS - _VGS curve, the hole mobility _μh can be derived from the following equation:

G _DS =I _DS /V _DS =μ _h C _G (V _GS -V _th -V _DS /2)L ² ,

where C _G is the gate capacitance, and

L is the channel length.

The gate capacitance includes the capacitance of the SiN _x dielectric on the substrate and the capacitance of the silicon oxide shell. However, calculating these capacitances is non-trivial. Simulations using a 3D finite element package (eg, Metamesh from FieldPrecision, http://www.fieldp.com) yielded a total capacitance of approximately 27 fF, resulting in a hole mobility of approximately 130 cm ² /V·s. This hole mobility is higher than the best value reported for p-type polysilicon (approximately 12 cm ² /V·s) and comparable to the hole mobility of p-type single crystal materials such as SOIMOSFET (approximately 180-250 cm ² /V·s). In addition, it is feasible to further increase the carrier mobility, for example, by reducing the doping level and/or minimizing the trapping states on the NW surface.

The inset curve 3602 in FIG. 36B represents an exponentially scaled I _DS -V _GS plot showing that the leakage current decreases exponentially below the threshold voltage and the transistor has an on-off current ratio close to 10 ⁸ . This is expressed as the largest on-off ratio reported for transistors assembled from chemically synthesized nanomaterials and is comparable to that of single crystal silicon devices. The exponential drop in current defines a key transistor parameter, the sub-threshold swing S=-dV _GS /dIn|I _DS |, which in such a device would be about 600mV/decade. In a conventional MOSFET, S is determined by S=(k _B T/e) Ln{(10)(1+α)}, where T is the temperature, k _B is Maxwell's constant, e is the element charge, and α depends on the device and when the gate capacitance is much larger than other capacitances such as the interface trap state capacitance, α is 0. So the lowest theoretical limit for S is S==(k _B T/e)·Ln {(10), or about 60 mV/decade at room temperature.

In general, for low threshold voltage and low power consumption, a small sub-threshold swing is desired. In an embodiment of the NW device of the present invention, the sub-threshold swing of about 600 mV/decade is significantly better than conventional amorphous Si TFTs or organic semiconductor TFTs, which typically range from 1 to many volts/decade. Furthermore, this is comparable to most poly-SiTFTs, which at the time were substantially larger than the best poly-SiTFTs (about 200mV) and monocrystalline silicon devices (about 70mV).

The observed relatively large sub-threshold swing of the NW devices of the present invention may be mainly due to the presence of surface trapping states and geometric effects, which can be achieved by passivating the surface (e.g., hydrogenation or using a core-shell structure) and/or using a top-gate type Or around the gate structure to significantly improve.

Geometric effects arise from NWs intersecting other NWs in NW-TFTs. NW films are usually composed of nearly monolayer NWs, but occasionally several NWs intersect on other NWs. When a NW intersects other NWs, it separates from the substrate surface, experiences a smaller electric field from the back gate, and thus turns on or off more slowly than other NWs in the device. This increases the sub-threshold swing of the NW-TFT as a whole. Needless to say, and importantly, subthreshold swings as small as about 70 mV/decade have been demonstrated using surrounding conformal electrolytic gates, as described below.

In practical applications, the variability of threshold voltage across individual devices is a key factor in determining technological variability. To this end, tests were performed on 20 individual devices fabricated according to an embodiment of the present invention. Figure 36C shows a histogram of the threshold voltage distributions for these devices. Gaussian matching means a standard offset of only 0.22V. In addition, optimization of structures and manufacturing processes may result in tighter distributions.

Specifically, the performance of NW-TFTs can be further improved in many ways by developing various NW core-shell structures. First, in NW-TFTs on plastic, the on-off ratio is limited by the low amount of e-beam evaporated _AlOx gate dielectric. This problem can potentially be overcome by using a core-shell NW structure consisting of a single crystal semiconductor core and a high-quality gate dielectric shell. Although SiNWs generally have a core-shell structure, the thin native oxide layer is not of high enough quality to withstand high electric fields. The native oxide may be replaced or supplemented by a shell of high quality silica produced by controlled thermal oxidation, chemical vapor deposition, or other suitable techniques. The core-shell NW structure is well suited for fabricating high-performance NW-TFTs on plastic because high-temperature processing, including semiconductor material synthesis and high-quality gate dielectric formation, is performed separately from the final device substrate. In addition, this core-shell structure can also lead to the passivation of surface trapping states, further enhancing the performance.

Second, current back-gate NW-TFTs are relatively limited in performance due to geometric effects. This geometric effect can be overcome by using a more complex NW core-shell structure comprising a core of monocrystalline semiconductor, an inner shell of the gate dielectric and an outer shell of the conformal gate. This can be achieved, for example, by depositing a layer of highly doped amorphous silicon as an outer gate shell around the Si/ _SiOx core-shell structure (described above).

Third, the performance of NW-TFTs can be further potentially enhanced by exploiting quantum electronic effects in small-diameter NWs, thereby surpassing those of single-crystal materials. In simulations of conventional two-dimensional semiconductor superlattices and 2D electron/hole gases, multiple core-shell NW structures can be imagined to separate dopants from active conducting channels for ultrahigh-mobility TFTs.

The main parameters of device performance, such as carriers and threshold voltage, are related to the number of NWs in the conducting channel. In this way, the design and manufacture of NW-TFTs with predetermined characteristics is feasible. For example, by changing the number of NWs in the conducting channel (changing the effective channel width), NW-TFTs can be designed and fabricated to carry current at a predetermined level. Figure 36D shows the linear dimension relationship of the drain current when the device is on ( _Vgs = -10V). Both curves represent on-state current as a function of effective channel width. The lower curve has V _DS =-1V and the upper curve has V _DS =-8V. The effective channel width corresponds to the product of the average diameter of NWs and the number of NWs. As expected, the on-state current varies linearly with the effective width (number of NWs in the conducting channel). On-state currents greater than 0.5 mA have been achieved with devices having effective channel widths less than 5 μm. Remanufacturable and predictable assembly of NW-TFTs with designed device parameters is important.

NW-TFT on plastic

An important scheme of the current NW thin film concept is that the entire NW-TFT fabrication process can be mainly performed at room temperature, except for the NW synthesis step, which is separated from the device fabrication. Therefore, assemblies of high-performance NW-TFTs are easily applied on low-cost glass and plastic substrates. To demonstrate NW-TFTs on plastic substrates, different device structures were used. Figure 37A shows the device structure. To fabricate the device of Figure 37A, a 1-2 μm thick SU-8 (MicroChemCorp.) photoresist layer was first spun onto a polyether ether ketone (PEEK) plate (50 or 100 μm thick, Goodfellow) and cured, This ensures a microscopically smooth surface. Cr/Au (10/30nm) strips are defined as the gate array, and a 30nm layer of aluminum oxide is deposited as the gate dielectric using e-beam evaporation. Aligned NW films are deposited on the surface and define Ti/Au (60/80nm) source-drain electrodes to form TFTs. Fig. 37B shows an example of a plastic device with NW-TFT. The lower part of FIG. 37B represents the source, gate and drain of an NW-TFT with a scale bar equal to 5 μm.

Electrical transport characterization was performed in the same manner as above. Figure 37C shows the I _DS -V _DS curves showing the same behavior as the devices on SiNx/Si land. The graph of Figure 37C represents the I _DS -V _DS relationship, where V _GS is variable and starts at V _GS = -8V and increases in 1V steps. The IDS-VGS relationship indicates a threshold voltage of approximately 3.0V and an on-off ratio greater than 10 ⁵ .

Figure 37D shows the transfer characteristics of the same device before and after slight bending of the plastic substrate. Inset 3702 of FIG. 37D highlights an on-off ratio greater than ¹⁰⁵ and a sub-threshold swing of 500-800 mV/decade. The device under test has 17 NWs with a diameter of 40 nm parallel to a channel length of 6 μm and a gate length of 3 μm. The two curves represent the transfer characteristics of the same device before and after slightly bending the plastic substrate (with a radius of curvature of about 55 nm), demonstrating the mechanical flexibility of the NWTFT on plastic.

The relatively small on-off ratio (compared to _SiNx /Si substrate) is due to: (1) low on-current due to non-optimal local gate device structure; (2) impact by AlO evaporated by e-beam Higher off current limited by low gate leakage current caused by low quality of _x- dielectric; and can be significantly increased with improved device structure and advanced core-shell NW structure.

The reduced subthreshold swing is mainly due to two factors. First, the electrolyte produces an excellent conformal gate, thus eliminating or reducing any geometric effects that broaden the subthreshold swing. Second, with electrolyte conformal gates, the gate capacitance is more than an order of magnitude larger than that of back-gated devices (approximately 0.77pF vs. approximately 0.05pF for approximately 160 NW devices). Thus, the relative importance of the other capacitances is reduced compared to the gate capacitance, leading to a significant reduction in the value of α in S=(k _B T/e) Ln(10)(1+α), and thus sub The threshold swing S is also reduced.

The main motivation driving research in plastic electronics is mechanical flexibility. Importantly, slight bending of the plastic with NW-TFT devices does not significantly change the device behavior. As noted above, Figure 37D provides two curves representing this feature. As shown in Figure 37C, the linear region in the IDS-VGS relationship provides a transconductance of 0.45 μS at _VDS = -1V. However, it is difficult to evaluate the exact hole mobility in the device because it is difficult to evaluate the gate capacitance in a partially gated device structure.

To measure the carrier mobility and the final device performance of NW-TFTs on plastic, electrolyte-gated TFT structures have been tested. Fig. 38A shows the tested electrolyte gate type NW-TFT structure. This protocol was used to study individual carbon nanotube FETs. The test scenario performs the following steps. Place a droplet of 1 mM saline solution on the TFT device on the plastic substrate, covering the entire TFT device, including the source, drain, NW film, and additional isolated gold electrodes. A voltage _VGS was applied to the isolated gold electrode, thereby establishing an electrochemical potential in the electrolyte with respect to the NW-TFT device. For the voltage range less than ±0.9V, the leakage current between the electrolyte and the source and drain of the NW can be ignored. The electrolyte functions as a well insulating liquid gate. A particular advantage is that the electrolyte creates a useful surrounding conformal gate for all NWs in the TFT channel, reducing or eliminating undesired geometric effects and surface charges, thereby providing an efficient structure for testing the final performance of NW-TFTs .

Figure 38B shows the I _DS -V _DS relationship as a function of the respective electrolyte gate voltages in 0.1 V steps and starting at the top curve with V _GS = -0.9V. The tested NW-TFT consisted of 162 NWs of 20 nm diameter parallel to the 5 μm channel length.

Figure 38C shows the I _DS -V _GS relationship for a V _DS of 10 mV. Overall overall results are similar to those of TFTs fabricated on silicon substrates as described above. But, in this device in particular, the drain current I _DS is more responsive to changes in the electrolyte gate voltage. The subthreshold swing was also significantly reduced (70-110 mV/10), as shown in inset 3802 of Figure 38C. The I _DS -V _GS relationship is determined using a lock-in amplifier (eg, available through Stanford Research). For this measurement, a 10-Hz sine wave at 10-mVRMS amplitude was used.

Furthermore, the particular configuration of the solution gate experiments may underestimate the performance of ideal devices, since the source and drain electrodes are also in contact with the solution. The source and drain potentials can affect the actual solution potential and compromise the electrochemical potential established by the gate, reducing the actual applied potential around the NW below the voltage applied to the gate. Thus, with improved schemes (eg, using a standard reference electrode) to establish the gate potential, even smaller sub-threshold swings can be achieved. At the same time, the results confirm the potential for high performance for TFTs on plastic, which can be improved by further optimizing the gate structure of these devices (for example, solid-state surrounding conformal gates can be realized in multi-core-shell NW structures, The core-shell NW structure consists of a single crystal semiconductor core, an inner shell of a gate dielectric, and an outer shell of a conformal gate).

The performance of electrolyte-gated TFT devices on plastic can be further analyzed by examining individual properties of the device features. Check the gate capacitance first. In this case, the total capacitance includes the series capacitance of the electrolyte capacitance and the NW case oxide capacitance, although the former can be ignored since the former is much larger than the latter. Consider a NW with a single crystalline core of 20 nm and an amorphous silicon oxide shell of about 2.5 nm on average. The gate capacitance can be evaluated by the following process: C _G =2Nπεε ₀ L/ln(1+t _ox /r), where N is the number of NWs in the channel, ε and t _ox are the dielectric constant and thickness, r is the radius of the NW. Based on the calculated capacitance and the following relationship: G _DS =I _DS /V _DS =μ _h C _G (V _GS -V _th -V _DS /2)/L ² , the hole mobility μ _h can be determined to be approximately 150 cm2/ V·s. This result is consistent with the mobility obtained for the same device on _SiNx /Si substrate with the same NW. This indicates that the mobility of the NW-TFT is intrinsic to the NW itself and is not significantly affected by the plastic substrate or the electrolyte gate.

N-channel CdS nanoribbon TFT

The above discussion confirms that high-performance NW-TFTs can be assembled from p-type SiNWs on low-temperature plastic substrates. Furthermore, since NW synthesis is relative to the final device substrate, a wide range of materials including III-V and II-VI semiconductors can be developed as TFT channel materials, yielding a wide range of opportunities. As an example, high-performance TFTs can also be easily assembled from II–VI cadmium sulfide (CdS) nanoribbons. CdS is an intrinsically low surface trapping state. Single-crystal CdS nanoribbons with a thickness of 30–150 nm, a width of 0.5–5 μm, and a length of up to 10–200 μm were synthesized using the vacuum vaporization transport method.

Specifically, a small amount of CdS powder (approximately 100 mg) was transferred into one end of the vacuum tube and sealed. The vacuum tube was heated so that the end with the CdS was kept at 900°C, while the other end of the vacuum tube was kept at a temperature below about 50°C. Within two hours, most of the CdS was transported to the cold end and deposited on the tube walls. The obtained material is mainly nanoribbons with a thickness of 30-150 nm, a width of 0.5-5 μm and a length of 10-200 μm. TEM images indicate that the nanoribbons are single crystals with low defects all the way to the edge surfaces.

Nanoribbons can be used in TFTs because their unique physical form resembles that of conventional single-crystal thin films. CdS nanoribbon TFTs with single-crystal conducting channels were fabricated using a scheme similar to that described above. Figure 39A shows a CdS nanoribbon TFT. Inset 3902 of Figure 39A represents a 3D atomic force microscopy topography image of a nanoribbon TFT.

Electrical transport measurements for CdS nanoribbon TFTs indicative of typical n-channel transistor characteristics. The n-channel behavior is consistent with previous studies on CdS bulk materials and NWs. Figure 39B provides the I _DS -V _DS relationship at different gate voltages for CdS nanoribbon TFTs. Figure 39B shows the linear region at low source and drain biases and saturation at higher biases. The I _DS -V _GS relationship at a V _DS of 1V shows approximately linear behavior above a threshold V _GS of 2.0V. The slope in the linear region provides a transconductance of about 2.4 μS/μm at VDS=1V. Assuming a parallel plate model, the gate capacitance is calculated as 1.9fF using C _G =εε ₀ L·W/h, where L and W are the channel length and width, respectively, and h is the dielectric thickness. Using the calculated capacitance, an electron mobility of approximately 300 cm ² /V·s can be deduced using I _DS /V _DS = μ _e C _G (V _GS −V _th −V _DS /2)/L ² . Importantly, this mobility value roughly matches that of single crystal CdS (approximately 300-350 cm ² /V·s).

In addition, the exponential curve of IDS-VGS provides an on-off ratio greater than ¹⁰⁷ and a subthreshold swing S as small as 70mV/10, as shown in Figure 39C and its inset, which is close to the theoretical limit of 60mV/10. The high carrier mobility and small carrier threshold swing observed in CdS nanoribbon TFTs are largely attributable to the high crystal quality and low surface states in these materials and the absence of geometric effects as in Si NW-TFTs.

compensation logic

The ability to fabricate p- and n-channel TFTs is key to building compensation electronics, which are known to outperform circuits constructed from p- or n-channel transistors. For this purpose, a compensation inverter (logic M, NOT gate) is constructed by connecting n-channel and p-channel TFTs in series. The compensating inverter was formed by connecting p-channel SiNW-TFTs (composed of 15 NWs in parallel) and n-channel CdS nanoribbon TFTs in series. Device 4002 is shown in FIG. 40 . Figure 40 also provides the output-input ( _Vout - _Vin ) voltage response of the inverter and represents a constant high voltage output with a low input. When the input increases to approximately 1.5V, the output quickly goes to 0V and remains low at higher input voltages. Most notably, the compensated inverter exhibits high voltage gain. The difference in the measured V _out -V _in relationship represents a voltage gain as large as 27, as shown in inset 4004 in FIG. 40 . This large gain demonstrates the high performance of our devices and is critical for the interconnection of logic circuit arrays for various large-area electronic applications, while not requiring signal recovery at every stage. Finally, it should be noted that the V _out -V _in relationship of the inverter was measured without any load on the output. The gain may decrease when the device is loaded in an actual circuit. However, given the reproducibility and predictability of the NW-TFT devices described herein with the characteristics shown in Figures 36A-D, with careful device/circuit design, it should be possible to achieve the desired voltage gain in practical applications.

NW-TFTs in displays and other applications

Over the past two decades, flat panel displays (FPDs) have become more mundane in modern electronics. FPDs are indispensable in many new products, including cellular phones, personal digital assistant systems, digital cameras, camcorders, and notebook computers. Furthermore, the market is expected to expand greatly as FLDs are balanced to replace desktop computers and television (TV) cathode ray tube (CRT) displays. Active Matrix Liquid Crystal Displays (AMLCDs) are the predominant commercial flat panel display technology, dominating roughly the entire large area flat panel display market. AMLCDs are also sometimes referred to as active-matrix thin-film transistors (AMTFTs), because large-area thin-film transistors are the key technology enabling today's AMLCDs.

The thin film transistor (TFT) was invented 13 years before the point contact junction transistor. The first US patent on TFT was issued by Lilienfield in 1933. Until the early 1960s, many industrial research laboratories, including GE, RCA, IBM, Zenith, Westinghouse, and Philips, effectively coordinated TFT research and development. However, around the mid-1960s, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) appeared and came into focus. Soon, major industrial laboratories invested in TFT research and development. Since most semiconductor technologies today, including MOSFET technology, are single crystal wafer based, the dimensions of the substrate are determined by the dimensions of the available wafers. To date, the largest wafer available is ~12". Therefore, this substrate size is unlikely to be suitable for applications requiring large substrate areas.

Interest in TFT technology was revived in the mid-1980's with the advent of liquid crystal displays (LCDs), especially AMLCDs, which required drive circuits on large glass substrates. Early efforts for TFTs focused on II-VI semiconductor materials. The technique has barely made it beyond the research lab because of the difficulty of controlling II-VI semiconductor materials. For example, in general, it is more difficult to form a crystal phase of a compound semiconductor than an element. Furthermore, doping of II-VI materials such as CdSe is difficult. It is also very difficult to deposit reliable dielectric materials on II-VI materials.

Meanwhile, hydrogenated amorphous silicon (a-Si:H) thin films have attracted great attention because of their potential applications as materials for solar cells and malicious imaging sensors. A shift occurred in 1975 when W.E. Spear and P.G. LeComber demonstrated that amorphous silicon materials could be doped. Soon, a-Si:H based TFTs became the driver element of choice for AMLCDs despite poor transistor performance. The technology is used almost exclusively in today's large-screen commercial AMLCD displays. In AMLCD displays, a-SiTFTs are fabricated on a glass substrate under LCD pixels and used as switches that switch pixels on/off by receiving instructions from an integrated circuit (IC) driver circuit. IC driving circuits are mounted on the periphery of the substrate. A-Si thin film crystals can be easily deposited on relatively large glass substrates at low temperatures using plasma-assisted chemical vapor deposition. This low deposition temperature makes it possible to use inexpensive glass substrates. A glass substrate is necessary because substrate transparency is required for the backlighting technology used in this technology.

Typically the field effect mobility of a-SiFET is around ~1 cm ² /V·s, which limits the performance of the display. A great deal of effort has been devoted worldwide to research towards improving a-Si TFTs by crystallizing a-Si into polycrystalline thin films. The field-effect mobility of polysilicon TFTs lies between those of a-Si TFTs and single-crystal silicon transistors, and has been reported to have values as high as several hundred. Current polycrystalline processing usually requires annealing a-Si at 600°C for up to 24 hours in order to manufacture transistors with a mobility of 10-50 cm ² /V·s. In addition to direct thermal annealing, several methods have been investigated to convert a-Si films to polycrystalline, including rapid thermal annealing, laser-induced crystallization, and transition metal-induced annealing. Rapid thermal annealing uses higher temperatures from 700°C to 800°C for each time emission cycle. The short time period minimizes potential damage to the substrate. However, it is impossible to use an inexpensive glass substrate for this purpose. Laser annealing allows rapid heating of small areas of amorphous silicon to very high temperatures without significantly heating the substrate. Unfortunately, this method is ineffective for large-area fabrication due to the small beam size. Additionally, the process is very difficult to control.

Metal-induced crystallization has attracted much attention in recent years. A nickel-based process emerged. In general, nickel-based processes reduce the annealing temperature required for low heat treatment from about 600°C to between 500°C and 550°C, reducing the annealing time from ~24 hours to several hours. However, metal-induced crystallization requires an additional step to deposit transition metals on top of a-Si. Crystallization depends on the quality of the metal film. Residual metals, metal silicides, and structural defects in complex grain boundaries can lead to high leakage currents in transistors.

Multi-TFT is unlikely to replace a-Si technology because there is no viable polysilicon process compatible with cheap glass substrates. The performance of polysilicon TFTs is unlikely to solve these problems for devices fabricated from conventional monocrystalline silicon because of grain boundary conduction and the difficulty of preparing high-quality polysilicon. Therefore, currently available a-Si or p-Si based TFT technologies are limited from various points of view.

A new thin film transistor technology - the organic TFT - has attracted a lot of attention in recent years. Organic TFTs with field-effect mobilities as high as ~1 cm ² /V·s have been demonstrated. By virtue of their properties, organic transistors are compatible with low-temperature processing on plastic substrates, although most workpieces have been performed using glass or oxide-coated silicon as substrates. Unfortunately, however, the performance of organic transistors is currently nowhere near that of silicon. Therefore, the area of application of organic-based transistors is limited. Attempts to place silicon on plastic have not yielded satisfactory results, mainly because the temperatures required for two critical steps, silicon deposition and gate dielectric material deposition, are too high for plastic substrates, which have the highest glass transition temperatures. , unbearable, where the above two steps are even used to manufacture amorphous silicon transistors.

Breakthroughs in recent years in Prof.Charles Lieber's lab at Harvard University, basically by Dr. XiangfengDuan, the principal investigator of this program, have shown that semiconducting nanowires are excellent or ideal for nanoscale electronics and optoelectronics building blocks. Prof Lieber's lab has demonstrated that IV, III-V can theoretically be synthesized in single crystal form with controlled and tunable chemical composition, physical dimensions (e.g. diameter and length), and electronic properties (e.g. doping type and concentration) and a wide range of II-VI semiconductor nanowires. The diameter of the nanowires can be controlled and varied in the range of 2-100nm. The length of the nanowires is typically in the range of 10-100 μm ( FIG. 41 ).

Figure 41A shows a scanning electron micrograph of synthesized silicon nanowires according to an exemplary embodiment of the present invention. The nanowires of Figure 41A have diameters on the order of ten nanometers and lengths up to tens of microns. The scale bar shown in Figure 41A is 5 [mu]m long. Figure 41B shows a lattice decomposition transmission electron microscopy image of an individual Si nanowire according to an exemplary embodiment of the present invention. The nanowire example of FIG. 41B has a synthetically controllable single-crystalline core and an amorphous oxide capping layer, where the single-crystalline core has a continuous lattice along their entire length.

The elongated longitudinal dimension and reduced lateral dimension give nanowires the smallest size material for efficient transport of electrical carriers. Furthermore, nanowires can be flexibly manipulated in solution and assembled onto substrates using electric fields or microfluidic flow schemes, thus demonstrating various nanoscale electronic and optoelectronic devices and device arrays, including single nanowire field-effect transistors. (FETs), crossed nanowire FETs, and strings of logic circuits, such as logic OR, AND, NOT, NOR gates, and logic half-adder circuits and memory arrays, as well as light-emitting diodes, photodetectors, and highly sensitive chemical/biological sensors.

In particular, studies on single nanowire FETs have demonstrated field-effect mobility up to 1500 cm ² /V s for Si nanowires, ~1000 cm ² /V s for GaN nanowires and n-type InP nano The wires have field-effect mobilities of ~4000 cm ² /V·s, all mobilities comparable to or better than their single crystal counterparts with simple doping concentrations. The high mobility values and high brightness observed in the nanowire material show the high quality of this new material. Furthermore, it is believed that these observed mobility values represent only low values for nanowire materials, since little attention has been paid to surface passivation etc. and the mobility values can be greatly increased by passivating the nanowire surface. The study suggests that scattering events can be greatly suppressed due to modulation of quantum mechanical properties in doped one-dimensional wires. For example, theoretical calculations have predicted a mobility of 3×10 ⁸ cm ² /V·s for selectively doped GaAs nanowires. In this way, extremely high carrier mobility can be achieved if dopants are dissociated from the conducting channel (e.g., molecules doped from the surface of the nanowire or from the shell in core-shell nanowire structures). .

In conclusion, nanowires represent the building blocks for high-mobility thin-film transistors. Randomly oriented nanowire films have carrier mobility comparable to polycrystalline silicon film materials, and oriented nanowire films exhibit mobility values comparable to or superior to single crystal materials.

TFTs are key to the development of many modern electronic technologies. Currently, research and development on TFTs is driven by the flat panel display (FPD) market, dominated by active matrix liquid crystal displays (AMLCDs). New TFT technology - real silicon on cheap large-area glass or plastic substrates could revolutionize current FPD technology and open the door to new industries for manufacturing new types of electronic devices. According to the present invention, TFTs incorporating thin films of nanowires achieve what was previously unattainable.

Described here are thin-film transistors (TFTs) based on aligned semiconductor nanowires and formed on inexpensive glass or flexible plastic substrates, with comparable performance to transistors fabricated from single-crystal silicon:

Field Effect Mobility:

1500cm ² /V·s.

I _on /I _off =10 ⁷ .

Threshold <2.5V.

Generally, nanomaterials are used to reduce the size of electronic devices. However, embodiments of the present invention use nanomaterials to make electronic devices faster and/or larger. Despite the high mobility of individual nanowires, it is impossible for a single nanowire to provide sufficient current density required for macroscopic electronic applications. To take advantage of the high mobility of nanowires, transistors are fabricated with films of oriented nanowires such that many nanowires comprising hundreds or thousands of nanowires span between electrodes (eg, between source and drain). This enables high mobility and high current density transistors on large flexible substrates.

FIG. 42 shows a flowchart of a process for synthesizing and realizing a high mobility thin film transistor according to an exemplary embodiment of the present invention. High-mobility single-crystal nanowire materials are synthesized at high temperatures and then aligned on the desired substrate to form aligned nanowire films. Then it is further subjected to a photolithography process, thereby forming a thin film transistor with a conduction channel parallel to the axis of the line. A single-crystal conductive channel along the length of the nanowires ensures high mobility in the resulting TFTs.

In this scheme, according to an exemplary embodiment of the present invention, a silicon nanowire core-shell structure with a single crystal core and a dielectric capping layer (shell) can be fabricated, as shown in FIG. 43 . Nanowires were first synthesized by using the recently developed gold nanoparticle-catalyzed chemical vapor deposition (CVD) method and later direct oxidation. The method can be applied to various semiconductor nanowires, including silicon (Si) and gallium arsenide (GaAs). Silicon nanowires are referenced here for illustration purposes. Suspending the chemically synthesized nanowires in a solvent, such as ethanol, allows for later processing and handling. From these nanowire-suspended solutions, monolayer nanowire films were prepared with wires oriented substantially parallel to the substrate. Finally, metal contacts for the source, drain, and gate can be applied by photolithographic processing to fabricate nanowire TFT arrays with conductive channels parallel to the wire axis.

The present invention provides a fundamentally new strategy towards the development of high performance thin film transistors and leads to innovations in technology classes and processing, performance advantages:

Single crystal conduction channel: In the present TFT device, multiple nanowires exist in parallel in all paths from source to drain (similar to a logic bridge), thereby providing a single crystal conduction channel for carriers. This results in high carrier mobility comparable to bulk single crystal materials, which is not possible with amorphous or polycrystalline silicon materials. This is mainly due to prolonged trapping states near grain boundaries, leading to significant carrier depletion and grain boundary scattering near grain boundaries for these materials (see Figures 44A-44C).

44A-44C show schematic diagrams of thin film transistors (TFTs) fabricated from amorphous silicon (FIG. 44A), polysilicon (FIG. 44B), and aligned nanowire films (FIG. 44C). In a-Si and poly-Si based technologies, electrical carriers undergo multiple grain boundary scattering, thus limiting the achievable carrier mobility (carrier mobility for a-Si is ~<1 cm ² /V·s, the carrier mobility of poly-Si is ~<100 cm ² /V·s). On the other hand, in the nanowire-based technology of the present invention, electric carriers are ^transported through the TFT channel along multiple single-crystal paths, and thus achieve ) TFT with carrier mobility.

Off-substrate high temperature treatment: semiconductor nanowires and gate dielectrics are prepared outside the substrate at high temperature, and then applied on the substrate at room temperature. Therefore, the thermal properties of the substrate will not be a limiting factor for high temperature processing. Thus, allowing for high-quality crystal materials and gate dielectrics, which are key to high-performance reliable device functionality. Furthermore, by incorporating an extremely thin gate dielectric shell around each individual nanowire instead of an exotic gate oxide layer on the device, processing can be significantly simplified, while due to the extremely thin and near-perfect shell properties This reduces the required turn-on voltage.

Solution processability: Unlike bulk semiconductor wafers, nanowires can be suspended in solution and then deposited and affixed to virtually any substrate over large areas. In this way, high performance semiconductor materials on many technically important substrates (eg plastic, glass) are realized. This further enables roll-to-roll fabrication of high-performance electronics by inkjet or screen printing techniques.

Mechanical flexibility: Due to the extremely small diameter and large aspect ratio (>1000), nanowires have excellent mechanical flexibility with a radius of curvature as small as, for example, 10 microns. By depositing dense films of mechanically flexible oriented nanowires onto large flexible substrates, the resulting structures have excellent electrical properties comparable to bulk single crystal semiconductors and can be extended over arbitrarily large areas and are as flexible as an optical fiber. Furthermore, the mechanical flexibility of nanowires enables the formation of high-performance electronic devices on relatively rough substrates such as most plastics, which are nearly impossible with thin films of amorphous or polycrystalline silicon.

Minimized device size: The intrinsically small diameter and large length of nanowires allow easy control of TFT channel width and length. Transistors of reduced size can be realized, which is limited in the case of polysilicon devices. Furthermore, the intrinsic high mobility of nanowire materials allows transistors to be formed to reduced dimensions while still maintaining functional current values and allows high-density integration on large-area substrates, which is not possible with traditional amorphous or polycrystalline silicon materials. possible.

Applicable to the processing of other high-mobility materials such as GaAs nanowires: The capabilities of silicon nanowires can be extended and applied to other intrinsic high-mobility materials, such as III-V materials, including GaAs and InAs nanowires. As such, ultrahigh mobility materials are feasible, and many new applications are possible. Even higher mobility can be achieved by exploiting the underlying quantum effect - ballistic conduction of the nanowires, as further described here.

Nanowire Synthesis: In some embodiments, reliable and reproducible TFT device behavior can be achieved using nanowires with uniform physical size and chemical dopant distribution. This control has been demonstrated at very small scale in a 1 inch tube furnace. There are 8-inch semiconductor tube furnaces that are capable of producing large size nanowires. Controlling uniformity over large volumes is more difficult than controlling uniformity over small volumes. The controlled diameter and diameter distribution of the silicon nanowires is determined by that of the gold colloids. Commercially available gold colloids can be used. The length of the nanowires depends on the growth conditions - temperature, vapor pressure, and time of growth. These issues, as well as those of crystallization and doping concentrations, can be addressed by changing and fine-tuning the growth conditions.

Dielectric Oxide/Nitride Coating: The quality of the gate dielectric coating is very important for nanowire TFT performance. Techniques exist in planar semiconductor technology for forming high quality gate dielectrics. However, it is technically challenging to form a pinhole-free gate dielectric of uniform thickness around the nanowire surface without defined crystallographic orientation. This question can be approached from different points of view. By performing slow thermal oxidation directly after silicon nanowire growth, the process can be used to produce silicon oxide coatings smaller than ~2nm. The key to controlling the oxide coating is the nanowires with a smooth and consistent surface structure. Low oxidation treatment helps avoid hot spots and produces thin, pinhole-free coatings. Alternatively, plasma-assisted direct nitridation of silicon oxide-coated nanowires can be used to create oxynitride or nitride coatings on the nanowire surface.

Surface states and trapped charges: Due to their high surface-to-bulk atomic ratio, surface states, trapped charges, and dangling bonds affect the nanowires, which significantly limit device performance. A number of strategies can be used to minimize surface states, including direct thermal annealing under an inert atmosphere or under a hydrogen/forming gas atmosphere, and annealing in a hydrogen plasma after thermal annealing. These and other strategies are described further above.

Large-area nanowire film deposition: The development of a scalable protocol for fabricating aligned nanowire films on large-area substrates is critical to the eventual successful implementation of this new technology. For example, single-layer nanowires can be placed on glass or plastic substrates using fluidic alignment processes or LangmuirBlogette membrane schemes.

Ohmic contact: Making reliable ohmic contact with nanowires is very difficult due to the small contact area and complex interface states. The interface chemistry and physics between metal contacts and silicon is an important technology area for ohmic contacts. The key to success is the precise control of the metallization process and the surface cleaning process prior to the metallization process. Three possible metallization schemes can be used - e-beam evaporation of Ti-Au, Ni and Al. Various other processes including ion gun cleaning or HF etching can be used to remove the surface dielectric prior to source-drain metallization.

The present invention allows innovative developments in large area electronics and provides a new generation of electronic devices by providing thin film TFTs with properties comparable to inorganic single crystal semiconductor materials and the size and flexibility of plastic electronics.

TFT nanowire transistors can be fabricated with performance characteristics close to those of transistors fabricated from conventional single crystal silicon, most notably on extremely large glass or plastic substrates, which will enable ultra-large-scale high-density integration and innovation in plastic technology Real silicon available on. Potential applications of this technology are extensive, including the incorporation of nanowire TFTs into liquid crystal displays (LCDs). Nanowire TFTs have a much smaller footprint than a-Si TFTs, allowing for increased pixel density—for example, ultra-high-density displays. Smaller TFTs also block less light and have higher aperture ratios. Using nanowire TFTs, peripheral driving circuits can be integrated on the edge of the glass substrate at the same time, which greatly simplifies the manufacturing process and reduces the cost. Nanowire TFTs can be suitable for microdisplays, digital projectors, and high-density imaging devices that require extremely high pixel densities. Furthermore, the actual silicon-on-plastic technology enables the development of light, high information density electronic devices. For example, the present invention enables computing and display on a single board and enables wearable electronics, which are extremely important for police officers, first responders working in the field, soldiers on the battlefield, and space and remote detection.

In a broader sense, the invention allows engineers to develop electronic materials on any substrate material with the performance and material properties of any industrially relevant semiconductor material. This technology enables engineers to design the functionality/properties (ie, conductivity, doping, mobility, and on-voltage) of electronic materials completely independent of their structural properties (ie, their flexibility, shape, size, and handling characteristics). The selection of the physical properties of the semiconducting nanowire element (eg composition, diameter, length, crystallinity and density) determines the electronic performance; the properties of the substrate, the physical properties, can be chosen entirely independently. Meanwhile, the high performance, easy processing, and potentially low cost of nanowire thin films yield versatile flexible electronic platforms, and can be used not only in drive circuits for high-density displays and microdisplay arrays, radio frequency identification tags, large-area biosensors, but also in Many new applications for plastics, such as mini-cards, logic and memory for wearable computers, and many more important applications to be identified.

Three stages of development are described as follows: (1) silicon nanowire synthesis; (2) aligned nanowire film deposition; and (3) nanowire thin film transistor (TFT) fabrication.

(1) Synthesis of silicon nanowires

Step 1: A scalable process for silicon nanowire synthesis is described below.

For presentation purposes, examples of nanowire suspensions, nanowire types and nanowire concentrations are provided: 1 mg/100 cc in ethanol, p and n doped 60 nm diameter silicon nanowires, with a core-shell structure. The nanowire core is single crystal silicon. The nanowire shell is a ~2 nm thick pinhole-free silicon oxide or oxynitride coating, ~20-50 μm in length.

The synthesis uses a gold nanoparticle catalyzed CVD process. At a total pressure of 20-50 Torr _, a predetermined precursor gas mixture in He, _SiH4 and _B2H6 or _PH3 was passed over catalyst gold particles deposited on an oxide-coated silicon substrate , while heating the gold nanoparticles to a temperature of ~450°C. By contacting the gold nanoparticles, SiH ₄ /B ₂ H ₆ decomposes, and Si and B atoms diffuse into the gold nanoparticles and generate liquid alloy droplets. Once supersaturation is reached, Si/B atoms precipitate out and nanowire growth begins. A continuous supply _{of SiH4} and _B2H6 allows the nanowires to grow continuously until intentional termination, or "death" resulting from local condition changes. The quality of the nanowires depends on the quality of the gold nanoparticles, the control of the distribution of the gold nanoparticles on the substrate, and the growth _conditions , including temperature, the ratio of _SiH4 and _B2H6 or _PH3 , the partial pressure of _SiH4 , and The residence time of the precursor gas in the reactor.

In the presently illustrated embodiment, growth was achieved using a computer-controlled 8" semiconductor furnace. A 4" silicon oxide-coated silicon wafer was used as the substrate.

The process for uniformly depositing gold nanoparticles on a 4" wafer is described below.

Commercially available 60 nm diameter gold colloids were used. The goal was to achieve a uniform deposition of gold nanoparticles at a density between 2-4 particles per micron sq. The key is to minimize gold particle cluster formation. The population of particles may lead to undesirably larger diameter nanowire growth. Deposition can use spin-coating and self-assembly methods.

Spin coating is a fairly simple process. The deposition density can be controlled by varying the concentration of gold particles in the precursor colloid, manipulating the surface chemistry of the silicon wafer, and varying the spin speed. A drawback of spin coating can be the low utilization efficiency of the gold colloidal solution. Where available, recycling processes from the manufacturing stage can be used.

Self-assembly involves some use of building chemistry. The surface of a 4" silicon oxide-coated wafer can be functionalized with (3-aminopropyltrimethoxysilane (APTMS) or (3-mercaptopropyl)-trimethoxysilane (MPTMS) and then mixed with 60 nm gold Colloidal solution contact. Assembly of gold particles onto a surface. Comparison between two different chemistries and the possibility to control the density of gold particles by controlling the contact time and concentration of gold particles in the contact solution can be exploited.

Step 2: Optimizing nanowire growth conditions: Growth parameters must be optimized, including the ratio of SiH ₄ and B ₂ H ₆ or PH ₃ , growth temperature and growth time. The diameter distribution of silicon nanowires can be determined from the diameter distribution of gold nanoparticles. Commercially available 60 nm gold colloids can have a diameter distribution of ±10%. The same distribution is our goal for nanowires. Gold nanoparticles can split into smaller nanoparticles during nanogrowth with smaller diameters, depending on the growth conditions. Growth conditions can be optimized to minimize this event. Given the growth conditions, the nanowire length can be controlled by varying the growth time. The crystallinity and dopant concentration of silicon nanowires are also related to growth conditions. They can be optimized and controlled together with other important nanoscale properties.

Another issue is the thermal decomposition _{of SiH4} and _B2H6 under growth conditions in order to grow high quality silicon nanowires. This decomposition may produce undesired silicon nanoparticles in the product. In their small size growth, thermal decomposition is not easily eliminated, but it can be minimized by changing the growth conditions.

Step 3: Processing for Dielectric Thin Film Coating: The quality of the dielectric coating is a key factor in determining the performance of the nanowire TFT. The methods and underpinning science for high quality dielectric coatings are well established for planar monocrystalline silicon and later for non-clean and polycrystalline silicon. In general, methods can be divided into direct oxidation/nitridation for silicon oxide/nitride dielectrics and CVD deposition for all kinds of dielectric coatings. The specialized structural properties of silicon nanowires led to the choice of direct oxidation/nitridation rather than deposition methods. However, a deposition method can also be used as a selection method.

A thin coating of silica with a thickness of ~2 nm can be used. Direct oxidation of 60 nm diameter silicon nanowires can be performed in a nanowire growth furnace. After finishing the nanowire growth, the reaction gas mixture may be depleted from the reaction tube and replenished with a mixture of oxygen (5%) and helium at a temperature below 150°C. The temperature of the furnace is then slowly raised to a value between 300°C and 800°C. The oxidation temperature together with the ratio of oxygen to helium, the partial pressure of oxygen, and the oxidation time determine the thickness of the silicon oxide produced. These conditions can be optimized until a thickness of -2 nm is obtained. Slow oxidation is desired to minimize defects, dangling bonds, which would lead to trapped charges and states.

If the performance of thin silicon oxide coatings is not satisfactory, direct nitridation of silicon oxide-coated nanowires can be employed, resulting in an oxynitride coating. A higher dielectric constant allows oxynitridation and nitridation to produce more attractive coatings. A plasma-assisted direct nitriding method using a gas of NO or NH ₃ can also be employed.

Step 4. Processes for removing surface states and trapped charges: Surface states and trapped charges can be a serious problem for nanowires because of their high surface-to-bulk atomic ratio. Processes for solving this problem are well known in the semiconductor industry for planar processing and are suitable for nanowires. First, we can anneal in hydrogen using single nanowire device testing as feedback for condition optimization.

Step 5. Preparation of nanowire suspensions in ethanol: After coating with dielectric coating and annealing, silicon nanowires are removed from a 4" (or other size) wafer and suspended in ethanol by ultrasound. Nanowires can coagulate and precipitate out. Surface active Agents such as TritonX-10 can be used for stabilization.

step6. Nanowire Characterization: The structure and electrical properties of nanowires can be characterized. SEM and AFM can be used for characterization of their length and diameter distributions, high resolution TEM for thickness and uniformity of dielectric thin film coatings, transport measurements, EFM scanning gate AFM for their electrical properties. Characterization results can be fed back and used to fine-tune synthesis procedures and conditions.

(2) Oriented nanowire film deposition

A scalable method for the deposition of aligned nanowire monolayer films is described below.

Result: Oriented monolayer 60nm silicon nanowire film on 4" x 4" glass or plastic such as polystyrene.

Oriented nanowire arrays are critical conditions to ensure a single-crystal conductive channel between the source and drain of nanowire TFTs, which enables high field-effect mobility. In order to obtain highly oriented nanowire films over a large area, two basic schemes, the fluid flow scheme and the Langmuir-Blodgett membrane scheme, can be employed as parallel strategies.

step 1. General chemistry for nanowire surface modification: The goal of this assignment is to develop a general set of processes for modifying the surface of silicon nanowires to create stable nanowire suspensions in non-polar solvents, This is necessary in order to practice the Langmuir-Blodgett membrane scheme. We can use alkyl-trimethoxysilane to immobilize hydrophobic alkyl groups such as octyl groups on the nanowire surface. This allows the nanowires to be suspended in organic solvents such as octane. These surface groups may have detrimental effects on the electrical properties of the nanowires. If desired, methods for removing organic molecules from the silicon nanowire surface after nanowire thin film formation (eg, oxygen plasma or ozone cleaning processes) can be developed.

Step 2: Process for substrate surface treatment: The surface chemistry of the substrate is important for the adhesion of the nanowires to the substrate. In the case of glass substrates, the nanowires are intrinsically very sticky, since glass and silica-coated nanowires also have the same surface chemistry. Conventional cleaning and fast plasma oxygen plasma etching can be performed. For hydrophobic plastic substrates, we can first perform oxygen plasma oxidation and then use 3-aminopropyltrimethoxysilane to fix a 3-aminopropyl monolayer onto the surface. The rigid polystyrene board can be tested first. If successful, a flexible membrane such as a sheet of polypropylene can then be used.

Step 3: Fluid flow alignment: For fluid alignment, we use nanowires suspended in ethanol. Fluid flow schemes have been used to scale nanowires with widths of a few hundred microns and lengths of several inches. In principle, fluid flow alignment can be extended over very large areas, like logs in a river. In order to achieve alignment over large areas, fluidic channels with lateral dimensions comparable to the substrate dimensions can be used. The height of the channel can be controlled to less than 500 μm, so that the main part of the nanowire solution is close to the substrate, and the shear flow near the substrate surface achieves the alignment of the nanowires along the flow direction. Figure 45 shows a schematic diagram of a fluidic cell for aligning nanowires over a large area according to an embodiment of the present invention. Detailed method and system examples for this fluid cell alignment scheme have been described above with reference to fluid mask 1500, as shown in Figures 15A and 15B. The inlet and outlet of the fluidic unit should be carefully designed to ensure uniform flow along and across the entire fluidic channel.

Various nanowire solution concentrations and flow times can be used to control the nanowire surface density/coverage on the substrate. When desired, the substrate can be functionalized in order to enhance the compensation between the substrate and the nanowires to achieve higher surface coverage. A systematic study can be performed to achieve reproducible nanowire deposition on surfaces. Surface coverage can be studied using optical microscopy and/or scanning electron microscopy, and sound statistical schemes can be developed to quantitatively characterize surface coverage. These studies were first performed on glass substrates and carried out on functionalized plastic substrates.

Several critical issues should be noted and carefully controlled: 1) The rubber stamp (polydimethylsiloxane) fluid channel used for alignment of small dimensions cannot be applied on inch to tens of inch dimensions because the channel is due to Due to the flexible nature of PDMS, it may potentially collapse in the middle. The perimeter of the channel can be sealed with an O-ring or coated with a thin layer of PDMS. 2) On such large scales, the fluid flow across and along the entire channel is unlikely to be uniform, which is undesirable for uniform nanowire deposition. To achieve uniform flow, special attention should be paid to designing and controlling fluid channel inlets and outlets. Careful attention should also be paid to designing solution delivery schemes. A programmable automatic syringe pump can be used to ensure a constant solution delivery rate. There is a high technical risk in achieving uniform nanowire deposition on the surface. For example, there may be a higher nanowire density in the region near the channel entrance than in the region near the exit, which is often observed in microscopic channel fluidic alignments where the channel entrance is not carefully designed. Phenomenon. Density variations can be compensated by alternately reversing the flow direction during the alignment process. Alternatively, Langmuir-Blodgett film technology can be employed, which can provide uniform alignment over a large area. However, results from fluid flow alignment can still be used for initial testing on device fabrication and characterization.

step 4. Langmuir-Blodgett membranes: To achieve uniform alignment over large areas, large-scale assembly schemes based on Langmuir-Blodgett (L-B) membranes can be used. Langmuir-Blodgett alignment has been used to form thin films of nanoparticles and to align nanorods. This scheme can be extended to the alignment of nanowires in order to fabricate aligned nanowire films. Figure 46 shows a schematic diagram of nanowire alignment over a large area using a Langmuir-Blodgett film according to an exemplary embodiment of the present invention.

In this protocol, nanowires are first functionalized and suspended in a nonpolar solvent (step 1 above). This non-polar nanowire suspension is then transferred onto the wafer surface in the L-B tank. At sufficiently low densities, the nanowires form an isotropic distribution with random orientation. As the surface is compressed, it becomes more difficult to pinpoint random directions and the nanowires undergo a transition to a more regular anisotropic phase with non-axial symmetry, thus having a nematic or smectic phase (see Figure 46). Indeed, this has been observed in Monte-Carlo simulations and in real experiments for the case alignment of thin-film nanorods (eg, aspect ratio = length/diameter < 10). Alignment of nanowires over a large area on the wafer surface can thus be achieved. In addition, the directional capillary force and van der Waals attraction between nanowires further enhance the parallel alignment of nanowires and the formation of aligned nanowire films. Due to the significantly large aspect ratio of the nanowires (eg, greater than 500), the nanowires may experience significantly greater resistance, rotating from random orientation to parallel to each other. This potential problem can be solved, for example, by inducing some pre-alignment prior to surface compression. There are also a number of strategies that can be employed to achieve this goal. For example, fluidic processes can be combined in order to achieve some pre-alignment. An electric field can also be applied to enhance the alignment of the wires. The aligned nanowires on the wafer are then transferred to the desired substrate. The nanowire density can be controlled by the ratio of surfactant to nanowire and by the amount of surface compression. After forming a thin film of aligned nanowires on a wafer surface, it can be transferred to any substrate. Different transfer protocols can be used during transfer to avoid interfering alignments. Surface coverage can be characterized using the same protocol described above.

(3) TFT fabrication and characterization

A silicon nanowire TFT was fabricated in the current example with a field effect mobility of ~1000 cm ² /V·s, an on/off ratio greater than 10 ⁷ , and a threshold voltage less than 2.0 V, as described below.

Results: 1000 x 1000 arrays of silicon nanowire TFTs on glass and polystyrene substrates.

Although FETs have been demonstrated using single nanowires as the conducting channel, the application of these FETs often has large variations between individual devices. This discrepancy may be due to the lack of compositional control, reliable means to form ohmic contacts, and large-area surface trapping states. Achieving reliable and controllable electrical characteristics is critical for any practical application of TFTs. To achieve a high level of control over device properties, the electronic properties of individual nanowires must be highly reproducible and controllable. Electronic quality control of nanowires can be characterized and optimized using individual nanowire FET structures. With well-controlled electronic properties, nanowire thin film transistor devices can be fabricated on different substrates including glass and plastic.

step 1. Process for reliable metal flower processing using a single nanowire FET:

Individual nanowire transistor FET devices can be used as test vehicles to develop reliable metallization processes. Single nanowire FET devices can be fabricated on _SiO2 /Si surfaces using electron beam printing or photolithography. The substrate silicon can be a spherical back gate, and two metal electrodes can be used as source and drain (FIG. 47). Prior to metallization, a suitable surface cleaning procedure can be performed to remove oxides from the nanowire film and to ensure good contact between the nanowires and the contact metal. Planar silicon technology can be used as a reference point for selecting appropriate contact metals and process protocols. Various strategies, including ion gun cleaning, or HF etching can be used to remove the surface dielectric prior to source-drain metallization. Different metallization schemes (eg Ti/Au, Ni/Au, Al) can be tested and optimized using electron beam evaporation or sputtering processes. Attention has been paid to the surface treatment of nanowires (via thermal annealing and hydrogen plasma annealing) and its effect on electronic properties. Device behavior can be characterized using a semiconductor analyzer. Individual measurement structures including gate-related two-terminal and four-terminal measurements, as well as power microscopy, can be used to characterize device behavior. The device structure can be rigorously simulated theoretically, thereby obtaining all key transistor parameters, including carrier concentration and mobility, threshold voltage, on/off ratio, etc. Results from electrical testing and theoretical simulations can be further fed back to optimize metallization until a reliable process is obtained. This is likely the standard metallization process used to make nanowire TFTs. Individual nanowire FETs can also be used for nanowire qualification testing. Given that the synthesis conditions and electronic parameters of nanowires can constitute a database, and this database can be further used to guide more controllable synthesis and device fabrication processes.

Figure 47 shows plan and perspective views of a single nanowire field effect transistor according to an example embodiment of the present invention. A single nanowire FET was used as the basic device geometry in order to characterize and optimize the electrical transport properties of individual nanowires. The various perspective views shown in Figure 47 represent scanning electron microscope (SEM) images of typical devices. In this device, a silicon substrate can be used as a back gate, and two metal electrodes can be used as source-drain contacts.

step2. Spherical back-gate nanowire TFT: The goal of this assignment is to demonstrate and characterize nanowire TFTs fabricated from nanowire films with different surface densities using the same device structure described above. A robust protocol for fabrication of individual nanowire device identification can be applied to nanowire thin-film transistors. TFT devices can be fabricated using nanowire films with different surface densities, thereby realizing individual TFT devices with variable amounts of nanowires bridging the source and drain. Semiconductor analyzers can be used to characterize device behavior as a function of nanowire film density, such as current value, on/off ratio, threshold voltage, and gate leakage current, and can theoretically simulate device behavior in order to calculate critical device parameters, Include mobility values. The simulation can then be used to guide the design of the device structure to achieve the desired device functionality. These studies can be performed on _SiO2 /Si substrates using silicon as the back gate, since this is a relatively easy way for device fabrication and simulation. At the conclusion of this task, reliable protocols can be developed to fabricate TFTs with variable nanowire density and controllable device behavior.

Step 3. Local gate-type nanowire FETs on glass and plastic: For example, the fabrication of nanowire TFTs and TFT arrays on glass and plastics is introduced, with the goal of achieving a mobility of ~1000cm ² /V·s. A TFT using a partially patterned gate is employed. Using Si/SiO ₂ or Si/Si ₃ N ₄ core-shell nanowires to fabricate partial gate TFT structure, where SiO ₂ or Si ₃ N ₄ shell can be used as the gate dielectric, and additional metal electrodes can be used as the gate (Fig. 48).

48A and 48B show perspective views of a local gate nanowire thin film transistor according to an embodiment of the present invention. Figure 48A shows a staggered structure with gates formed below the nanowire film and source and drain electrodes formed from the top of the nanowire film with the dielectric cap removed. Figure 48B shows a TFT structure with all contacts formed on top of the nanowire film.

Bottom-contact and top-contact gate structures can be tested to guarantee the lowest switching voltage, highest on/off ratio and lowest leakage current. All these tests were first performed on glass substrates and then applied to plastics. As a result, controllable device characteristics (carrier mobility ~1000cm ² /V·s, controllable threshold (less than 2.5V), current value (1μA-1mA) and turn-on/ cut-off ratio (greater than 10 ⁶ )) to fabricate individual nanowire TFTs.

Step 4. Integrated nanowire TFT arrays: It can be applied on 4×4” glass and plastic substrates due to the identification of reliable protocols for the fabrication of individually localized gate TFTs on glass and selected plastics utilizing desired device properties Fabrication of integrated TFT device arrays. Multi-level lithography can be used to pattern nanowire films and form source-drains and gates for integrated TFT arrays. Special attention should be paid to precise device structure design and device manufacturing process design. Amorphous silicon The mature technology of polysilicon TFT and polysilicon TFT can be used as a reference point for this design.At the end, a 1000×1000 nanowire TFT array can be fabricated and further constituted into a logic circuit to manufacture logic functions.

Electronic devices comprising nanowire layers, nanowire layers combined with single crystalline, amorphous and polycrystalline semiconductor materials

In another aspect of the invention, electronic devices may be fabricated using structures comprising multiple nanowire film layers. In other words, multiple layers of nanowire thin films can be stacked, as in the various embodiments described above, to fabricate devices.

For example, in an embodiment, a first plurality of nanowires is deposited on a substrate to form a first thin film layer of nanowires. A second plurality of nanowires is deposited on the first nanowire film to form a second nanowire film layer. Any number of additional plurality of nanowires may also be deposited on the previous nanowire thin film layer to form stacked additional thin film layers.

For illustration purposes, referring to two thin film layer embodiments, the nanowires of the first and second layers are differently doped. For example, the first layer may include p-doped nanowires and the second layer may include n-doped nanowires. In this way, junctions such as p-n junctions are thereby formed at the intersections/intersections between the nanowires of the first and second thin film layers.

Contacts can be formed to form electronic devices based on junction properties. For example, in a diode embodiment, a first contact coupled to a nanowire of a first film may be formed and a second contact coupled to a nanowire of a second film may be formed. In this way, a two-terminal p-n diode can be formed. Three-terminal and other terminal count devices, such as transistors, can be formed in the same manner.

Note that the nanowires of the first thin film layer are preferably aligned parallel to each other, and the nanowires of the second thin film layer are preferably aligned parallel to each other. However, in an alternative, the nanowires of the first and/or second film layer may be randomly oriented.

In another embodiment, an electronic device is formed comprising a hybrid nanowire single crystal semiconductor structure. For example, forming single crystal semiconductor strips/thin films. For example, single crystal stripes can be formed by etching a wafer, such as a silicon-on-insulator (SOI) wafer. In addition, single crystal semiconductor strips/films can be formed to have any shape or size desired according to a particular application. A plurality of nanowires are deposited on top of the strips. A junction, such as a p-n junction, is formed at the intersection between the nanowire and the single crystal semiconductor strip. For example, a single crystal semiconductor strip can be doped in a first way (eg n or p doped) and the nanowires can be doped in a different way (eg p or n doped). In this way, a p-n junction can be formed at the intersection of the strip and the nanowire.

Contacts can be formed to make electronic devices based on the properties of these junctions. For example, in a diode embodiment, a first contact coupled to the monocrystalline semiconductor strip may be formed, and a second contact coupled to the nanowire film may be formed. In this way, a two-terminal p-n diode can be formed. Three-terminal and other terminal count devices, such as transistors, can be formed in the same manner.

The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but may also be randomly oriented.

In another embodiment, an electronic device comprising a hybrid nanowire-amorphous/polycrystalline semiconductor structure is formed. For example, amorphous or polycrystalline semiconductor films can be deposited on the substrate. A plurality of nanowires are deposited on the thin film pattern. A junction, such as a p-n junction, is formed at the intersection point/position between the nanowire and the amorphous/polycrystalline semiconductor film pattern. For example, an amorphous or polycrystalline semiconductor film can be doped in a first way (eg, n or p doping), and nanowires can be doped in a different way (eg, p or n doping). In this way, a p-n junction can be formed at the intersection of the amorphous or polycrystalline semiconductor film and the nanowire.

Contacts can be formed to make electronic devices based on the properties of these junctions. For example, in a diode embodiment, a first contact may be formed coupled to the amorphous or polycrystalline semiconductor film, and a second contact may be formed coupled to the nanowire film. In this way, a two-terminal p-n diode can be formed. Three-terminal and other terminal count devices, such as transistors, can be formed in the same manner.

The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but may also be randomly oriented.

In example embodiments, light emitting devices can be made using these structures. For example, light-emitting semiconductor nanowires, such as light-emitting semiconductor nanowires that emit red, green, and blue light, can be selected at a predetermined ratio of nanowires. Nanowires selected in predetermined ratios may be mixed in the solution. The nanowire mixture flows through single crystalline, amorphous or polycrystalline semiconductor strips/films. As described above, contacts can be formed to make light emitting electronic devices such as light emitting diodes in two contact/terminal devices. Depending on the chosen mixture of luminescent nanowires, any color of light, including white light, can be emitted by the light-emitting electronics.

Application of the invention

According to embodiments of the present invention, various electronic devices and systems may incorporate semiconductor or other types of devices with nanowire films. Some application examples for the present invention are described below, which are for illustrative purposes only and not limiting. Applications described herein may include aligned or non-aligned films of nanowires, and may include composite or non-composite films of nanowires.

Semiconductor devices (or other types of devices) of the present invention may be coupled to signals of other electronic circuits and/or may be integrated with other electronic circuits. The semiconductor devices of the present invention can be formed on a large substrate, which can later be separated or diced into smaller substrates. Furthermore, on large substrates (ie, substrates substantially larger than conventional semiconductor wafers), semiconductor devices formed thereon in accordance with the present invention may be interconnected.

The present invention can be incorporated in applications requiring a single semiconductor device, and in multiple semiconductor devices. For example, the invention is particularly applicable to large area, macroscopic electronic substrates on which multiple semiconductor devices are formed. Such electronic devices may include display driver circuits for active matrix liquid crystal displays (LCDs), organic LED displays, field emission type displays. Other active displays can be formed from nanowire polymers, quantum dot polymer composites that can be used as emitters and active drive matrices. The invention is also applicable to small libraries, credit cards, large area array sensors, and radio frequency identification (RFID) tags, including small cards, small inventory tags, and the like.

The invention is also applicable to digital and analog circuit applications. In particular, the invention is applicable to applications requiring very large-scale integration on large-area substrates. For example, nanowire film embodiments of the present invention may be implemented in logic circuits, memory circuits, processors, amplifiers, and other digital and analog circuits.

The invention can be applied to optoelectronic applications. In these applications, transparent conductive substrates are used to enhance the optoelectronic performance of specific optoelectronic devices. For example, such transparent conductive substrates can be used as flexible, large-area replacements for indium tin oxide (ITO) and the like. The substrate can be coated with a thin film of nanowires formed with a large bandgap, i.e. larger than visible light, so that she should be non-absorbing, but should be formed with an active HOMO or LUMO strips for material alignment. Transparent conductors can be located on both sides of the photovoltaic absorbing material, thereby carrying current away from the photovoltaic device. Two different nanowire materials can be chosen, one with the HOMO aligned with the HOMO band of the optoelectronic material and the other with the LUMO aligned with the LUMO of the optoelectronic material. The bandgap of the two nanowire materials can be chosen to be much larger than that of the optoelectronic material. According to this embodiment, the nanowires may be lightly doped in order to reduce the electrical resistance of the nanowire film while allowing the substrate to remain substantially non-absorptive.

Thus, a wide range of military and consumer products can incorporate nanowire film embodiments of the present invention. These products may include, for example, personal computers, workstations, servers, network devices, steering electronics such as PDAs and palm pilots, telephones (eg, cellular and standard), radios, televisions, electronic game devices and gaming systems, home security systems, automobiles, aircraft, boats, and other household and commercial devices.

in conclusion

Various embodiments of the present invention have been described above, and it should be understood that they are only examples and not limitations. It will be apparent to those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. As such, the scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims (56)

1. electronic substrate with a plurality of semiconductor device comprises:

Substrate;

Nano wire film on described substrate comprises semiconductor nanowires, reaches working current value thereby have enough nanowire density, and wherein said nano wire film limits a plurality of semiconductor device region; With

It is right that one or more source electrode that forms in described semiconductor device region and draining contacts, be provided to the electrical connection of a plurality of semiconductor device thus, at least two nano wires in the wherein said nano wire film form each source electrode and drain electrode contact centering each between raceway groove.

2. according to the electronic substrate of claim 1, wherein time group semiconductor device comprises diode at least, and described one or more source electrode and draining contact to comprise be formed on the described nano wire film or under anode and negative electrode.

3. according to the electronic substrate of claim 2, wherein said nano wire film forms p-n junction between described anode and negative electrode.

4. according to the electronic substrate of claim 2, wherein said diode comprises light-emitting diode.

5. according to the electronic substrate of claim 1, wherein time group semiconductor device comprises logical device at least.

6. according to the electronic substrate of claim 1, wherein time group semiconductor device comprises memory device at least.

7. according to the electronic substrate of claim 1, wherein time group semiconductor device comprises active matrix driving circuit at least.

8. according to the electronic substrate of claim 1, wherein said nano wire substantial registration is parallel to their major axis.

9. according to the electronic substrate of claim 1, wherein the nano wire rough alignment is parallel to the axle between source electrode and the drain electrode contact.

10. according to the electronic substrate of claim 1, also comprise one or more grid that is formed on the substrate,

Wherein said nano wire film is formed on described one or more grid, and described one or more source electrode contacts being formed on the described nano wire film with drain electrode.

11. electronic substrate according to claim 1, wherein said one or more source electrode contacts being formed on the described substrate with drain electrode, described nano wire film is formed on described source electrode and contacts with drain electrode, and described semiconductor device also comprises one or more grid contact that is formed on the described nano wire film.

12. electronic substrate according to claim 10, wherein said one or more grid, described one or more source electrode and drain electrode contact being formed on the described substrate, and described nano wire film is formed on described one or more grid and described one or more source electrode contacts last with drain electrode.

13. according to the electronic substrate of claim 10, wherein said one or more grid and described one or more source electrode contact being formed on the described nano wire film with drain electrode.

14., also be included in the interconnection between time group semiconductor device according to the electronic substrate of claim 1.

15. according to the electronic substrate of claim 1, wherein said substrate comprises fexible film.

16. according to the electronic substrate of claim 1, wherein said substrate comprises transparent material.

17. according to the electronic substrate of claim 1, wherein said nano wire is a monocrystal nanowire.

18. according to the electronic substrate of claim 1, wherein said nano wire film comprises the nano wire of capacity, thus have greater than 10 receive the peace raceway groove in the on-state current value.

19. according to the electronic substrate of claim 10, wherein time described grid of group comprises more than one nano wire film at least.

20. according to the electronic substrate of claim 1, wherein time group raceway groove comprises p-n junction at least, thus during operation, p-n junction is luminous.

21. according to the electronic substrate of claim 1, wherein said nano wire is doped.

22. according to the electronic substrate of claim 1, wherein time described nano wire of group has the doping core at least.

23. according to the electronic substrate of claim 1, wherein time described nano wire of group has the doping shell at least.

24. according to the electronic substrate of claim 1, wherein time described nano wire of group has doping core and shell at least.

25. according to the electronic substrate of claim 1, wherein time described nano wire of group is oxidized at least, thereby forms gate dielectric.

26. according to the electronic substrate of claim 1, wherein time group semiconductor device is electrically coupled on other circuit at least.

27. according to the electronic substrate of claim 26, wherein said circuit is a logical circuit.

28. according to the electronic substrate of claim 26, wherein said circuit is a memory circuitry.

29. according to the electronic substrate of claim 26, wherein said circuit is an active matrix driving circuit.

30. according to the electronic substrate of claim 1, wherein time group semiconductor device physically is coupled to other circuit at least.

31. according to the electronic substrate of claim 30, wherein said circuit is a logical circuit.

32. according to the electronic substrate of claim 30, wherein said circuit is a memory circuitry.

33. according to the electronic substrate of claim 30, wherein said circuit is an active matrix driving circuit.

34. according to the electronic substrate of claim 1, wherein said nano wire is patterned.

35. according to the electronic substrate of claim 34, wherein said patterning nano line is by photoetching composition.

36. according to the electronic substrate of claim 34, wherein said patterning nano line is screen printed.

37. according to the electronic substrate of claim 34, wherein said patterning nano line is by ink jet printing.

38. according to the electronic substrate of claim 34, wherein said patterning nano line is by miniature contact print.

39. according to the electronic substrate of claim 1, wherein nano wire is revolved notes.

40. according to the electronic substrate of claim 1, wherein nano wire is mechanically aimed at.

41. according to the electronic substrate of claim 1, wherein nano wire is aimed at by fluid.

42. according to the electronic substrate of claim 1, wherein nano wire is sheared the power aligning.

43. according to the electronic substrate of claim 1, wherein said nano wire comprises enough density, thereby has the statistical probability that realizes device on any position on the substrate.

44., also comprise one deck oxide at least a portion that is deposited on described nano wire according to the electronic substrate of claim 1.

45. according to the electronic substrate of claim 1, wherein said nano wire is the ballistic conductor that has greater than the mobility of the piece crystal of same semiconductor material.

46. according to the electronic substrate of claim 1, wherein said nano wire is orientated randomly.

47. according to the electronic substrate of claim 1, wherein said nano wire forms monofilm, inferior monofilm or multilayer film.

48. a manufacturing has the method for the electronic substrate of a plurality of semiconductor device, comprising:

(a) on substrate, deposit the nano wire film that comprises semiconductor nanowires, thereby it have enough nanowire density realization working current values;

(b) in nano wire film or on limit a plurality of semiconductor device region; With

(c) in semiconductor device region, form one or more source electrode and draining contact right, electrical connection is provided for thus a plurality of semiconductor device, at least two nano wires in the wherein said nano wire film form each source electrode and drain electrode contact centering each between raceway groove.

49., also comprise the major axis aligning nano wire that is arranged essentially parallel to them according to the method for claim 48.

50., also comprise the step that forms grid according to the method for claim 48.

51. according to the method for claim 48, wherein step (c) comprises formation anode and negative electrode.

52. according to the method for claim 48, wherein the nano wire rough alignment is parallel to the axle between source electrode and the drain electrode contact.

53. according to the method for claim 50, wherein grid is formed on the substrate, nano wire film is formed on the grid, and described one or more source electrode contacts being formed on the nano wire film with drain electrode.

54. according to the method for claim 50, wherein said one or more source electrode and drain electrode are to being formed on the substrate, nano wire film is formed on source electrode and contacts with drain electrode, and grid is formed on the nano wire film.

55. according to the method for claim 50, wherein grid and described one or more source electrode contact with drain electrode being formed on the substrate, nano wire film is formed on grid and described one or more source electrode contacts last with drain electrode.

56. according to the method for claim 50, wherein grid and described one or more source electrode contact being formed on the nano wire film with drain electrode.

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