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CN1744326A - Epitaxial substrates and semiconductor elements - Google Patents

Epitaxial substrates and semiconductor elements Download PDF

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CN1744326A
CN1744326A CNA2005100990233A CN200510099023A CN1744326A CN 1744326 A CN1744326 A CN 1744326A CN A2005100990233 A CNA2005100990233 A CN A2005100990233A CN 200510099023 A CN200510099023 A CN 200510099023A CN 1744326 A CN1744326 A CN 1744326A
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gallium nitride
epitaxial
substrate
epitaxial layer
semiconductor element
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CN100555659C (en
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木山诚
冈久拓司
樱田隆
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Sumitomo Electric Industries Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • H10D62/405Orientations of crystalline planes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/252Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN

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Abstract

In a Schottky diode 11, a gallium nitride support base 13 includes a first surface 13a and a second surface 13b opposite from the first surface and has a carrier concentration exceeding 1 x 10 18 cm -3 . A gallium nitride epitaxial layer 15 is disposed on the first surface 13a. An Ohmic electrode 17 is disposed on the second surface 13b. The Schottky electrode 19 is disposed on the gallium nitride epitaxial layer 15. A thickness D1 of the gallium nitride epitaxial layer 15 is at least 5 microns and no more than 1000 microns. Also, the carrier density of the gallium nitride epitaxial layer 15 is at least 1 x 10 14 cm -3 and no more than 1 x 10 17 cm -3 .

Description

外延基底和半导体元件Epitaxial substrates and semiconductor elements

技术领域technical field

本发明涉及外延基底和半导体元件。The present invention relates to epitaxial substrates and semiconductor elements.

背景技术Background technique

Y.Irokawa等人于2003年9月15日在Appl.Phys.Lett.(第83卷第11期)中描述了一种PIN二极管。PIN二极管上装备有生长在GaN独立式基底上的外延层。用氢化物气相外延(HVPE)法在Al2O3基底上生长用作GaN独立式基底的厚膜。将激光应用在该厚膜上,使其与Al2O3基底分离,形成GaN独立式基底。在该GaN独立式基底上,用金属有机气相外延生长法生长厚度为3微米的无掺杂氮化镓膜。然后在该无掺杂氮化镓膜上生长厚度为0.3微米的Mg掺杂的氮化镓膜。GaN独立式基底、无掺杂氮化镓膜和Mg掺杂的氮化镓膜形成PIN结构。A PIN diode is described in Appl. Phys. Lett., Vol. 83, No. 11, Sept. 15, 2003 by Y. Irokawa et al. PIN diodes are equipped with epitaxial layers grown on a GaN free-standing substrate. Thick films used as GaN free-standing substrates were grown on Al 2 O 3 substrates by hydride vapor phase epitaxy (HVPE). A laser is applied to this thick film, which separates it from the Al2O3 substrate, forming a GaN free-standing substrate. On the GaN free-standing substrate, a non-doped gallium nitride film with a thickness of 3 microns is grown by metal-organic vapor phase epitaxy. A Mg-doped gallium nitride film was then grown to a thickness of 0.3 microns on the non-doped gallium nitride film. A GaN independent substrate, an undoped gallium nitride film and a Mg-doped gallium nitride film form a PIN structure.

P.Kozodoy等人于1998年8月17日在Appl.Phys.Lett.(第73卷第7期)中描述了氮化镓pn结的特征。首先,用LEO再结合用的SiO2掩膜通过金属有机气相外延生长法在c-平面蓝宝石基底上生长厚度为2微米的GaN膜。掩膜形成为带有5微米开孔的条带,其分布间隔是45微米。在LEO生长时,氮化镓在垂直于掩膜开孔的方向上生长,并且在掩膜上水平蔓延。生长的氮化镓的高度和蔓延长度都约为8微米。在该LEO氮化镓区域上形成pn结二极管。这种pn结二极管包括厚度为1微米的n型GaN膜、在该n型GaN膜顶部上生长的厚度为0.5微米的Mg掺杂的p型GaN膜。这种pn结二极管的尺寸是2微米×20微米。Gallium Nitride pn junctions are characterized in Appl. Phys. Lett., Vol. 73, No. 7, Aug. 17, 1998 by P. Kozodoy et al. First, a GaN film with a thickness of 2 μm was grown on a c-plane sapphire substrate by metal-organic vapor phase epitaxy using a SiO2 mask for LEO recombination. The mask was formed as stripes with 5 micron openings at intervals of 45 microns. During LEO growth, GaN grows perpendicular to the mask opening and spreads horizontally across the mask. The height and spread length of the grown GaN are both about 8 microns. A pn junction diode is formed on the LEO gallium nitride region. This pn junction diode includes an n-type GaN film with a thickness of 1 micron, and a Mg-doped p-type GaN film with a thickness of 0.5 micron grown on top of the n-type GaN film. The size of this pn junction diode is 2 microns x 20 microns.

在Kozodoy的论文中描述的氮化镓pn结二极管中,低位错区域(小于106cm-2)处的反向泄漏电流比高位错区域(约4×108cm-2)处的低,这表明反向击穿性得以改善。但是,该论文中的装置结构很复杂,实际上不能在低位错区域上生产该装置。在上述Irokawa的论文中,GaN外延层的厚度是3微米,不足以使载流子浓度达到5×1016cm-3。Irokawa论文中的PIN二极管的反向闭锁电压也不足够高。In the GaN pn junction diode described in Kozodoy's paper, the reverse leakage current is lower in the low dislocation region (less than 10 6 cm -2 ) than in the high dislocation region (about 4×10 8 cm -2 ), This indicates that reverse breakdown is improved. However, the structure of the device in that paper is complex, and the device cannot be practically produced on low-dislocation regions. In the above-mentioned paper by Irokawa, the thickness of the GaN epitaxial layer is 3 micrometers, which is not enough for the carrier concentration to be 5×10 16 cm -3 . The reverse blocking voltage of the PIN diode in Irokawa's paper is not high enough either.

氮化物半导体如二极管的击穿机理如下。当作为反偏压状态下最大场强的肖特基(Schottky)结或PN结处的场强大于临界值时,冲击电离会使反向泄漏电流陡增。这就是公知的击穿现象。理想的击穿发生时间是当耗尽层延伸时外延层足够厚和即使结处的场强达到临界值耗尽层也在外延层中。但是,如果外延层的厚度不足以提供载流子浓度,则外延层的整个厚度都会在结处的场强达到临界值(穿通)之前耗尽,结处的场强将提前达到临界值,与上述理想的情况相比,击穿会在较低的电压下发生。另外,因为耗尽层延伸到外延层和基底之间的边界面上,所以边界面中的缺陷导致的泄漏电流能够降低泄漏电流的反向性能,可能降低击穿电压。如果因为这些因素发生穿通,则击穿电压将下降。The breakdown mechanism of a nitride semiconductor such as a diode is as follows. When the field strength at the Schottky junction or PN junction, which is the maximum field strength in the reverse bias state, is greater than a critical value, the impact ionization will cause a sharp increase in the reverse leakage current. This is the well-known phenomenon of breakdown. The ideal time for breakdown to occur is when the depletion layer is extended and the epitaxial layer is thick enough and the depletion layer is in the epitaxial layer even if the field strength at the junction reaches a critical value. However, if the thickness of the epitaxial layer is not sufficient to provide the carrier concentration, the entire thickness of the epitaxial layer will be exhausted before the field strength at the junction reaches the critical value (punchthrough), and the field strength at the junction will reach the critical value earlier, compared with Breakdown occurs at lower voltages than in the ideal case described above. In addition, since the depletion layer extends to the boundary surface between the epitaxial layer and the substrate, leakage current caused by defects in the boundary surface can reduce the reverse performance of the leakage current, possibly reducing the breakdown voltage. If punch through occurs due to these factors, the breakdown voltage will drop.

本发明的目的是克服这些问题,提供一种包含III族化合物半导体层的半导体元件,III族化合物半导体层包括用于改善击穿的结构。本发明的另一个目的是提供用于该半导体元件的外延基底。It is an object of the present invention to overcome these problems and provide a semiconductor element including a group III compound semiconductor layer including a structure for improving breakdown. Another object of the present invention is to provide an epitaxial substrate for the semiconductor element.

发明内容Contents of the invention

一方面,本发明提供一种包括III族氮化物半导体层的半导体元件。该半导体元件包括:(a)氮化镓独立式基底,该基底包括第一表面和与第一表面相反的第二表面,其载流子浓度大于1×1018cm-3;(b)放置在第一表面上的第一氮化镓外延膜;(c)放置在第二表面上的欧姆电极;和(d)放置在第一氮化镓外延层上的肖特基(Schottky)电极。第一氮化镓外延膜的厚度至少是5微米,但不大于1000微米。第一氮化镓外延膜的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3。半导体元件是肖特基(Schottky)二极管。In one aspect, the present invention provides a semiconductor device including a Group III nitride semiconductor layer. The semiconductor element includes: (a) a free-standing gallium nitride substrate, the substrate includes a first surface and a second surface opposite to the first surface, the carrier concentration of which is greater than 1×10 18 cm -3 ; (b) placing A first GaN epitaxial film on the first surface; (c) an ohmic electrode disposed on the second surface; and (d) a Schottky electrode disposed on the first GaN epitaxial layer. The thickness of the first GaN epitaxial film is at least 5 microns but not greater than 1000 microns. The carrier concentration of the first gallium nitride epitaxial film is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 . The semiconductor element is a Schottky diode.

在这种肖特基(Schottky)二极管中,因为第一氮化镓外延层的厚度至少是5微米,但不大于1000微米,还因为第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层的厚度和载流子浓度进行设计,在没有穿通的情况下达到理想的击穿效果。In this Schottky diode, because the thickness of the first GaN epitaxial layer is at least 5 micrometers, but not more than 1000 micrometers, and because the carrier concentration of the first GaN epitaxial layer is at least 1 ×10 14 cm -3 , but not greater than 1×10 17 cm -3 , so the thickness and carrier concentration of the epitaxial layer can be designed to achieve an ideal breakdown effect without punch-through.

另一方面,本发明提供一种包括III族氮化物半导体层的半导体元件。该半导体元件包括:(a)氮化镓支撑底板,该底板包括第一表面和与第一表面相反的第二表面,其载流子浓度大于1×1018cm-3;(b)放置在第一表面上的第一氮化镓外延层;(c)放置在第二表面上的欧姆电极;(d)放置在第一氮化镓外延层上并且含有p型掺杂剂的第二氮化镓外延层;和(e)放置在第二氮化镓外延层上的欧姆电极。氮化镓支撑底板具有n型导电性。第一氮化镓外延层的厚度至少是5微米,但不大于1000微米。第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3。半导体元件是pn结二极管。In another aspect, the present invention provides a semiconductor element including a Group III nitride semiconductor layer. The semiconductor element includes: (a) a gallium nitride support base plate, the base plate includes a first surface and a second surface opposite to the first surface, the carrier concentration of which is greater than 1×10 18 cm -3 ; (b) placed on A first gallium nitride epitaxial layer on the first surface; (c) an ohmic electrode placed on the second surface; (d) a second nitrogen nitrogen layer placed on the first gallium nitride epitaxial layer and containing a p-type dopant a gallium nitride epitaxial layer; and (e) an ohmic electrode disposed on the second gallium nitride epitaxial layer. The gallium nitride support base has n-type conductivity. The thickness of the first GaN epitaxial layer is at least 5 microns, but not greater than 1000 microns. The carrier concentration of the first gallium nitride epitaxial layer is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 . The semiconductor element is a pn junction diode.

在这种pn结二极管中,因为第一氮化镓外延层的厚度至少是5微米,但不大于1000微米,还因为第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层的厚度和载流子浓度进行设计,在没有穿通的情况下达到理想的击穿效果。In this pn junction diode, because the thickness of the first GaN epitaxial layer is at least 5 μm but not more than 1000 μm, and because the carrier concentration of the first GaN epitaxial layer is at least 1×10 14 cm -3 , but not greater than 1×10 17 cm -3 , so the thickness and carrier concentration of the epitaxial layer can be designed to achieve an ideal breakdown effect without punchthrough.

另一方面,本发明提供一种包括III族氮化物半导体层的半导体元件。该半导体元件包括:(a)氮化镓支撑底板,该底板包括第一表面和与第一表面相反的第二表面,其载流子浓度大于1×1018cm-3;(b)放置在第一表面上的第一氮化镓外延层;(c)放置在第一氮化镓外延层中的p型半导体区域;(d)放置在p型半导体区域中的n型半导体区域;(e)放置在n型半导体区域上的源电极;(f)放置在第二表面上的漏电极;(g)放置在第一氮化镓外延膜上的绝缘层;和(f)放置在绝缘层上的门电极。第一氮化镓外延层的厚度至少是5微米,但不大于1000微米。第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3。半导体元件是MIS晶体管。In another aspect, the present invention provides a semiconductor element including a Group III nitride semiconductor layer. The semiconductor element includes: (a) a gallium nitride support base plate, the base plate includes a first surface and a second surface opposite to the first surface, the carrier concentration of which is greater than 1×10 18 cm -3 ; (b) placed on A first gallium nitride epitaxial layer on the first surface; (c) a p-type semiconductor region placed in the first gallium nitride epitaxial layer; (d) an n-type semiconductor region placed in the p-type semiconductor region; (e ) a source electrode placed on the n-type semiconductor region; (f) a drain electrode placed on the second surface; (g) an insulating layer placed on the first gallium nitride epitaxial film; and (f) an insulating layer placed on the on the gate electrode. The thickness of the first GaN epitaxial layer is at least 5 microns, but not greater than 1000 microns. The carrier concentration of the first gallium nitride epitaxial layer is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 . The semiconductor elements are MIS transistors.

MIS晶体管具有的结构中包括放置在n型半导体区域上的源电极和放置在基底第二表面上的漏电极,其中,电流从一个电极垂直流向另一个电极。因为第一氮化镓外延层的厚度至少是5微米,但不大于1000微米,还因为第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层的厚度和载流子浓度进行设计,在没有穿通的情况下达到理想的击穿效果。The MIS transistor has a structure including a source electrode placed on an n-type semiconductor region and a drain electrode placed on a second surface of a substrate, wherein current flows vertically from one electrode to the other. Because the thickness of the first GaN epitaxial layer is at least 5 μm but not more than 1000 μm, and because the carrier concentration of the first GaN epitaxial layer is at least 1×10 14 cm −3 but not more than 1× 10 17 cm -3 , so the thickness and carrier concentration of the epitaxial layer can be designed to achieve the ideal breakdown effect without punch-through.

在本发明的半导体元件中,优选用离子注入法将p型半导体区域的p型掺杂剂引入。另外,在本发明的半导体元件中,优选用离子注入法将n型半导体区域的n型掺杂剂引入。In the semiconductor device of the present invention, the p-type dopant in the p-type semiconductor region is preferably introduced by ion implantation. In addition, in the semiconductor element of the present invention, the n-type dopant in the n-type semiconductor region is preferably introduced by ion implantation.

在本发明的半导体元件中,氮化镓支撑底板第一表面的表面取向优选在不大于(0001)的+5度但至少是(0001)的-5度范围内。这样就提供了低位错的GaN基底。In the semiconductor element of the present invention, the surface orientation of the first surface of the gallium nitride supporting substrate is preferably within a range of not more than +5 degrees of (0001) but at least -5 degrees of (0001). This provides a low dislocation GaN substrate.

在本发明的半导体元件中,氮化镓独立式基底第一表面的表面取向优选在不大于(1-100)或(11-20)的+5度但至少是(1-100)或(11-20)的-5度范围内。In the semiconductor element of the present invention, the surface orientation of the first surface of the gallium nitride free-standing substrate is preferably +5 degrees not greater than (1-100) or (11-20) but at least (1-100) or (11 -20) within -5 degrees.

使用该半导体元件时,外延层中的位错下降,反向泄漏电流下降,反向击穿得以改善。When this semiconductor element is used, the dislocations in the epitaxial layer are reduced, the reverse leakage current is reduced, and the reverse breakdown is improved.

在本发明的半导体元件中,氮化镓支撑底板第一表面的位错密度优选不大于1×108cm-2In the semiconductor device of the present invention, the dislocation density of the first surface of the gallium nitride supporting base plate is preferably not greater than 1×10 8 cm -2 .

使用该半导体元件时,位错密度低,所以外延层中的位错下降,因此,反向泄漏电流下降,反向击穿得以改善。When this semiconductor element is used, the dislocation density is low, so the dislocations in the epitaxial layer are reduced, and therefore, the reverse leakage current is reduced, and the reverse breakdown is improved.

在本发明的半导体元件中,氮化镓支撑底板的第一表面优选包括位错密度不大于1×108cm-2的第一区域和位错密度大于第一区域的位错密度的第二区域。In the semiconductor element of the present invention, the first surface of the gallium nitride supporting base plate preferably includes a first region having a dislocation density not greater than 1×10 8 cm −2 and a second region having a dislocation density greater than that of the first region. area.

使用该半导体元件时,在位错密度较低的区域上形成的外延层中的位错较低。因此,半导体元件的反向泄漏电流进一步下降,反向击穿得以改善。When this semiconductor element is used, the dislocations in the epitaxial layer formed on the region where the dislocation density is low are low. Therefore, the reverse leakage current of the semiconductor element is further reduced, and the reverse breakdown is improved.

另一方面,本发明提供一种外延基底,其包括:(a)氮化镓独立式基底,该基底包括第一表面和与第一表面相反的第二表面,其载流子浓度大于1×1018cm-3;和(b)放置在第一表面上的第一氮化镓外延膜。第一氮化镓外延膜的厚度至少是5微米,但不大于1000微米。第一氮化镓外延膜的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3In another aspect, the present invention provides an epitaxial substrate, which includes: (a) a gallium nitride free-standing substrate, the substrate includes a first surface and a second surface opposite to the first surface, the carrier concentration of which is greater than 1× 10 18 cm −3 ; and (b) a first gallium nitride epitaxial film disposed on the first surface. The thickness of the first GaN epitaxial film is at least 5 microns but not greater than 1000 microns. The carrier concentration of the first gallium nitride epitaxial film is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 .

使用该外延基底时,因为第一氮化镓外延膜的厚度至少是5微米,但不大于1000微米,还因为第一氮化镓外延膜的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层的厚度和载流子浓度进行设计,在没有穿通的情况下达到理想的击穿效果。所以提供的外延基底可用于反向击穿性能改善的半导体元件。When this epitaxial substrate is used, because the thickness of the first GaN epitaxial film is at least 5 microns but not more than 1000 µm, and because the carrier concentration of the first GaN epitaxial film is at least 1×10 14 cm -3 , but not greater than 1×10 17 cm -3 , so the thickness and carrier concentration of the epitaxial layer can be designed to achieve an ideal breakdown effect without punch-through. The epitaxial substrate thus provided can be used for a semiconductor element with improved reverse breakdown performance.

本发明的外延基底还可以包括放置在第一氮化镓外延膜上并且包括p型掺杂剂的第二氮化镓外延膜。使用该外延基底时,提供的外延基底可用于反向击穿性能改善的pn结二极管。另外,在本发明的外延基底中,优选用离子注入法将p型掺杂剂引入,或者优选用金属有机气相外延生长法形成p型外延层。The epitaxial substrate of the present invention may also include a second gallium nitride epitaxial film disposed on the first gallium nitride epitaxial film and including a p-type dopant. When using the epitaxial substrate, the provided epitaxial substrate can be used for a pn junction diode with improved reverse breakdown performance. In addition, in the epitaxial substrate of the present invention, the p-type dopant is preferably introduced by ion implantation, or the p-type epitaxial layer is preferably formed by metal-organic vapor phase epitaxy.

本发明的外延基底可以包括:(c)放置在第一氮化镓外延层中的p型半导体区域;和(d)放置在p型半导体区域中的n型半导体区域。第一氮化镓外延膜和氮化镓独立式基底优选具有n型导电性。The epitaxial substrate of the present invention may include: (c) a p-type semiconductor region disposed in the first gallium nitride epitaxial layer; and (d) an n-type semiconductor region disposed in the p-type semiconductor region. The first GaN epitaxial film and the GaN free-standing substrate preferably have n-type conductivity.

使用该外延基底时,提供的外延基底可用于反向击穿性能改善的晶体管。When the epitaxial substrate is used, the provided epitaxial substrate can be used for a transistor with improved reverse breakdown performance.

在本发明的外延基底中,优选用HVPE生长第一氮化镓外延膜。因为生长速度很快,所以能够在实际可行的时间内提供厚的外延膜。在本发明的外延基底中,优选用金属有机气相外延生长法形成第二氮化镓外延膜。用这样的外延基底可以提供高质量的外延膜。In the epitaxial substrate of the present invention, HVPE is preferably used to grow the first gallium nitride epitaxial film. Because the growth rate is fast, thick epitaxial films can be provided within a practical time. In the epitaxial substrate of the present invention, the second gallium nitride epitaxial film is preferably formed by metal organic vapor phase epitaxy. Using such an epitaxial substrate can provide a high-quality epitaxial film.

在本发明的外延基底中,氮化镓独立式基底第一表面的表面取向优选在不大于(0001)的+5度但至少是(0001)的-5度范围内。In the epitaxial substrate of the present invention, the surface orientation of the first surface of the gallium nitride free-standing substrate is preferably within a range of not more than +5 degrees of (0001) but at least -5 degrees of (0001).

用这样的外延基底可以提供低位错的GaN基底。Using such an epitaxial substrate can provide a low dislocation GaN substrate.

在本发明的外延基底中,氮化镓独立式基底第一表面的表面取向优选在不大于(1-100)或(11-20)的+5度但至少是(1-100)或(11-20)的-5度范围内。In the epitaxial substrate of the present invention, the surface orientation of the first surface of the gallium nitride free-standing substrate is preferably +5 degrees not greater than (1-100) or (11-20) but at least (1-100) or (11 -20) within -5 degrees.

用这样的外延基底可以提供外延层中的位错下降、反向泄漏电流下降、反向击穿改善的半导体元件用的外延基底。Using such an epitaxial substrate can provide an epitaxial substrate for semiconductor elements with reduced dislocations in the epitaxial layer, reduced reverse leakage current, and improved reverse breakdown.

在本发明的外延基底中,外延层中的位错密度优选不大于1×108cm-2In the epitaxial substrate of the present invention, the dislocation density in the epitaxial layer is preferably not more than 1×10 8 cm -2 .

使用该外延基底时,位错密度低,所以外延层中的位错下降。从而可以提供反向泄漏电流下降、反向击穿改善的半导体元件用的外延基底。When this epitaxial substrate is used, the dislocation density is low, so the dislocations in the epitaxial layer are reduced. Accordingly, it is possible to provide an epitaxial substrate for a semiconductor element with reduced reverse leakage current and improved reverse breakdown.

在本发明的外延基底中,氮化镓支撑底板的第一表面优选包括位错密度不大于1×108cm-2的第一区域和位错密度大于第一区域的位错密度的第二区域。In the epitaxial substrate of the present invention, the first surface of the gallium nitride supporting base plate preferably includes a first region with a dislocation density not greater than 1×10 8 cm -2 and a second region with a dislocation density greater than that of the first region. area.

使用该外延基底时,可以在位错密度较低的区域上形成半导体元件,由此外延层中的位错进一步降低。从而可以提供反向泄漏电流下降、反向击穿改善的半导体元件用的外延基底。When this epitaxial substrate is used, a semiconductor element can be formed on a region where the dislocation density is low, whereby dislocations in the epitaxial layer are further reduced. Accordingly, it is possible to provide an epitaxial substrate for a semiconductor element with reduced reverse leakage current and improved reverse breakdown.

通过结合附图阅读下面的说明书,可以更清楚本发明的上述及其他目的、特征和优点,在附图中,类似的符号表示同样的部件。The above and other objects, features and advantages of the present invention can be more clearly understood by reading the following description in conjunction with the accompanying drawings, in which similar symbols indicate the same components.

如上所述,本发明可以提供具有能够改善反向击穿性能的结构的III族氮化物元件。还可以提供用于这种半导体元件的外延基底。As described above, the present invention can provide a group III nitride device having a structure capable of improving reverse breakdown performance. An epitaxial substrate for such a semiconductor element can also be provided.

附图说明Description of drawings

图1是示出含有第一个实施方案的III族氮化物半导体层的半导体元件的图。FIG. 1 is a diagram showing a semiconductor element including a Group III nitride semiconductor layer of a first embodiment.

图2是示出样品A和样品B的I-V特征的图。FIG. 2 is a graph showing the I-V characteristics of Sample A and Sample B. FIG.

图3A是用于描述在具有厚外延膜的肖特基(Schottky)二极管中击穿现象的图。图3B是用于描述在具有薄外延膜的肖特基(Schottky)二极管中击穿现象的图。FIG. 3A is a diagram for describing a breakdown phenomenon in a Schottky diode having a thick epitaxial film. FIG. 3B is a diagram for describing a breakdown phenomenon in a Schottky diode having a thin epitaxial film.

图4是示出样品A和样品C的I-V特征的图。FIG. 4 is a graph showing the I-V characteristics of Sample A and Sample C. FIG.

图5是示出样品A和样品D的I-V特征的图。FIG. 5 is a graph showing the I-V characteristics of Sample A and Sample D. FIG.

图6是示出样品E、样品F和样品G的I-V特征的图。FIG. 6 is a graph showing I-V characteristics of Sample E, Sample F, and Sample G. FIG.

图7是示出含有第二个实施方案的III族氮化物半导体层的半导体元件的图。FIG. 7 is a diagram showing a semiconductor element including a Group III nitride semiconductor layer of a second embodiment.

图8是示出样品H的I-V特征的图。FIG. 8 is a graph showing the I-V characteristics of Sample H. FIG.

图9A是示出第四个实施方案的晶体管的图。图9B是示出沿图9A中的II-II线剖开的剖视图。FIG. 9A is a diagram showing a transistor of a fourth embodiment. FIG. 9B is a sectional view showing a section taken along line II-II in FIG. 9A .

图10A-10C是示出根据第五个实施方案生产外延基底的图。图10D-10G是示出生产外延基底的图。10A-10C are diagrams showing production of an epitaxial substrate according to a fifth embodiment. 10D-10G are diagrams illustrating production of an epitaxial substrate.

图11A是示出在独立式基底中高置换区域和低置换区域的一种排列的图。图11B是示出在独立式基底中高置换区域和低置换区域的另一种排列的图。FIG. 11A is a diagram showing an arrangement of high displacement regions and low displacement regions in a freestanding substrate. 11B is a diagram showing another arrangement of high displacement regions and low displacement regions in a freestanding substrate.

具体实施方式Detailed ways

通过下面的说明和附图易于理解本发明的前景。下面说明本发明实施方案的半导体元件和外延基底。如果可能,用类似的符号标注相同的部件。The scope of the present invention is readily understood from the following description and accompanying drawings. A semiconductor element and an epitaxial substrate according to an embodiment of the present invention will be described below. Where possible, label identical parts with similar symbols.

(第一个实施方案)(first implementation)

图1示出本发明第一个实施方案的III族氮化物半导体元件。该半导体元件是肖特基(Schottky)二极管11。肖特基(Schottky)二极管11上装备有氮化镓支撑底板13、氮化镓外延层15、欧姆电极17和肖特基(Schottky)电极19。氮化镓支撑底板13包括第一表面13a和与第一表面相反的第二表面13b,其载流子浓度大于1×1018cm-3。氮化镓外延层15放置在第一表面13a上。欧姆电极17放置在第二表面13b上。肖特基(Schottky)电极19放置在氮化镓外延层15上。氮化镓外延层15的厚度D1是5微米或更大并且1000微米或更小。另外,氮化镓外延层15的载流子浓度是1×1014cm-3或更大并且1×1017cm-3或更小。当载流子浓度是1×1014cm-3或更大时,“接通”电阻可以保持很低。当载流子浓度是1×1017cm-3或更小时,可以增加击穿电压。Fig. 1 shows a Group III nitride semiconductor element of the first embodiment of the present invention. The semiconductor element is a Schottky diode 11 . The Schottky diode 11 is equipped with a gallium nitride support substrate 13 , a gallium nitride epitaxial layer 15 , an ohmic electrode 17 and a Schottky electrode 19 . The gallium nitride supporting base 13 includes a first surface 13a and a second surface 13b opposite to the first surface, and its carrier concentration is greater than 1×10 18 cm −3 . A gallium nitride epitaxial layer 15 is placed on the first surface 13a. Ohmic electrodes 17 are placed on the second surface 13b. A Schottky electrode 19 is placed on the GaN epitaxial layer 15 . Thickness D1 of gallium nitride epitaxial layer 15 is 5 micrometers or more and 1000 micrometers or less. In addition, the carrier concentration of gallium nitride epitaxial layer 15 is 1×10 14 cm −3 or more and 1×10 17 cm −3 or less. When the carrier concentration is 1×10 14 cm -3 or more, the "on" resistance can be kept low. When the carrier concentration is 1×10 17 cm −3 or less, the breakdown voltage can be increased.

在这种肖特基(Schottky)二极管11中,因为氮化镓外延层15的厚度是5微米或更大并且1000微米或更小,还因为载流子浓度是1×1014cm-3或更大并且1×1017cm-3或更小,所以可以以合适的方式设计外延层厚度和载流子浓度,以提供不会导致穿通的理想击穿效果。从而可以增加肖特基(Schottky)二极管11的击穿电压。In this Schottky diode 11, since the thickness of gallium nitride epitaxial layer 15 is 5 micrometers or more and 1000 micrometers or less, and because the carrier concentration is 1×10 14 cm −3 or larger and 1×10 17 cm −3 or smaller, so the epitaxial layer thickness and carrier concentration can be designed in a suitable manner to provide the desired breakdown effect without causing punch-through. Thereby, the breakdown voltage of the Schottky diode 11 can be increased.

GaN基底的载流子浓度高于外延层的载流子浓度。如图1所示,在肖特基(Schottky)二极管11中,欧姆电极17放置在整个第二表面13b上。肖特基(Schottky)电极19形成在外延层的一部分表面上,例如大致在元件中心的一个圆上。对于肖特基(Schottky)电极19来说,可以使用诸如镍金(Ni/Au)的材料,但是也可以使用Pt/Au或Au。氮化镓支撑底板13和氮化镓外延层15作为n型导体。氮化镓外延层15直接在氮化镓支撑底板13上均相外延生长。氮化镓支撑底板13的厚度D2优选如至少是100微米,但是不大于700微米。The carrier concentration of the GaN substrate is higher than that of the epitaxial layer. As shown in FIG. 1, in a Schottky diode 11, an ohmic electrode 17 is placed on the entire second surface 13b. A Schottky electrode 19 is formed on a part of the surface of the epitaxial layer, for example, on a circle approximately in the center of the element. For the Schottky electrodes 19, materials such as nickel gold (Ni/Au) can be used, but Pt/Au or Au can also be used. The gallium nitride supporting substrate 13 and the gallium nitride epitaxial layer 15 serve as n-type conductors. The gallium nitride epitaxial layer 15 is grown homogeneously and epitaxially directly on the gallium nitride supporting substrate 13 . The thickness D2 of the gallium nitride supporting base 13 is preferably, for example, at least 100 micrometers, but not greater than 700 micrometers.

(第一个工作例)(first working example)

制备HPVE生产的(0001)面GaN独立式基底。用下述步骤生产肖特基(Schottky)二极管。n型导体GaN独立式基底的载流子浓度是3×1018cm-3,厚度是400微米。在该基底中,平均位错密度是5×106cm-2。利用HVPE在GaN独立式基底上生长载流子浓度是5×1015cm-3、厚度是20微米的n型导体外延膜,从而形成外延基底(后面称为样品A)。在该基底背面上形成欧姆电极,在外延膜上形成肖特基(Schottky)电极。在进行了有机清洁后的整个基底背面表面上形成欧姆电极。为了形成欧姆电极,用EB蒸汽沉积法形成Ti/Al/Ti/Au(20nm/100nm/20nm/300nm)。形成欧姆电极膜后,在600℃下合金化约1分钟。用电阻加热沉积法形成作为500nm金膜的肖特基(Schottky)电极。肖特基(Schottky)电极的形状是直径为200微米的圆。在形成欧姆电极和肖特基(Schottky)电极前,并且在沉积前,在室温下用HCl溶液(氢氯酸1∶纯净水1)将外延膜表面处理1分钟。The (0001) plane GaN free-standing substrate produced by HPVE was prepared. Schottky diodes were produced using the following procedure. The carrier concentration of the n-type conductor GaN free-standing substrate is 3×10 18 cm -3 , and the thickness is 400 microns. In this substrate, the average dislocation density was 5×10 6 cm -2 . An n-type conductor epitaxial film with a carrier concentration of 5×10 15 cm −3 and a thickness of 20 μm was grown on a GaN freestanding substrate by HVPE to form an epitaxial substrate (hereinafter referred to as sample A). Ohmic electrodes are formed on the back surface of the substrate, and Schottky electrodes are formed on the epitaxial film. Ohmic electrodes are formed on the entire rear surface of the substrate after organic cleaning. To form an ohmic electrode, Ti/Al/Ti/Au (20nm/100nm/20nm/300nm) was formed by EB vapor deposition. After forming the ohmic electrode film, alloying was carried out at 600° C. for about 1 minute. A Schottky electrode was formed as a 500 nm gold film by resistance heating deposition. The shape of the Schottky electrode is a circle with a diameter of 200 microns. Before the formation of ohmic electrodes and Schottky electrodes, and before deposition, the surface of the epitaxial film was treated with HCl solution (hydrochloric acid 1:purified water 1) at room temperature for 1 minute.

利用HVPE在另一个GaN独立式基底上生长载流子浓度是5×1015cm-3、厚度是3微米的外延膜,从而形成外延基底(后面称为样品B)。用上述同样的方法形成欧姆电极和肖特基(Schottky)电极。An epitaxial film with a carrier concentration of 5×10 15 cm −3 and a thickness of 3 μm was grown on another GaN freestanding substrate by HVPE to form an epitaxial substrate (hereinafter referred to as sample B). Ohmic electrodes and Schottky electrodes were formed in the same manner as above.

图2是示出样品A和样品B的I-V特征的图。在图2中,特征曲线CA表示样品A的特征,特征曲线CB表示样品B的特征。图3A是用于描述在具有厚外延膜的肖特基(Schottky)二极管中击穿现象的图。图3B是用于描述在具有薄外延膜的肖特基(Schottky)二极管中击穿现象的图。样品B的反向击穿电压小于样品A的反向击穿电压。其原因如下。如图3A所示,在样品A中,外延层足够厚,当施加的电压增加时,在耗尽层DepA达到基底和外延膜之间的边界面之前在肖特基(Schottky)电极和外延膜之间的边界面附近发生冲击电离,从而导致反向泄漏电流的流动。这种冲击电离决定了反向击穿电压。如图3B所示,在样品B中,外延膜没有足够的厚度,当施加的电压增加时,发生穿通现象,其中,在肖特基(Schottky)电极下面的外延表面处出现冲击电离之前耗尽层DepB就到达了基底和外延膜之间的边界面。这样就降低了反向击穿电压。FIG. 2 is a graph showing IV characteristics of Sample A and Sample B. FIG. In FIG. 2 , the characteristic curve C A represents the characteristics of sample A, and the characteristic curve C B represents the characteristics of sample B. FIG. 3A is a diagram for describing a breakdown phenomenon in a Schottky diode having a thick epitaxial film. FIG. 3B is a diagram for describing a breakdown phenomenon in a Schottky diode having a thin epitaxial film. The reverse breakdown voltage of sample B is less than that of sample A. The reason for this is as follows. As shown in Figure 3A, in Sample A, the epitaxial layer is thick enough that when the applied voltage increases, the depletion layer DepA reaches the boundary surface between the substrate and the epitaxial film before the Schottky electrode and the epitaxial film Impact ionization occurs near the boundary surface between them, resulting in the flow of reverse leakage current. This impact ionization determines the reverse breakdown voltage. As shown in Fig. 3B, in Sample B, the epitaxial film does not have sufficient thickness, and when the applied voltage is increased, a punch-through phenomenon occurs, in which the epitaxial surface is depleted before impact ionization occurs at the epitaxial surface below the Schottky electrode. Layer DepB reaches the interface between the substrate and the epitaxial film. This reduces the reverse breakdown voltage.

(第二个工作例)(second working example)

制备HPVE生产的(0001)面GaN独立式基底。n型导体GaN独立式基底的载流子浓度是3×1018cm-3,厚度是400微米。在该基底中,平均位错密度是5×105cm-2。利用HVPE在GaN独立式基底上生长载流子浓度是5×1015cm-3、厚度是20微米的n型导体外延膜,从而形成外延基底(后面称为样品C)。用在第一个工作例中使用的方法在该外延基底上形成肖特基(Schottky)二极管。The (0001) plane GaN free-standing substrate produced by HPVE was prepared. The carrier concentration of the n-type conductor GaN free-standing substrate is 3×10 18 cm -3 , and the thickness is 400 microns. In this substrate, the average dislocation density was 5×10 5 cm -2 . An n-type conductor epitaxial film with a carrier concentration of 5×10 15 cm −3 and a thickness of 20 μm was grown on a GaN freestanding substrate by HVPE to form an epitaxial substrate (hereinafter referred to as sample C). A Schottky diode was formed on the epitaxial substrate by the method used in the first working example.

图4是示出样品A和样品C的I-V特征的图。在图4中,特征曲线CA表示样品A的特征,特征曲线CC表示样品C的特征。在样品A的GaN独立式基底中,平均位错密度是5×106cm-2,而在样品C的GaN独立式基底中,平均位错密度是5×105cm-2。与样品A的反向击穿电压相比,样品C的反向击穿电压高。换句话说,可以认为,支撑底板中的位错增加了反向泄漏电流。FIG. 4 is a graph showing the IV characteristics of Sample A and Sample C. FIG. In FIG. 4 , the characteristic curve C A represents the characteristics of sample A, and the characteristic curve C C represents the characteristics of sample C. In the GaN free-standing substrate of Sample A, the average dislocation density was 5×10 6 cm −2 , whereas in the GaN free-standing substrate of Sample C, the average dislocation density was 5×10 5 cm −2 . Compared with the reverse breakdown voltage of sample A, the reverse breakdown voltage of sample C is high. In other words, it can be considered that dislocations in the supporting base plate increase the reverse leakage current.

(第三个工作例)(third working example)

制备HPVE生产的(1-100)面GaN独立式基底。n型导体GaN独立式基底的载流子浓度是3×1018cm-3,厚度是400微米。在该基底中,平均位错密度是5×105cm-2。利用HVPE在GaN独立式基底上生长载流子浓度是5×1015cm-3、厚度是20微米的n型导体外延膜,从而形成外延基底(样品D)。用在第一个工作例中使用的方法在该外延基底上形成肖特基(Schottky)二极管。Preparation of (1-100) plane GaN free-standing substrate produced by HPVE. The carrier concentration of the n-type conductor GaN free-standing substrate is 3×10 18 cm -3 , and the thickness is 400 microns. In this substrate, the average dislocation density was 5×10 5 cm -2 . An n-type conductor epitaxial film with a carrier concentration of 5×10 15 cm -3 and a thickness of 20 μm was grown on a GaN freestanding substrate by HVPE to form an epitaxial substrate (sample D). A Schottky diode was formed on the epitaxial substrate by the method used in the first working example.

图5是示出样品A和样品D的I-V特征的图。在图5中,特征曲线CA表示样品A的特征,特征曲线CD表示样品D的特征。因为样品A中的GaN独立式基底具有(0001)面,而样品D中的GaN独立式基底具有(1-100)面,所以与样品A的反向击穿相比,样品C的反向击穿性能得以改善。更具体地说,当氮化镓膜在(1-100)面上外延生长时,不会在[0001]方向上发生螺纹位错。所以在该肖特基(Schottky)二极管中泄漏电流非常小。FIG. 5 is a graph showing the IV characteristics of Sample A and Sample D. FIG. In FIG. 5, the characteristic curve CA represents the characteristics of sample A, and the characteristic curve CD represents the characteristics of sample D. Since the GaN free-standing substrate in sample A has a (0001) plane and the GaN free-standing substrate in sample D has a (1-100) plane, the reverse breakdown of sample C Wearability is improved. More specifically, when a gallium nitride film is epitaxially grown on a (1-100) plane, threading dislocations do not occur in the [0001] direction. So the leakage current in the Schottky diode is very small.

(第四个工作例)(fourth working example)

制备HPVE生产的(0001)面GaN独立式基底。n型导体GaN独立式基底的载流子浓度是3×1018cm-3,厚度是400微米。利用HVPE在GaN独立式基底上生长载流子浓度是1×1017cm-3、厚度是10、5和3微米的n型导体外延膜,从而形成外延基底(样品E、F、G)。用在第一个工作例中使用的方法在这些外延基底上形成肖特基(Schottky)二极管。The (0001) plane GaN free-standing substrate produced by HPVE was prepared. The carrier concentration of the n-type conductor GaN free-standing substrate is 3×10 18 cm -3 , and the thickness is 400 microns. HVPE was used to grow n-type conductor epitaxial films with a carrier concentration of 1×10 17 cm -3 and a thickness of 10, 5 and 3 microns on GaN free-standing substrates to form epitaxial substrates (samples E, F, and G). Schottky diodes were formed on these epitaxial substrates by the method used in the first working example.

图6示出上述样品E、F和G的I-V特征。在图6中,特征曲线CE、CF、CG分别表示样品E、F、G的特征。样品E和样品F显示出大致相同的反向击穿电压,但是样品G的反向击穿电压小于样品E和样品F的反向击穿电压。在样品G中,可以认为,当施加的电压增加时,在外延膜中的耗尽层到达基底和外延膜之间的边界面时发生穿通现象。从而降低了反向击穿电压。所以外延膜的厚度至少应当是5微米。Figure 6 shows the IV characteristics of samples E, F and G described above. In FIG. 6, characteristic curves CE , CF , and CG represent characteristics of samples E, F, and G, respectively. Sample E and Sample F exhibit approximately the same reverse breakdown voltage, but the reverse breakdown voltage of Sample G is smaller than that of Sample E and Sample F. In sample G, it is considered that a punch-through phenomenon occurs when the depletion layer in the epitaxial film reaches the boundary surface between the substrate and the epitaxial film when the applied voltage is increased. Thereby reducing the reverse breakdown voltage. Therefore, the thickness of the epitaxial film should be at least 5 micrometers.

在功率转换器件如(Schottky)二极管的漂移层(n层)中,为了改善击穿性能,载流子浓度优选至少是1×1017cm-3。为了防止穿通现象,重要的是要使外延厚度适合于载流子浓度。在载流子浓度是1×1017cm-3时,厚度为5微米或更大的外延膜就能够提供对于高击穿性能来说足够厚度的外延膜。In a drift layer (n layer) of a power conversion device such as a (Schottky) diode, the carrier concentration is preferably at least 1×10 17 cm −3 in order to improve breakdown performance. To prevent the punch-through phenomenon, it is important to adapt the epitaxial thickness to the carrier concentration. When the carrier concentration is 1×10 17 cm −3 , an epitaxial film having a thickness of 5 μm or more can provide an epitaxial film of sufficient thickness for high breakdown performance.

(第二个实施方案)(second implementation)

图7示出第二个实施方案的含有III族半导体层的半导体元件。该半导体元件是pn结二极管31。pn结二极管31包括:氮化镓支撑底板33;第一氮化镓外延层35;第一欧姆电极37;第二氮化镓外延膜39;第二欧姆电极41。氮化镓支撑底板33包括第一表面33a和与第一表面33a相反的第二表面33b。其载流子浓度大于1×1018cm-3。氮化镓支撑底板33具有n型导电性。第一氮化镓外延层35的厚度至少是5微米且不大于1000微米。第一氮化镓外延层35的载流子浓度至少是1×1014cm-3且不大于1×1017cm-3。第一氮化镓外延层35放置在第一表面33a上。第一欧姆电极(如阴极)37放置在第二表面33b上。第二氮化镓外延膜39放置在第一氮化镓外延层35上并且包括p型掺杂剂。第二欧姆电极(如阳极)41放置在第二氮化镓外延膜39上。FIG. 7 shows a semiconductor element including a Group III semiconductor layer of a second embodiment. This semiconductor element is a pn junction diode 31 . The pn junction diode 31 includes: a gallium nitride support base plate 33 ; a first gallium nitride epitaxial layer 35 ; a first ohmic electrode 37 ; a second gallium nitride epitaxial film 39 ; and a second ohmic electrode 41 . The gallium nitride supporting base 33 includes a first surface 33a and a second surface 33b opposite to the first surface 33a. Its carrier concentration is greater than 1×10 18 cm -3 . The gallium nitride supporting base 33 has n-type conductivity. The thickness of the first GaN epitaxial layer 35 is at least 5 microns and not greater than 1000 microns. The carrier concentration of the first gallium nitride epitaxial layer 35 is at least 1×10 14 cm −3 and not more than 1×10 17 cm −3 . A first gallium nitride epitaxial layer 35 is placed on the first surface 33a. A first ohmic electrode (such as a cathode) 37 is placed on the second surface 33b. The second gallium nitride epitaxial film 39 is placed on the first gallium nitride epitaxial layer 35 and includes a p-type dopant. A second ohmic electrode (such as an anode) 41 is placed on the second GaN epitaxial film 39 .

使用这种pn结二极管31时,因为第一氮化镓外延层35的厚度至少是5微米且不大于1000微米,还因为第一氮化镓外延层35的载流子浓度至少是1×1014cm-3且不大于1×1017cm-3,所以可以通过适当设计外延层厚度和载流子浓度来达到不会产生穿通的理想击穿效果。When using this pn junction diode 31, because the thickness of the first gallium nitride epitaxial layer 35 is at least 5 microns and not more than 1000 microns, and because the carrier concentration of the first gallium nitride epitaxial layer 35 is at least 1×10 14 cm -3 and not greater than 1×10 17 cm -3 , so the ideal breakdown effect without punch-through can be achieved by properly designing the epitaxial layer thickness and carrier concentration.

氮化镓支撑底板33和第一氮化镓外延层35具有n型导电性,第二氮化镓外延层39具有p型导电性。GaN独立式基底33的载流子浓度高于外延层35的载流子浓度。第一氮化镓外延层35的载流子浓度低于第二氮化镓外延层39的载流子浓度。因此,耗尽层主要向第一氮化镓外延层35延伸。可以用第一个实施方案的肖特基(Schottky)二极管11的厚度和载流子浓度设计外延层35的厚度和载流子浓度。氮化镓外延层39的载流子浓度优选至少是1×1017cm-3The GaN supporting substrate 33 and the first GaN epitaxial layer 35 have n-type conductivity, and the second GaN epitaxial layer 39 has p-type conductivity. The carrier concentration of GaN free-standing substrate 33 is higher than that of epitaxial layer 35 . The carrier concentration of the first GaN epitaxial layer 35 is lower than the carrier concentration of the second GaN epitaxial layer 39 . Therefore, the depletion layer mainly extends toward the first GaN epitaxial layer 35 . The thickness and carrier concentration of the epitaxial layer 35 can be designed with the thickness and carrier concentration of the Schottky diode 11 of the first embodiment. The gallium nitride epitaxial layer 39 preferably has a carrier concentration of at least 1×10 17 cm −3 .

在pn结二极管31中,欧姆电极(阴极)37放置在基底33的整个第二表面33b上。用于阴极的材料例如可以是Ti/Al/Ti/Au(20nm/100nm/20nm/300nm)。用于阳极的材料例如可以是Ni/Au(50nm/100nm)。第一氮化镓外延层35直接在氮化镓支撑底板33上均相外延生长。第二氮化镓外延层39直接在第一氮化镓外延层35上均相外延生长。第一氮化镓外延层35的厚度优选大于第二氮化镓外延层39的厚度。第二氮化镓外延层的厚度D3优选如至少是0.1微米,但是不大于10微米。In the pn junction diode 31 , an ohmic electrode (cathode) 37 is placed on the entire second surface 33 b of the substrate 33 . The material used for the cathode can be, for example, Ti/Al/Ti/Au (20nm/100nm/20nm/300nm). The material used for the anode can be, for example, Ni/Au (50nm/100nm). The first GaN epitaxial layer 35 is grown homogeneously and epitaxially directly on the GaN supporting substrate 33 . The second GaN epitaxial layer 39 is homogeneously epitaxially grown directly on the first GaN epitaxial layer 35 . The thickness of the first GaN epitaxial layer 35 is preferably greater than the thickness of the second GaN epitaxial layer 39 . The thickness D3 of the second gallium nitride epitaxial layer is preferably, for example, at least 0.1 microns, but not greater than 10 microns.

(第五个工作例)(fifth working example)

制备HPVE生产的(0001)面GaN独立式基底。n型导体GaN独立式基底的载流子浓度是3×1018cm-3,厚度是400微米。该基底的位错密度是5×105cm-3。利用HVPE在GaN独立式基底上生长载流子浓度是5×1015cm-3、厚度是20微米的n型导体外延膜,从而形成外延基底。然后用金属有机气相外延生长法形成p型导体GaN层,从而形成含pn结的外延基底。用5×1019cm-3的Mg作为掺杂剂进行掺杂,其厚度是1微米。载流子浓度是1×1018cm-3。用下述方法形成p型欧姆电极:首先用Cl2基RIE将表面p型层干燥蚀刻成深度约为2微米的台面形状。在台面上进行Ni/Au电阻加热真空蒸汽沉积,然后在700℃的氮气中进行热处理。P型电极的形状例如可以是直径为200微米的圆。用下述方法形成n型欧姆电极:在基底的整个背面表面上进行EB真空蒸汽沉积Ti/Al/Ti/Au(20nm/100nm/20nm/300nm),然后在600℃的氮气中热处理1分钟(样品H)。图8示出样品H的I-V特征。图中所示的反向击穿电压类似于样品C的反向击穿电压,样品C是具有相同结构的肖特基(Schottky)二极管。The (0001) plane GaN free-standing substrate produced by HPVE was prepared. The carrier concentration of the n-type conductor GaN free-standing substrate is 3×10 18 cm -3 , and the thickness is 400 microns. The dislocation density of this substrate was 5×10 5 cm -3 . An n-type conductor epitaxial film with a carrier concentration of 5×10 15 cm -3 and a thickness of 20 microns is grown on a GaN free-standing substrate by HVPE, thereby forming an epitaxial substrate. Then a p-type conductor GaN layer is formed by a metal-organic vapor phase epitaxial growth method, thereby forming an epitaxial substrate containing a pn junction. Doping was performed with 5×10 19 cm −3 Mg as a dopant, and its thickness was 1 μm. The carrier concentration was 1×10 18 cm -3 . The p-type ohmic electrode was formed by the following method: first, the surface p-type layer was dry-etched into a mesa shape with a depth of about 2 micrometers using Cl 2 -based RIE. Ni/Au resistance heating vacuum vapor deposition was carried out on the mesa, followed by heat treatment in nitrogen at 700 °C. The shape of the P-type electrode can be, for example, a circle with a diameter of 200 microns. The n-type ohmic electrode was formed by the following method: EB vacuum vapor deposition of Ti/Al/Ti/Au (20nm/100nm/20nm/300nm) on the entire back surface of the substrate, followed by heat treatment in nitrogen at 600°C for 1 minute ( Sample H). Figure 8 shows the IV characteristics of sample H. The reverse breakdown voltage shown in the figure is similar to that of sample C, which is a Schottky diode with the same structure.

(第三个实施方案)(third implementation)

图9A是示出第三个实施方案的晶体管。图9B是沿图9A中的II-II线剖开的剖视图。III族氮化物半导体MIS场效应晶体管71包括:氮化镓支撑底板53;氮化镓外延层55;p型半导体区域57;n型半导体区域59;源电极61;漏电极63;门电极75。氮化镓支撑底板53包括:第一表面53a和与第一表面53a相反的第二表面53b。载流子浓度大于1×1018cm-3。氮化镓外延层55放置在第一表面53a上。p型半导体区域57放置在氮化镓外延层55上。n型半导体区域59放置在p型半导体区域57中。源电极61放置在高掺杂的n型半导体区域59上。漏电极63放置在第二表面53b上。门电极75放置在形成于氮化镓外延层55上的绝缘层77上。p型半导体区域57包括放置在门电极75下面的延伸部分57b。用于绝缘层的材料可以是氧化硅膜、氧氮化硅膜、氮化硅膜、氧化铝、氮化铝、AlGaN等。氮化镓外延层55的厚度至少是5微米,但不大于1000微米。氮化镓外延层55的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3Fig. 9A is a diagram showing a transistor of the third embodiment. Fig. 9B is a cross-sectional view taken along line II-II in Fig. 9A. Group III nitride semiconductor MIS field effect transistor 71 includes: gallium nitride support substrate 53 ; gallium nitride epitaxial layer 55 ; p-type semiconductor region 57 ; n-type semiconductor region 59 ; source electrode 61 ; drain electrode 63 ; gate electrode 75 . The gallium nitride supporting base 53 includes: a first surface 53a and a second surface 53b opposite to the first surface 53a. The carrier concentration is greater than 1×10 18 cm -3 . A gallium nitride epitaxial layer 55 is placed on the first surface 53a. A p-type semiconductor region 57 is placed on the gallium nitride epitaxial layer 55 . An n-type semiconductor region 59 is placed in the p-type semiconductor region 57 . The source electrode 61 is placed on the highly doped n-type semiconductor region 59 . The drain electrode 63 is placed on the second surface 53b. Gate electrode 75 is placed on insulating layer 77 formed on gallium nitride epitaxial layer 55 . The p-type semiconductor region 57 includes an extension portion 57b placed under the gate electrode 75 . The material used for the insulating layer may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, aluminum oxide, aluminum nitride, AlGaN, or the like. The GaN epitaxial layer 55 has a thickness of at least 5 microns but not greater than 1000 microns. The gallium nitride epitaxial layer 55 has a carrier concentration of at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 .

晶体管71具有垂直结构,源电极61放置在n型半导体区域59上,漏电极63放置在基底的第二表面53b上,电流从一个电极流向另一个电极。因为氮化镓外延层55的厚度至少是5微米,但不大于1000微米,还因为氮化镓外延层55的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以通过适当设计外延层厚度和载流子浓度来达到不会产生穿通的理想击穿效果。The transistor 71 has a vertical structure, the source electrode 61 is placed on the n-type semiconductor region 59, the drain electrode 63 is placed on the second surface 53b of the substrate, and current flows from one electrode to the other. Because the thickness of the GaN epitaxial layer 55 is at least 5 microns but not more than 1000 microns, and because the carrier concentration of the GaN epitaxial layer 55 is at least 1×10 14 cm −3 but not more than 1×10 17 cm -3 , so the ideal breakdown effect without punch-through can be achieved by properly designing the epitaxial layer thickness and carrier concentration.

通过用离子注入法形成p型半导体区域,可以形成具有平面结构的半导体元件,该平面结构在选择区域中具有p导电性半导体。对于p型掺杂剂来说,可以使用镁等。通过用离子注入法形成n型半导体区域,可以形成具有平面结构的半导体元件,该平面结构具有n导电性半导体。对于n型掺杂剂来说,可以使用硅等。p型半导体区域57将n型半导体区域59与外延层55电隔离。p型半导体区域57包括放置在绝缘膜下面的延伸部分57b,绝缘膜在门电极下面。当在门电极75上施加电势时,在绝缘膜和p型区域57的边界面处形成n型反向层,电势由n型半导体区域59通过载流子反向层到达外延层55。p型半导体区域57的深度优选至少是0.1微米,但不大于3微米。p型半导体区域57表面部分的载流子浓度优选至少是5×1017cm-3。如图9A所示,门电极75的分支75a在源电极61的分支61a之间。电极75、61的角被圆整,以防止击穿。By forming a p-type semiconductor region by ion implantation, it is possible to form a semiconductor element having a planar structure having a p-conductive semiconductor in a selected region. For the p-type dopant, magnesium or the like can be used. By forming an n-type semiconductor region by ion implantation, a semiconductor element having a planar structure having n-conductive semiconductor can be formed. For the n-type dopant, silicon or the like can be used. The p-type semiconductor region 57 electrically isolates the n-type semiconductor region 59 from the epitaxial layer 55 . The p-type semiconductor region 57 includes an extension portion 57b placed under the insulating film under the gate electrode. When a potential is applied to the gate electrode 75 , an n-type inversion layer is formed at the boundary surface between the insulating film and the p-type region 57 , and the potential reaches the epitaxial layer 55 from the n-type semiconductor region 59 through the carrier inversion layer. The depth of the p-type semiconductor region 57 is preferably at least 0.1 micrometers but not more than 3 micrometers. The carrier concentration of the surface portion of the p-type semiconductor region 57 is preferably at least 5×10 17 cm −3 . As shown in FIG. 9A , the branch 75 a of the gate electrode 75 is between the branches 61 a of the source electrode 61 . The corners of the electrodes 75, 61 are rounded to prevent breakdown.

在第一至第三个实施方案的半导体元件11、31、71中,氮化镓支撑底板第一表面的表面取向优选是(0001)面(包括结晶学上等同的面)。结果可以提供低位错的GaN基底。另外,在半导体元件11、31、71中,氮化镓支撑底板第一表面的表面取向优选是(1-100)面(包括结晶学上等同的面)或(11-20)面(包括结晶学上等同的面)。考虑到表面取向中的不一致性,这些优选不超过从这些晶面的+5度且不小于从这些晶面的-5度。使用半导体元件11、31、71时,外延层中的位错下降,反向泄漏电流下降,反向击穿得以改善。另外,使用半导体元件11、31、71时,氮化镓支撑底板第一表面的位错密度优选至少是1×108cm-2。使用半导体元件11、31、71时,低位错密度降低了外延层中的位错,因此,反向泄漏电流下降,反向击穿性能得以改善。另外,在半导体元件11、31、71中,氮化镓支撑底板的第一表面优选包括位错密度不大于1×108cm-2的第一区域和位错密度大于第一区域的位错密度的第二区域。使用这样的半导体元件11、31、71时,如果在位错密度较低的区域中形成半导体元件,则外延层中的位错可以进一步降低。因此,反向泄漏电流进一步下降,反向击穿性能得以改善。In the semiconductor elements 11, 31, 71 of the first to third embodiments, the surface orientation of the first surface of the gallium nitride supporting substrate is preferably a (0001) plane (including crystallographically equivalent planes). As a result, a low-dislocation GaN substrate can be provided. In addition, in the semiconductor elements 11, 31, 71, the surface orientation of the first surface of the gallium nitride supporting substrate is preferably a (1-100) plane (including crystallographically equivalent planes) or a (11-20) plane (including crystallographically equivalent planes) or a (11-20) plane (including crystallographically equivalent planes). academic equivalent). These are preferably not more than +5 degrees from these crystal planes and not less than -5 degrees from these crystal planes in consideration of inconsistencies in surface orientation. When the semiconductor elements 11, 31, 71 are used, the dislocations in the epitaxial layer are reduced, the reverse leakage current is reduced, and the reverse breakdown is improved. In addition, when the semiconductor element 11, 31, 71 is used, the dislocation density on the first surface of the gallium nitride supporting base is preferably at least 1×10 8 cm −2 . When the semiconductor element 11, 31, 71 is used, the low dislocation density reduces the dislocations in the epitaxial layer, therefore, the reverse leakage current is reduced and the reverse breakdown performance is improved. In addition, in the semiconductor element 11, 31, 71, the first surface of the gallium nitride supporting base plate preferably includes a first region with a dislocation density not greater than 1×10 8 cm −2 and a dislocation density greater than the first region. The second area of density. When such semiconductor elements 11, 31, 71 are used, dislocations in the epitaxial layer can be further reduced if the semiconductor elements are formed in regions where the dislocation density is low. Therefore, the reverse leakage current is further reduced and the reverse breakdown performance is improved.

(第五个实施方案)(fifth implementation)

图10A-10C示出根据第五个实施方案生产外延基底。如图10A所示,制备氮化镓独立式基底83。n导电性氮化镓独立式基底83的载流子浓度大于1×1018cm-3。如图10B所示,外延膜85层放在氮化镓独立式基底83的第一表面83a上。氮化镓外延膜85的厚度至少是5微米,但不大于1000微米。氮化镓外延膜85例如可以具有n型导电性,其载流子浓度至少是1×1014cm-3,但不大于1×1016cm-3。这样就产生了外延基底81。可以用这样的基底生产第一至第三个实施方案的半导体元件。优选用HVPE生长氮化镓外延膜85。10A-10C illustrate the production of an epitaxial substrate according to a fifth embodiment. As shown in FIG. 10A, a gallium nitride free-standing substrate 83 is prepared. The carrier concentration of the n-conductive GaN free-standing substrate 83 is greater than 1×10 18 cm −3 . As shown in FIG. 10B , an epitaxial film 85 is placed on the first surface 83 a of the GaN freestanding substrate 83 . GaN epitaxial film 85 has a thickness of at least 5 micrometers but not more than 1000 micrometers. Gallium nitride epitaxial film 85 may have n-type conductivity, for example, and its carrier concentration is at least 1×10 14 cm −3 but not more than 1×10 16 cm −3 . Thus, epitaxial substrate 81 is produced. The semiconductor elements of the first to third embodiments can be produced using such a substrate. The gallium nitride epitaxial film 85 is preferably grown by HVPE.

如图10C所示,肖特基(Schottky)电极膜87层放在外延基底81的外延膜85表面上,欧姆电极膜89层放在基底83的第二表面83b上。因为氮化镓外延膜85的厚度至少是5微米,但不大于1000微米,还因为载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层厚度和载流子浓度进行设计,以达到在肖特基(Schottky)电极膜87和欧姆电极膜89之间施加电势时没有穿通的理想击穿效果。这样就提供了击穿性能改善的半导体元件用的外延基底。As shown in FIG. 10C , a Schottky electrode film 87 layer is placed on the epitaxial film 85 surface of the epitaxial substrate 81 , and an ohmic electrode film 89 layer is placed on the second surface 83 b of the substrate 83 . Since the thickness of GaN epitaxial film 85 is at least 5 µm but not more than 1000 µm, and because the carrier concentration is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 , it is possible to The thickness of the epitaxial layer and the carrier concentration are designed to achieve the ideal breakdown effect without punch-through when a potential is applied between the Schottky electrode film 87 and the ohmic electrode film 89 . This provides an epitaxial substrate for a semiconductor element with improved breakdown performance.

在该外延基底81中,还可以在氮化镓外延膜85上形成p型半导体区域,在p型半导体区域中形成n型半导体区域。这样就提供了击穿性能改善的晶体管用的外延基底。In this epitaxial substrate 81, a p-type semiconductor region may be formed on the gallium nitride epitaxial film 85, and an n-type semiconductor region may be formed in the p-type semiconductor region. This provides an epitaxial substrate for transistors with improved breakdown characteristics.

图10D-10G示出外延基底的生产。如图10D和10E所示生产外延基底81。如图10F所示,p型氮化镓外延膜93层放在外延基底81上,制备外延基底91。优选用金属有机气相外延生长法生长氮化镓外延膜93。氮化镓外延膜93的载流子浓度大于氮化镓外延膜85的载流子浓度,使耗尽层主要形成在氮化镓外延膜85上。10D-10G illustrate the production of epitaxial substrates. Epitaxial substrate 81 is produced as shown in FIGS. 10D and 10E. As shown in FIG. 10F , a p-type GaN epitaxial film 93 is placed on the epitaxial substrate 81 to prepare the epitaxial substrate 91 . The gallium nitride epitaxial film 93 is preferably grown by metal organic vapor phase epitaxy. The carrier concentration of GaN epitaxial film 93 is higher than that of GaN epitaxial film 85 , so that the depletion layer is mainly formed on GaN epitaxial film 85 .

如图10G所示,欧姆电极膜95层放在外延基底91的外延膜93上,欧姆电极膜97层放在第二表面83b上。因为氮化镓外延膜85的厚度至少是5微米,但不大于1000微米,还因为氮化镓外延膜85的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3,所以可以对外延层厚度和载流子浓度进行设计,以达到在欧姆电极膜95和欧姆电极膜97之间施加电势时没有穿通的理想击穿效果。这样就提供了击穿性能改善的半导体元件用的外延基底91。As shown in FIG. 10G, an ohmic electrode film 95 layer is placed on the epitaxial film 93 of the epitaxial substrate 91, and an ohmic electrode film 97 layer is placed on the second surface 83b. Because the thickness of the GaN epitaxial film 85 is at least 5 micrometers but not more than 1000 micrometers, and because the carrier concentration of the GaN epitaxial film 85 is at least 1×10 14 cm −3 but not more than 1×10 17 cm −3 , so the thickness of the epitaxial layer and the carrier concentration can be designed to achieve the ideal breakdown effect without punch-through when a potential is applied between the ohmic electrode film 95 and the ohmic electrode film 97 . This provides epitaxial substrate 91 for semiconductor elements with improved breakdown performance.

在上述外延基底81、91中,可以用HVPE生长外延膜85,在实际可行的时间内生长厚度最大约为1000微米的外延膜。用外延基底91通过金属有机气相外延生长法可以提供高质量的外延膜。另外,使用外延基底81、91时,氮化镓独立式基底83第一表面83a的表面取向优选是(0001)面(包括结晶学上等同的面)。用这种外延基底可以提供低位错的GaN独立式基底。另外,使用外延基底81、91时,氮化镓独立式基底第一表面83a的表面取向优选在不大于(1-100)面(包括结晶学上等同的面)和(11-20)面(包括结晶学上等同的面)的+5度但至少是(1-100)面(包括结晶学上等同的面)和(11-20)面(包括结晶学上等同的面)的-5度范围内。使用外延基底81、91时,外延层中的位错下降,反向泄漏电流下降,反向击穿得以改善。In the above-mentioned epitaxial substrates 81, 91, the epitaxial film 85 can be grown by HVPE, and the epitaxial film can be grown to a thickness of about 1000 micrometers at the maximum within a practicable time. A high-quality epitaxial film can be provided by metal organic vapor phase epitaxy using the epitaxial substrate 91 . In addition, when the epitaxial substrates 81 and 91 are used, the surface orientation of the first surface 83a of the gallium nitride free-standing substrate 83 is preferably the (0001) plane (including crystallographically equivalent planes). A low-dislocation GaN free-standing substrate can be provided with this epitaxial substrate. In addition, when epitaxial substrates 81 and 91 are used, the surface orientation of the first surface 83a of the gallium nitride free-standing substrate is preferably not greater than the (1-100) plane (including crystallographically equivalent planes) and the (11-20) plane ( +5 degrees including crystallographically equivalent planes) but at least -5 degrees from (1-100) planes (including crystallographically equivalent planes) and (11-20) planes (including crystallographically equivalent planes) within range. When the epitaxial substrates 81 and 91 are used, the dislocations in the epitaxial layer are reduced, the reverse leakage current is reduced, and the reverse breakdown is improved.

图11A是示出在GaN独立式基底上高位错区域和低位错区域的一种排列的图。图11B是示出在GaN独立式基底上高位错区域和低位错区域的另一种排列的图。用于外延基底81、91的氮化镓独立式基底82的第一表面82a包括:第一区域,其上显示有具有较大螺纹位错密度的高位错区域82c;第二区域,其上显示有具有较小螺纹位错密度的低位错区域82d。高位错区域82c被低位错区域82d环绕,在第一表面82a上,第一区域无规地点状分布在第二区域中。整体螺纹位错密度例如不大于1×108cm-2。使用这些外延基底81、91时,低位错密度降低了外延层中的位错,因此,反向泄漏电流下降,反向击穿性能得以改善。FIG. 11A is a diagram showing an arrangement of high and low dislocation regions on a GaN freestanding substrate. 11B is a diagram showing another arrangement of high and low dislocation regions on a GaN freestanding substrate. The first surface 82a of the gallium nitride freestanding substrate 82 used for the epitaxial substrates 81, 91 includes: a first region on which is shown a high dislocation region 82c having a larger thread dislocation density; a second region on which is shown There is a low dislocation region 82d with a smaller thread dislocation density. The high dislocation region 82c is surrounded by the low dislocation region 82d, and on the first surface 82a, the first region is randomly distributed in the second region. The overall thread dislocation density is, for example, not greater than 1×10 8 cm -2 . When these epitaxial substrates 81, 91 are used, the low dislocation density reduces the dislocations in the epitaxial layer, therefore, the reverse leakage current is reduced and the reverse breakdown performance is improved.

在图11B所示的氮化镓独立式基底84中,第一表面84a包括:第一区域,其上显示有具有较大螺纹位错密度的高位错区域84c;第二区域,其上显示有具有较小螺纹位错密度的低位错区域84d。低位错区域82d沿高位错区域82c延伸。结果,在第一表面84a上,第一区域(条带区域)和第二区域(条带区域)交替式排列。每一个低位错区域84d与另一个低位错区域82d都被高位错区域84c隔开。In the gallium nitride freestanding substrate 84 shown in FIG. 11B , the first surface 84a includes: a first region showing a high dislocation region 84c having a larger thread dislocation density thereon; a second region showing thereon Low dislocation regions 84d with less threading dislocation density. The low dislocation region 82d extends along the high dislocation region 82c. As a result, on the first surface 84a, the first regions (stripe regions) and the second regions (stripe regions) are alternately arranged. Each low dislocation region 84d is separated from the other low dislocation region 82d by a high dislocation region 84c.

低位错区域的螺纹位错密度至少是1×108cm-2,其螺纹势密度比第一区域的位错密度高,例如至少是1×108cm-2。通过在位错密度较低的区域上形成半导体元件,外延膜中的位错可以进一步降低。结果,反向泄漏电流进一步下降,反向击穿性能得以改善。The thread dislocation density of the low dislocation region is at least 1×10 8 cm -2 , and its thread potential density is higher than that of the first region, for example at least 1×10 8 cm -2 . Dislocations in the epitaxial film can be further reduced by forming the semiconductor element on a region where the dislocation density is low. As a result, the reverse leakage current is further reduced and the reverse breakdown performance is improved.

与使用硅半导体的半导体元件相比,使用氮化镓半导体的高反向击穿电压半导体元件能够提供更高的反向击穿电压和更低的正向“接通”电阻(forward“on”resistance)。Compared with semiconductor elements using silicon semiconductors, high reverse breakdown voltage semiconductor elements using gallium nitride semiconductors can provide higher reverse breakdown voltage and lower forward "on" resistance (forward "on" resistance).

前面用优选实施方案说明了本发明的原理,但是本领域普通技术人员应当理解,在不背离本发明的这些原理的情况下可以改变这些排列和细节。本发明并不限于这些实施方案公开的具体结构。例如,实施方案中描述了常关(normal-off)晶体管,但是本发明不限于这种晶体管。因此,本发明包括权利要求书的保护范围和在权利要求书的精神范围内作出的校正和改动。The principles of the invention have been described in terms of preferred embodiments, but it will be understood by those of ordinary skill in the art that changes may be made in these arrangements and details without departing from the principles of the invention. The invention is not limited to the specific structures disclosed in these embodiments. For example, a normally-off transistor was described in the embodiment, but the present invention is not limited to this transistor. Therefore, the present invention includes the protection scope of the claims and corrections and changes made within the spirit of the claims.

Claims (19)

1、一种外延基底,其包括:1. An epitaxial substrate comprising: 氮化镓独立式基底,该基底包括第一表面和与所述第一表面相反的第二表面,并且其载流子浓度大于1×1018cm-3;和a gallium nitride free-standing substrate comprising a first surface and a second surface opposite said first surface and having a carrier concentration greater than 1×10 18 cm −3 ; and 放置在所述第一表面上的第一氮化镓外延膜;a first gallium nitride epitaxial film disposed on the first surface; 其中:in: 所述第一氮化镓外延膜的厚度至少是5微米,但不大于1000微米;且The thickness of the first gallium nitride epitaxial film is at least 5 microns but not greater than 1000 microns; and 所述第一氮化镓外延膜的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3The carrier concentration of the first gallium nitride epitaxial film is at least 1×10 14 cm -3 but not more than 1×10 17 cm -3 . 2、根据权利要求1所述的外延基底,其包括:2. The epitaxial substrate according to claim 1, comprising: 放置在所述第一氮化镓外延膜中的p型半导体区域;和a p-type semiconductor region disposed in said first gallium nitride epitaxial film; and 放置在所述p型半导体区域中的n型半导体区域;an n-type semiconductor region disposed in said p-type semiconductor region; 其中,所述第一氮化镓外延膜和所述氮化镓独立式基底具有n型导电性。Wherein, the first GaN epitaxial film and the GaN free-standing substrate have n-type conductivity. 3、根据权利要求1所述的外延基底,其还包括放置在所述第一氮化镓外延膜上并且包括p型掺杂剂的第二氮化镓外延膜。3. The epitaxial substrate of claim 1, further comprising a second gallium nitride epitaxial film disposed on the first gallium nitride epitaxial film and including a p-type dopant. 4、根据权利要求3所述的外延基底,其中,用离子注入法将所述p型掺杂剂引入。4. The epitaxial substrate according to claim 3, wherein the p-type dopant is introduced by ion implantation. 5、根据权利要求3所述的外延基底,其中,用金属有机气相外延生长法形成所述第二氮化镓外延膜。5. The epitaxial substrate according to claim 3, wherein the second gallium nitride epitaxial film is formed by a metal organic vapor phase epitaxial growth method. 6、根据权利要求1-5中任一项所述的外延基底,其中,所述氮化镓独立式基底的所述第一表面的表面取向在不大于(0001)的+5度但至少是(0001)的-5度范围内。6. The epitaxial substrate according to any one of claims 1-5, wherein the surface orientation of the first surface of the gallium nitride free-standing substrate is not more than +5 degrees of (0001) but at least (0001) within -5 degrees. 7、根据权利要求1-5中任一项所述的外延基底,其中,所述氮化镓独立式基底的所述第一表面的表面取向在不大于(1-100)或(11-20)的+5度但至少是(1-100)或(11-20)的-5度范围内。7. The epitaxial substrate according to any one of claims 1-5, wherein the surface orientation of the first surface of the gallium nitride free-standing substrate is not greater than (1-100) or (11-20 ) but at least within -5 degrees of (1-100) or (11-20). 8、根据权利要求1-7中任一项所述的外延基底,其中,所述氮化镓独立式基底的所述第一表面的位错密度不大于1×108cm-28. The epitaxial substrate according to any one of claims 1-7, wherein the dislocation density of the first surface of the gallium nitride free-standing substrate is not greater than 1×10 8 cm -2 . 9、根据权利要求1-7中任一项所述的外延基底,其中,所述氮化镓独立式基底的所述第一表面包括位错密度不大于1×108cm-2的第一区域和位错密度大于所述第一区域的所述位错密度的第二区域。9. The epitaxial substrate according to any one of claims 1-7, wherein the first surface of the gallium nitride free-standing substrate comprises a first surface with a dislocation density not greater than 1×10 8 cm -2 . A region and a second region having a dislocation density greater than the dislocation density of the first region. 10、根据权利要求1-9中任一项所述的外延基底,其中,用HVPE生长所述第一氮化镓外延膜。10. The epitaxial substrate according to any one of claims 1-9, wherein the first gallium nitride epitaxial film is grown by HVPE. 11、一种包含III族氮化物半导体元件的半导体元件,该半导体元件包括:11. A semiconductor element comprising a Group III nitride semiconductor element, the semiconductor element comprising: 氮化镓支撑底板,该底板包括第一表面和与所述第一表面相反的第二表面,并且其载流子浓度大于1×1018cm-3a gallium nitride support base plate comprising a first surface and a second surface opposite said first surface and having a carrier concentration greater than 1×10 18 cm −3 ; 放置在所述第一表面上的第一氮化镓外延层;a first gallium nitride epitaxial layer disposed on the first surface; 放置在所述第二表面上的欧姆电极;和an ohmic electrode placed on said second surface; and 放置在所述第一氮化镓外延层上的肖特基电极;a Schottky electrode disposed on said first gallium nitride epitaxial layer; 其中:in: 所述第一氮化镓外延层的厚度至少是5微米,但不大于1000微米;The thickness of the first gallium nitride epitaxial layer is at least 5 microns, but not greater than 1000 microns; 所述第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3;且The carrier concentration of the first gallium nitride epitaxial layer is at least 1×10 14 cm -3 but not greater than 1×10 17 cm -3 ; and 所述半导体元件是肖特基二极管。The semiconductor element is a Schottky diode. 12、一种包含III族氮化物半导体元件的半导体元件,该半导体元件包括:12. A semiconductor element comprising a Group III nitride semiconductor element, the semiconductor element comprising: 氮化镓支撑底板,该底板包括第一表面和与所述第一表面相反的第二表面,并且其载流子浓度大于1×1018cm-3a gallium nitride support base plate comprising a first surface and a second surface opposite said first surface and having a carrier concentration greater than 1×10 18 cm −3 ; 放置在所述第一表面上的第一氮化镓外延层;a first gallium nitride epitaxial layer disposed on the first surface; 放置在所述第二表面上的欧姆电极;an ohmic electrode placed on said second surface; 放置在所述第一氮化镓外延层上并且含有p型掺杂剂的第二氮化镓外延层;和a second epitaxial layer of gallium nitride disposed on the first epitaxial layer of gallium nitride and containing a p-type dopant; and 放置在所述第二氮化镓外延层上的欧姆电极;an ohmic electrode disposed on the second gallium nitride epitaxial layer; 其中:in: 所述氮化镓支撑底板具有n型导电性;The gallium nitride supporting base plate has n-type conductivity; 所述第一氮化镓外延层的厚度至少是5微米,但不大于1000微米;The thickness of the first gallium nitride epitaxial layer is at least 5 microns, but not greater than 1000 microns; 所述第一氮化镓外延膜的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3;且The first gallium nitride epitaxial film has a carrier concentration of at least 1×10 14 cm −3 but not more than 1×10 17 cm −3 ; and 所述半导体元件是pn结二极管。The semiconductor element is a pn junction diode. 13、一种包含III族氮化物半导体元件的半导体元件,该半导体元件包括:13. A semiconductor element comprising a Group III nitride semiconductor element, the semiconductor element comprising: 氮化镓支撑底板,该底板包括第一表面和与所述第一表面相反的第二表面,并且其载流子浓度大于1×1018cm-3a gallium nitride support base plate comprising a first surface and a second surface opposite said first surface and having a carrier concentration greater than 1×10 18 cm −3 ; 放置在所述第一表面上的第一氮化镓外延层;a first gallium nitride epitaxial layer disposed on the first surface; 放置在所述第一氮化镓外延层中的p型半导体区域;a p-type semiconductor region disposed in said first gallium nitride epitaxial layer; 放置在所述p型半导体区域中的n型半导体区域;an n-type semiconductor region disposed in said p-type semiconductor region; 放置在所述n型半导体区域上的源电极;a source electrode placed on said n-type semiconductor region; 放置在所述第二表面上的漏电极;a drain electrode placed on said second surface; 放置在所述第一氮化镓外延膜上的绝缘层;和an insulating layer disposed on said first gallium nitride epitaxial film; and 放置在所述绝缘层上的门电极;a gate electrode placed on said insulating layer; 其中:in: 所述第一氮化镓外延层的厚度至少是5微米,但不大于1000微米;The thickness of the first gallium nitride epitaxial layer is at least 5 microns, but not greater than 1000 microns; 所述第一氮化镓外延层的载流子浓度至少是1×1014cm-3,但不大于1×1017cm-3;且The carrier concentration of the first gallium nitride epitaxial layer is at least 1×10 14 cm -3 but not greater than 1×10 17 cm -3 ; and 所述半导体元件是MIS晶体管。The semiconductor element is an MIS transistor. 14、根据权利要求13所述的半导体元件,其中,用离子注入法将所述p型半导体区域的p型掺杂剂引入。14. The semiconductor element according to claim 13, wherein the p-type dopant of the p-type semiconductor region is introduced by ion implantation. 15、根据权利要求13或14所述的半导体元件,其中,用离子注入法将所述n型半导体区域的n型掺杂剂引入。15. The semiconductor element according to claim 13 or 14, wherein the n-type dopant in the n-type semiconductor region is introduced by ion implantation. 16、根据权利要求11-15中任一项所述的半导体元件,其中,所述氮化镓支撑底板的所述第一表面的表面取向在不大于(0001)的+5度但至少是(0001)的-5度范围内。16. The semiconductor element according to any one of claims 11-15, wherein the surface orientation of the first surface of the gallium nitride supporting base plate is at +5 degrees not greater than (0001) but at least ( 0001) within -5 degrees. 17、根据权利要求11-15中任一项所述的半导体元件,其中,所述氮化镓独立式基底的所述第一表面的表面取向在不大于(1-100)或(11-20)的+5度但至少是(1-100)或(11-20)的-5度范围内。17. The semiconductor device according to any one of claims 11-15, wherein the surface orientation of the first surface of the gallium nitride free-standing substrate is not greater than (1-100) or (11-20 ) but at least within -5 degrees of (1-100) or (11-20). 18、根据权利要求11-17中任一项所述的半导体元件,其中,所述氮化镓支撑底板的所述第一表面的位错密度不大于1×108cm-218. The semiconductor device according to any one of claims 11-17, wherein the dislocation density of the first surface of the gallium nitride supporting base plate is not greater than 1×10 8 cm -2 . 19、根据权利要求11-17中任一项所述的半导体元件,其中,所述氮化镓支撑底板的所述第一表面包括位错密度不大于1×108cm-2的第一区域和位错密度大于所述第一区域的所述位错密度的第二区域。19. The semiconductor device according to any one of claims 11-17, wherein the first surface of the gallium nitride supporting base comprises a first region with a dislocation density not greater than 1×10 8 cm -2 and a second region having a dislocation density greater than said dislocation density of said first region.
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